U.S. patent application number 11/257428 was filed with the patent office on 2006-02-16 for vertically mountable and alignable semiconductor device packages and assemblies including the same.
Invention is credited to Warren M. Farnworth, Larry D. Kinsman, Walter L. Moden.
Application Number | 20060033190 11/257428 |
Document ID | / |
Family ID | 21699488 |
Filed Date | 2006-02-16 |
United States Patent
Application |
20060033190 |
Kind Code |
A1 |
Kinsman; Larry D. ; et
al. |
February 16, 2006 |
Vertically mountable and alignable semiconductor device packages
and assemblies including the same
Abstract
A semiconductor device package includes a die, a package
encapsulating at least a portion of the die, and a plurality of
leads. Each lead of the plurality includes an external portion. The
external portion of each lead is substantially planar and extends
outward from a bottom edge of the package. The external portion of
each lead may be oriented in a plane that is substantially parallel
to a plane within which the die is located. A semiconductor device
including these features may be part of an assembly that also
includes an alignment device for orienting the semiconductor device
package in nonparallel relation to a substrate.
Inventors: |
Kinsman; Larry D.; (Boise,
ID) ; Moden; Walter L.; (Meridian, ID) ;
Farnworth; Warren M.; (Nampa, ID) |
Correspondence
Address: |
TRASK BRITT
P.O. BOX 2550
SALT LAKE CITY
UT
84110
US
|
Family ID: |
21699488 |
Appl. No.: |
11/257428 |
Filed: |
October 24, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10352698 |
Jan 27, 2003 |
6963128 |
|
|
11257428 |
Oct 24, 2005 |
|
|
|
09873869 |
Jun 4, 2001 |
6512290 |
|
|
10352698 |
Jan 27, 2003 |
|
|
|
09416357 |
Oct 12, 1999 |
6265773 |
|
|
09873869 |
Jun 4, 2001 |
|
|
|
09002160 |
Dec 31, 1997 |
6342731 |
|
|
09416357 |
Oct 12, 1999 |
|
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Current U.S.
Class: |
257/678 |
Current CPC
Class: |
H05K 2201/10696
20130101; Y10T 29/49121 20150115; Y10T 29/49156 20150115; H01L
2924/0002 20130101; H05K 3/301 20130101; Y10S 83/942 20130101; Y10T
29/53178 20150115; H01L 2225/107 20130101; H01L 2924/09701
20130101; H01L 2924/00 20130101; H05K 2201/10454 20130101; H01L
2924/3011 20130101; H01L 25/105 20130101; H01L 2924/0002 20130101;
Y10T 29/4913 20150115; Y10T 29/49147 20150115; Y10T 29/49169
20150115; Y10T 29/49135 20150115; Y10T 29/53174 20150115 |
Class at
Publication: |
257/678 |
International
Class: |
H01L 23/02 20060101
H01L023/02 |
Claims
1. A packaged semiconductor device, comprising: a semiconductor
die; a package encapsulating at least a portion of the
semiconductor die; and a plurality of leads, each lead of the
plurality of leads including an external portion that consists
essentially of a substantially planar element extending outward
from a bottom edge of the package, at least a portion of each lead
in communication with a bond pad of the semiconductor die.
2. The packaged semiconductor device of claim 1, wherein each lead
of the plurality of leads extends less than about one millimeter
past the bottom edge.
3. The packaged semiconductor device of claim 1, wherein each lead
of the plurality of leads extends less than about one-half
millimeter past the bottom edge.
4. The packaged semiconductor device of claim 1, wherein each lead
of the plurality of leads extends about 10 mils or less past the
bottom edge.
5. The packaged semiconductor device of claim 1, wherein a length
each lead of the plurality of leads protrudes from the bottom edge
and a thickness of each lead of the plurality of leads imparts that
lead with rigidity.
6. The packaged semiconductor device of claim 5, wherein each lead
is substantially nondeformable.
7. The packaged semiconductor device of claim 1, wherein the
external portion of each lead extends along a plane oriented
substantially parallel to a plane in which the semiconductor die is
located.
8. A packaged semiconductor device, comprising: a semiconductor
die; a package covering at least a portion of the semiconductor
die; a plurality of leads in communication with corresponding bond
pads of the semiconductor die, each lead of the plurality including
an external portion consisting essentially of a substantially
planar element extending outwardly from a single, bottom edge of
the package in a plane substantially parallel to a plane of the
semiconductor die.
9. The packaged semiconductor device of claim 8, wherein each lead
of the plurality of leads extends less than about one millimeter
past the bottom edge.
10. The packaged semiconductor device of claim 8, wherein each lead
of the plurality of leads extends less than about one-half
millimeter past the bottom edge.
11. The packaged semiconductor device of claim 8, wherein each lead
of the plurality of leads extends about 10 mils or less past the
bottom edge.
12. The packaged semiconductor device of claim 8, wherein a length
each lead of the plurality of leads protrudes from the bottom edge
and a thickness of each lead of the plurality of leads imparts that
lead with rigidity.
13. The packaged semiconductor device of claim 12, wherein each
lead is substantially nondeformable.
14. A semiconductor device assembly, comprising: at least one
semiconductor device package including: a semiconductor die; a
package covering at least a portion of the semiconductor die; and a
plurality of leads in communication with corresponding bond pads of
the semiconductor die, each lead of the plurality including an
external portion consisting essentially of a substantially planar
element protruding from a single, bottom edge of the package; and
an alignment device including a receptacle configured to removably
receive the at least one semiconductor device package in a
nonparallel orientation relative to a substrate.
15. The assembly of claim 14, wherein each lead of the plurality of
leads extends less than about one millimeter past the bottom
edge.
16. The assembly of claim 14, wherein each lead of the plurality of
leads extends less than about one-half millimeter past the bottom
edge.
17. The assembly of claim 14, wherein each lead of the plurality of
leads extends about 10 mils or less past the bottom edge.
18. The assembly of claim 14, wherein a length each lead of the
plurality of leads protrudes from the bottom edge and a thickness
of each lead of the plurality of leads imparts that lead with
rigidity.
19. The assembly of claim 14, wherein each lead of the plurality of
leads is substantially nondeformable.
20. The assembly of claim 14, wherein the at least one
semiconductor device package may be removed from the receptacle and
replaced by at least one of another semiconductor device package
and an upgrade thereof.
21. The assembly of claim 14, wherein the alignment device includes
a plurality of receptacles.
22. The assembly of claim 21, wherein at least one semiconductor
device package disposed in the receptacle is removable separately
from another semiconductor device package disposed in another
receptacle of the alignment device.
23. The assembly of claim 14, wherein the external portion of each
lead of the at least one semiconductor device package extends along
a plane oriented substantially parallel to a plane in which the
semiconductor die of the at least one semiconductor device package
is located.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of application Ser. No.
10/352,698, filed Jan. 27, 2003, pending, which is a continuation
of application Ser. No. 09/873,869, filed Jun. 4, 2001, now U.S.
Pat. No. 6,512,290, issued Jan. 28, 2003, which is a continuation
of application Ser. No. 09/416,357, filed Oct. 12, 1999, now U.S.
Pat. No. 6,265,773, issued Jul. 24, 2001, which is a continuation
of application Ser. No. 09/002,160, filed Dec. 31, 1997, now U.S.
Pat. No. 6,342,731, issued Jan. 29, 2002.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to vertically mountable
semiconductor devices and devices which orient semiconductor
devices perpendicularly relative to a carrier substrate. In
particular, this invention relates to vertical surface mount
package assemblies and alignment devices for biasing leads of the
semiconductor device against terminals on a carrier substrate to
establish and maintain electrical communication therebetween. The
present invention also relates to vertical surface mount packages
with low impedance and to user-upgradeable, vertical surface mount
package assemblies.
[0004] 2. Background of the Related Art
[0005] Vertical surface mount packages are known in the art. When
compared with traditional, horizontally mountable semiconductor
packages and horizontally oriented multi-chip packages, many
vertical surface mount packages have a superior ability to transfer
heat. Vertical surface mount packages also consume less area on a
carrier substrate than a horizontally mounted package of the same
size. Thus, many skilled individuals in the semiconductor industry
are finding vertical surface mount packages more desirable than
their traditional, horizontally mountable counterparts.
[0006] Exemplary vertical surface mount packages are disclosed in
the following U.S. Pat. Nos.: Re. 34,794 (the "'794 patent"),
issued to Warren M. Farnworth on Nov. 22, 1994; 5,444,304 (the
"'304 patent"), issued to Kouija Hara and Jun Tanabe on Aug. 22,
1995; 5,450,289, issued to Yooung D. Kweon and Min C. An on Sep.
12, 1995; 5,451,815, issued to Norio Taniguchi et al. on Sep. 19,
1995; 5,592,019, issued to Tetsuya Ueda et al. on Jan. 7, 1997; and
5,635,760, issued to Toru Ishikawa on Jun. 3, 1997.
[0007] The '794 patent discloses a vertical surface mount package
having a gull-wing, zig-zag, in-line lead configuration and a
mechanism for mounting the package to a printed circuit board (PCB)
or other carrier substrate. The force with which the package mounts
to the carrier substrate establishes a tight interference contact
between the package's leads and their corresponding terminals on
the carrier substrate.
[0008] The '304 patent describes a vertical surface mount package
which has integrally formed fins radiating therefrom. The fins of
that device facilitate the dissipation of heat away from the
device. The semiconductor device is electrically connected to the
package's leads by wire bonding. The leads of that vertical surface
mount package, which extend therefrom in an in-line configuration,
are mountable to the terminals of a carrier substrate by
soldering.
[0009] However, many of the vertical surface mount packages in the
prior art are somewhat undesirable from the standpoint that they
permanently attach to a carrier substrate. Thus, those vertical
surface mount packages are not readily user-upgradeable. Moreover,
many prior art vertical surface mount packages include relatively
long leads, which tend to increase the impedance of the leads and
reduce the overall speed of systems of which they are a part.
Similarly, the wire bonding typically used in many vertical surface
mount packages increases the impedance and reduces the overall
speed of such devices. As the speed of operation of semiconductor
devices increases, more heat is generated by the semiconductor
device, requiring greater heat transfer. Similarly, as the speed of
operation of semiconductor devices increases, it is important to
decrease the length of the leads regarding circuitry connecting the
semiconductor device to other components and thereby decrease the
impedance of the leads to increase the responsiveness of the
semiconductor device.
[0010] Vertical surface mount package sockets are also known in the
art. Vertical surface mount package sockets support one or more
vertical surface mount packages relative to a carrier substrate.
Exemplary devices are disclosed in U.S. Pat. No. 5,619,067 (the
"'067 patent"), which issued to Goh J. Sua and Chan M. Yu on Apr.
8, 1997, and U.S. Pat. No. 5,644,161 (the "'161 patent"), which
issued to Carmen D. Burns on Jul. 1, 1997. The '161 patent does not
describe the platform shown therein in any detail.
[0011] The '067 patent discloses a mechanism for vertically
mounting a plurality of vertical surface mount packages onto a
carrier substrate. A plurality of vertical surface mount packages
is installed upside-down within a cover and against one another in
a side-by-side arrangement. The cover is then inverted and attached
to the carrier substrate. Clips on each side of the cover insert
through and engage an edge of holes formed through the carrier
substrate. The downward force of the cover on the vertical surface
mount packages forces the leads against the corresponding contacts
on the carrier substrate, creating electrical contact
therebetween.
[0012] The cover of the '067 patent is somewhat undesirable for
several reasons. First, the vertical surface mount packages
illustrated by that patent have conventional, long, bent leads.
Such long leads tend to increase the impedance of such vertical
surface mount packages. Second, the cover, as described, includes
no mechanism for aligning the devices so that the corresponding
leads and carrier substrate contacts match up to each other. The
only alignment mechanism described by the '067 patent is the two
clips on the cover and the corresponding crude holes formed through
the carrier substrate. Further, in order to effectively position
the vertical surface mount packages and maintain adequate
electrical contact between the vertical surface mount packages and
the carrier substrate, the cover device of the '067 patent must be
filled to capacity with vertical surface mount packages. The
illustrated clip-hole attachment mechanism also seems inadequate
for establishing and maintaining an adequate interference contact
between the vertical surface mount package leads and the carrier
substrate contacts.
[0013] What is needed is a low impedance, vertical surface mount
package which is readily removable from and reinstallable upon a
carrier substrate. A vertical surface mount package alignment and
attachment device which transfers heat away from the vertical
surface mount package and establishes and maintains adequate
electrical connections between a vertical surface mount package and
a carrier substrate is also needed.
SUMMARY OF THE INVENTION
[0014] The vertically mountable semiconductor device assembly of
the present invention includes very short stub contacts, which
impart it with low impedance. The assembly of the present invention
includes an alignment device, which exerts consistent downward
force upon all of the vertically mountable semiconductor devices
disposed therein to establish and maintain an electrical connection
between the vertically mountable semiconductor device(s) and the
carrier substrate. Vertically mountable semiconductor devices are
readily removable from and reinstallable in the alignment device,
making the device user-upgradeable.
[0015] An embodiment of the system of the present invention
includes a vertically mountable semiconductor device and an
alignment device which attaches the vertically mountable
semiconductor device to a carrier substrate. The alignment device
of the present invention includes one or more receptacles formed
therethrough, each of which receives and aligns at least one
vertically mountable semiconductor device. The alignment device
also includes a mechanism, which is referred to as a contact
element, for biasing the vertically mountable semiconductor
device(s) disposed within the receptacle(s) against the carrier
substrate. A preferred contact element is a cover which exerts
constant force on the vertically mountable semiconductor device to
establish and maintain a connection with a carrier substrate. A
preferred engagement mechanism releasably engages the vertically
mountable semiconductor device(s) that has been inserted into the
alignment device receptacle(s).
[0016] In use, the alignment device is mounted to a carrier
substrate, one or more vertically mountable semiconductor devices
are inserted into the receptacle(s) thereof, and the contact
element engages the vertically mountable semiconductor device(s),
exerting downward force thereon to establish and maintain an
electrical connection between stub contacts on the vertically
mountable semiconductor device(s) and corresponding terminals on
the carrier substrate. Disengagement of the contact element
facilitates the ready removal of the vertically mountable
semiconductor device(s) from the alignment device. Consequently,
each vertically mountable semiconductor device is readily removable
from the receptacle and may also be readily replaced therein.
[0017] A vertically mountable semiconductor device which may be
used in the system of the present invention has a plurality of
short stub contacts extending therefrom. Preferably, the lead
length is less than about one millimeter (mm). More preferably, the
lead length is less than about one-half (1/2) mm. Shorter lead
lengths of about 10 mils or less are even more preferred due to the
decrease in impedance as lead length decreases. Thus, it is a
consequent advantage that vertically mountable semiconductor
devices which are useful in the system of the present invention
have reduced impedance.
[0018] The present invention also includes a method for fabricating
the vertically mountable semiconductor device and a method for
modifying existing vertical surface mount packages to manufacture
the vertically mountable semiconductor device of the present
invention. A computer which includes the vertically mountable
semiconductor device of the present invention is also within the
scope of the invention.
[0019] Other advantages of the present invention will become
apparent through a consideration of the appended drawings and the
ensuing description.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0020] FIG. 1a is a perspective assembly view of a first embodiment
of the vertically mountable semiconductor device assembly according
to the present invention;
[0021] FIG. 1b is a frontal perspective view of the vertically
mountable semiconductor device assembly of FIG. 1a, showing the
cover disposed on the alignment device;
[0022] FIG. 2 is a frontal perspective view of a vertically
mountable semiconductor device that is useful in the assembly of
FIG. 1a;
[0023] FIGS. 3a through 3c are cross-sectional views of exemplary
alignment device-cover combinations that are useful in the assembly
of FIG. 1a, which illustrate various embodiments of the alignment
device, the cover, the electrical connection of package stub
contacts to carrier substrate terminals, and the attachment of the
alignment device to the carrier substrate;
[0024] FIGS. 4a through 4c are cross-sectional views of exemplary
alignment device-cover combinations that are useful in the assembly
of FIG. 1a, which illustrate various mechanisms for securing the
cover to the alignment device;
[0025] FIG. 4d is a frontal perspective view of a cover and
alignment device that includes another variation of a mechanism for
securing the cover to the alignment device;
[0026] FIG. 5 is a frontal perspective view of another variation of
the cover that includes a heat sink mechanism thereon;
[0027] FIG. 6 is a frontal perspective view of another variation of
the alignment device that includes a plurality of package
receptacles; and
[0028] FIG. 7 is a schematic representation of the vertically
mountable semiconductor device assembly in a computer.
DETAILED DESCRIPTION OF THE INVENTION
[0029] With reference to FIG. 1a, a vertically mountable
semiconductor device assembly according to the present invention
includes a vertically mountable semiconductor device 10, an
alignment device 20, and a cover 30, which is also referred to as a
contact element. Alignment device 20 attaches to a carrier
substrate 40 by a substrate attachment mechanism 25. As FIG. 1b
illustrates, cover 30 is disposable over alignment device 20.
Preferably, cover 30 is removable from and replaceable upon
alignment device 20 in order to permit a user to upgrade the
vertically mountable semiconductor devices 10 installed within the
alignment device 20.
[0030] FIG. 2 depicts a vertically mountable semiconductor device
10 according to the present invention, which includes a cover 14
that encloses an integrated circuit die 11, a bottom edge 16 on the
cover, and a plurality of stub contacts 12a, 12b, 12c, etc.
extending from the bottom edge. Preferably, stub contacts 12a, 12b,
12c, etc. extend perpendicular to bottom edge 16. At least a
portion of stub contacts 12a, 12b, 12c, etc. are electrically
connected to bond pads 15 on integrated circuit die 11. The bond
pads 15, shown in phantom, are electrically connected 17, also
shown in phantom, to the stub contacts 12a, 12b, 12c, etc. Stub
contacts 12a, 12b, 12c, etc. are manufactured from materials which
are known in the art, including, without limitation, copper alloys,
iron-nickel (Fe--Ni) alloys, and iron-nickel-cobalt (Fe--Ni--Co)
alloys. Typical leads have a thickness of about 4 mils to about 10
mils. As a result of their materials and thinness, typical
semiconductor leads are compliant. Due to the compliance of typical
semiconductor leads, stub contacts 12a, 12b, 12c, etc. are
preferably very short and straight in order to reduce their
tendency to buckle as a load is placed thereon. Preferably, stub
contacts 12a, 12b, 12c, etc. (collectively referred to as "stub
contacts 12") extend from cover 14 a length of less than about 1
mm. More preferably, stub contacts 12 extend from cover 14 a length
of less than about one-half (1/2) mm. Even more preferred are stub
contact 12 lengths of about 10 mils or less. Moreover, the
relatively short length of stub contacts 12a, 12b, 12c, etc.
reduces the amount of impedance that is generated thereby and
increases the overall speed of the device of which they are a part,
relative to many vertical surface mount packages in the prior
art.
[0031] Vertically mountable semiconductor device 10 has a
standardized number of stub contacts 12a, 12b, 12c, etc., which are
spaced apart from one another at a standardized pitch, and which
may be positioned at a specific location relative to a center line
18 of the vertically mountable semiconductor device 10, or relative
to any other landmark on the vertically mountable semiconductor
device 10, such as a side thereof. Alternatively, the number and
pitch of stub contacts 12 may be nonstandardized.
[0032] Vertically mountable semiconductor device 10 may be packaged
by methods which are known in the art. However, the leads of many
vertical surface mount packages in the prior art are trimmed to a
desired length, then bent to a desired shape. In comparison, stub
contacts 12a, 12b, 12c, etc., of vertically mountable semiconductor
device 10 are merely trimmed to a short length. Thus, at least one
step is eliminated from the packaging process, which reduces the
overall manufacturing cost of the vertically mountable
semiconductor device of the present invention relative to other
vertical surface mount packages in the prior art. Additionally, due
to the reduced length of stub contacts 12a, 12b, 12c, etc. relative
to such devices, less material is required to form each lead,
further reducing the cost of vertically mountable semiconductor
device 10.
[0033] Alternatively, a vertically mountable semiconductor device
which has longer leads and/or bent leads, including many vertical
surface mount packages in the prior art, may also be used in the
assembly of the present invention.
[0034] Referring again to FIG. 1a, alignment device 20 includes one
or more receptacles 26 defined by an alignment device body 24.
Preferably, receptacles 26 extend completely through alignment
device 20. Receptacle 26 orients vertically mountable semiconductor
device 10 vertically with respect to carrier substrate 40 and
aligns stub contacts 12a, 12b, 12c, etc. relative to their
respective terminals (not shown) on the carrier substrate.
Preferably, the shape and size of receptacle 26 facilitates the
insertion and alignment of vertically mountable semiconductor
device 10. Thus, receptacle 26 is slightly larger than vertically
mountable semiconductor device 10. Alternatively, the vertically
mountable semiconductor device 10 may include a guide which
corresponds to a guide in the alignment device receptacle 26. Thus,
as the vertically mountable semiconductor device 10 is inserted
into the receptacle, the guide aligns stub contacts 12a, 12b, 12c,
etc. with respect to their corresponding terminals (not shown) on
carrier substrate 40.
[0035] Preferably, alignment device 20 is thin-walled in order to
conserve area or "real estate" on carrier substrate 40. A preferred
alignment device 20 material, such as ceramic, glass, copper,
aluminum or another "heat sink" material, has good thermal
conductivity properties. Alternatively, alignment device 20 may be
manufactured from materials such as plastics and epoxy resins.
Preferably, cover 30 is made from the same material as alignment
device 20.
[0036] As mentioned above, alignment device 20 is attached to
carrier substrate 40 with a substrate attachment mechanism 25. As
illustrated in FIG. 1a, a preferred substrate attachment mechanism
25 is a layer of z-axis elastomer. However, other mechanisms which
are known in the art are useful for attaching alignment device 20
to carrier substrate 40, including, without limitation, screws,
epoxies, acrylics, tabs and adhesives.
[0037] FIGS. 3a through 3c illustrate various embodiments of covers
and alignment devices according to another aspect of the present
invention. FIG. 3a shows a first variation of an alignment device
20 which includes a receptacle 26 extending therethrough. The
height of receptacle 26 is slightly less than that of a vertically
mountable semiconductor device 10 insertable therein. Thus, as a
corresponding first variation of a cover 30 is secured to alignment
device 20, the cover 30 exerts a downward force on vertically
mountable semiconductor device 10 to establish and maintain an
electrical contact between stub contacts 12 and their corresponding
terminals 42 on carrier substrate 40. FIG. 3a also illustrates a
substrate attachment mechanism 25, here, a thin layer of a z-axis
elastomer, which secures alignment device 20 to carrier substrate
40, and through which an electrical connection is established
between stub contacts 12 and terminals 42.
[0038] FIG. 3b depicts second variations of an alignment device 20'
and a cover 30' that are useful in the present invention. The
receptacles 26' of alignment device 20' have about the same or a
greater height than that of a vertically mountable semiconductor
device 10 insertable therein. Cover 30' includes a depressor
component 36', which exerts adequate downward force on vertically
mountable semiconductor device 10 to establish and maintain an
electrical connection between stub contacts 12 and their respective
terminals 42. Depressor component 36' is a short downward extension
of cover 30' which is adapted to insert into receptacle 26' and
apply a constant downward force on vertically mountable
semiconductor device 10. As depicted, alignment device 20' may be
secured to carrier substrate 40 with a thin layer of z-axis
elastomer or other substrate attachment mechanism 25.
[0039] FIG. 3c shows a third variation of an alignment device 20''
and a cover 30'', which are substantially the same as the alignment
device and cover described above in reference to FIG. 3a. However,
the assembly shown in FIG. 3c lacks a z-axis elastomer. Rather,
alignment device 20'' is attached to carrier substrate 40 with an
attachment mechanism 25'' which may include, but is not limited to,
screws, epoxies and adhesive materials. The downward force of cover
30'' on a vertically mountable semiconductor device 10 which has
been inserted into receptacle 26'' establishes and maintains an
interference fit between stub contacts 12, which extend from the
vertically mountable semiconductor device 10, and their respective
terminals 42 on carrier substrate 40. Thus, the downward force of
cover 30'' on vertically mountable semiconductor device 10
establishes and maintains electrical connections between each of
the stub contacts 12 and its corresponding terminal 42.
[0040] Different combinations of the alignment device, cover, and
securing mechanism, as well as variations thereof, which orient and
align a vertically mountable semiconductor device perpendicularly
relative to a carrier substrate and which establish and maintain an
electrical connection between the vertically mountable
semiconductor device's stub contacts and their respective terminals
on the carrier substrate are also contemplated to be within the
scope of the present invention.
[0041] In order to exert sufficient downward force on a vertically
mountable semiconductor device disposed within an alignment
device's receptacle, the cover must be secured to the alignment
device. FIGS. 4a through 4d illustrate various exemplary alignment
device-cover combinations and their respective securing
mechanisms.
[0042] FIG. 4a shows a preferred configuration of an alignment
device 420 and its complementary cover 430. The top 428 of
alignment device 420 is adapted to receive and engage cover 430.
Preferably, the top 428 of alignment device 420 is recessed around
the entire perimeter thereof. A shoulder 427, which extends around
the entire perimeter of alignment device 420, separates recessed
top 428 from the remainder of the alignment device. Cover 430
includes a downwardly extending perimeter, which is referred to as
lip 432. Preferably, lip 432 is shaped complementarily to recessed
top 428 of alignment device 420. Lip 432 defines a receptacle 435
in cover 430, which is adapted to receive the top 428 of alignment
device 420. Lip 432 also includes a bottom edge 436 (see FIG. 4a),
which rests upon shoulder 427 of alignment device 420 as cover 430
is disposed on the alignment device. As cover 430 is placed over
top 428 of alignment device 420, the top of the alignment device is
inserted into receptacle 435 of the cover. Preferably, when cover
430 is disposed on alignment device 420, the outer surfaces of the
sides of the alignment device and the cover are flush.
[0043] With continued reference to FIG. 4a, a first variation of a
cover engagement mechanism 429 and its corresponding alignment
device engagement mechanism 434 are shown. Recessed top 428 of
alignment device 420 includes a horizontal, elongate groove 429
(the cover engagement mechanism) formed therein. On cover 430, one
or more ridges 434 (the alignment device engagement mechanism),
which are complementary to groove 429, extend slightly into
receptacle 435 from the inner surface of lip 432. Ridge 434 is
preferably manufactured from a compressible, resilient material
such as polyurethane, silicone rubber, latex, or other resilient
thermoplastic material. Thus, as cover 430 is disposed over
alignment device 420, ridge 434 compresses as it is forced downward
along the recessed top 428 of the alignment device. When ridge 434
overlaps groove 429, the ridge expands to substantially its
original shape and size to secure itself into the groove and secure
cover 430 to alignment device 420. In order to remove cover 430
from alignment device 420, sufficient upward force must be applied
to the cover to compress ridge 434 and pull it from groove 429.
[0044] FIG. 4b illustrates a second variation of a cover engagement
mechanism 429' and its corresponding alignment device engagement
mechanism 434'. Alignment device engagement mechanism 434' includes
a plurality of protrusions which extends downwardly from lip 432'
of cover 430'. Cover engagement mechanism 429' includes a plurality
of receptacles which opens through shoulder 427' and extends
downward through the lower portion of alignment device 420'. The
receptacles of cover engagement mechanism 429' align with and are
complementary to protrusions 434'. Thus, as protrusions 434' are
inserted into the receptacles of cover engagement mechanism 429',
they mate with the receptacles and are secured thereby, securing
cover 430' to alignment device 420'.
[0045] FIG. 4c depicts a third variation of a mechanism for
securing a cover 430'' to an alignment device 420''. A plurality of
bores 434'' extends downward through lip 432'' of cover 430''. As
cover 430'' is disposed on alignment device 420'', bores 434''
align with complementary downwardly extending bores 429'' formed in
the alignment device through shoulder 427''. A securing mechanism
(not shown), such as a screw, a retaining pin, or another elongate
fastener, is then inserted into each of cover bores 434'' and their
respective alignment device bores 429'' and secured within the
alignment device bores to secure cover 430'' to alignment device
420''.
[0046] Referring to FIG. 4d, a fourth variation of an alignment
device securing mechanism is shown, wherein the cover 130 includes
a downwardly extending securing element 134. Preferably, securing
element 134 is a resilient, outwardly forcible, integrally molded
leaf spring which comprises a latch 135 near the bottom thereof.
Latch 135 faces inwardly relative to cover 130. A corresponding
receptacle 129 formed in alignment device 120 receives latch 135 as
cover 130 is placed over the alignment device. Thus, as cover 130
is placed over alignment device 120, securing element 134 is flexed
outward until latch 135 reaches receptacle 129. As latch 135
overlaps receptacle 129, securing element 134 snaps back to its
relaxed state, securing the latch 135 within the receptacle 129,
thereby securing cover 130 to alignment device 120.
[0047] Other mechanisms which secure a cover to an alignment device
are also within the scope of the present invention. Contact
elements which establish and maintain a constant bias of the
vertically mountable semiconductor device's stub contacts against
their corresponding carrier substrate leads as the vertically
mountable semiconductor device is disposed within an alignment
device, other than a cover, are also contemplated as being within
the scope of the invention. Such contact elements include, but are
not limited to, spring loaded devices, latches, levers and
snap-fit-type bosses which are part of the alignment device or
insertable therein, and which hold the vertically mountable
semiconductor device within the alignment device receptacle.
Alternative contact elements may apply downward force to the top of
a vertically mountable semiconductor device or engage a portion of
the vertically mountable semiconductor device to exert a downward
force thereupon.
[0048] FIG. 5 illustrates a cover 530 which includes a heat sink
532 thereon. As mentioned above, the cover may be made from a heat
sink material.
[0049] FIG. 6 illustrates an alternative variation 620 of the
alignment device, which includes a plurality of receptacles 626a,
626b, 626c, etc. defined thereby in a serial arrangement. Other
variations of the alignment device may include only one receptacle
or a plurality of receptacles in a matrix-type arrangement. In
variations of the alignment device which include a plurality of
receptacles, some of the receptacles may remain empty so that the
computer or other device within which the assembly of the present
invention is installed may be upgraded in the future by inserting
additional vertically mountable semiconductor devices into the
empty receptacles. Alternatively, each of the receptacles of such
multi-receptacle alignment devices may include a vertically
mountable semiconductor device.
[0050] FIG. 7 depicts a computer 700 which includes a carrier
substrate 710 therein. Alignment device 20, which includes one or
more vertically mountable semiconductor devices (not shown)
disposed therein, is attached to carrier substrate 710. A cover 30
is disposed over alignment device 20 to establish and maintain an
electrical connection between the vertically mountable
semiconductor device(s) and carrier substrate 710. Thus, the
vertically mountable semiconductor device(s) is (are) operatively
incorporated into computer 700.
[0051] Referring again to FIG. 1a, in use, alignment device 20 is
mounted to carrier substrate 40 with an attachment mechanism 25.
One or more vertically mountable semiconductor devices 10 are
inserted into receptacle(s) 26 of alignment device 20. A contact
element, such as cover 30, is disposed against vertically mountable
semiconductor device(s) 10 to bias the vertically mountable
semiconductor devices against carrier substrate 40. Cover 30 exerts
sufficient force on vertically mountable semiconductor device(s) 10
to establish and maintain an electrical connection between stub
contacts 12 and their corresponding terminals (not shown) on
carrier substrate 40. Disengagement of cover 30 facilitates the
ready removal of the vertically mountable semiconductor device(s)
10 from alignment device 20. Consequently, each vertically
mountable semiconductor device 10 is readily removable from
receptacle 26 and may also be readily replaced therein.
[0052] The features of the vertically mountable semiconductor
device and alignment device of the present invention provide
several advantages over many vertically mountable semiconductor
devices in the prior art. First, the vertically mountable
semiconductor device includes short stub contacts. Consequently,
the vertically mountable semiconductor device has relatively low
impedance when compared with many vertically mountable
semiconductor devices in the prior art. Second, the alignment
device and removable cover of the present invention establish an
electrical connection between a vertically mountable semiconductor
device and a carrier substrate. Such electrical connections are
preferably made by a z-axis elastomer or interference fit, both of
which are readily disconnected. Advantageously, the assembly of the
present invention is readily user-upgradeable. Moreover, vertically
mountable semiconductor devices are readily installable within the
alignment device, and a cover or other mechanism forces the
vertically mountable semiconductor device against a carrier
substrate to effect an operative connection between the vertically
mountable semiconductor device and the carrier substrate. Thus, the
assembly establishes and maintains adequate electrical connections
between the vertically mountable semiconductor device and the
carrier substrate.
[0053] Although the foregoing description contains many
specificities, these should not be construed as limiting the scope
of the present invention, but merely as providing illustrations of
selected presently preferred embodiments. Similarly, other
embodiments of the invention may be devised which do not depart
from the spirit or scope of the present invention. The scope of
this invention is, therefore, indicated and limited only by the
appended claims and their legal equivalents, rather than by the
foregoing description. All additions, deletions and modifications
to the invention as disclosed herein which fall within the meaning
and scope of the claims are embraced within their scope.
* * * * *