U.S. patent application number 10/899215 was filed with the patent office on 2006-01-26 for nitride-based transistors having laterally grown active region and methods of fabricating same.
Invention is credited to Adam William Saxler, Scott Sheppard, Richard Peter Smith.
Application Number | 20060017064 10/899215 |
Document ID | / |
Family ID | 34964204 |
Filed Date | 2006-01-26 |
United States Patent
Application |
20060017064 |
Kind Code |
A1 |
Saxler; Adam William ; et
al. |
January 26, 2006 |
Nitride-based transistors having laterally grown active region and
methods of fabricating same
Abstract
High electron mobility transistors and/or methods of fabricating
high electron mobility transistors that include a first Group
III-nitride layer having vertically grown regions, laterally grown
regions and a coalescence region are provided. A Group III-nitride
channel layer is provided on the first Group III-nitride layer and
a Group III-nitride barrier layer is provided on the Group
III-nitride channel layer. A drain contact, a source contact and a
gate contact are provided on the barrier layer. The gate contact is
disposed on a portion of the barrier layer on a laterally grown
region of the first Group III-nitride layer and at least a portion
of one of the source contact and/or the drain contact is disposed
on a portion of the barrier layer on a vertically grown region of
the first Group III-nitride layer.
Inventors: |
Saxler; Adam William;
(Durham, NC) ; Sheppard; Scott; (Chapel Hill,
NC) ; Smith; Richard Peter; (Carrboro, NC) |
Correspondence
Address: |
MYERS BIGEL SIBLEY & SAJOVEC
PO BOX 37428
RALEIGH
NC
27627
US
|
Family ID: |
34964204 |
Appl. No.: |
10/899215 |
Filed: |
July 26, 2004 |
Current U.S.
Class: |
257/194 ;
257/E21.407; 257/E29.253 |
Current CPC
Class: |
H01L 29/2003 20130101;
H01L 29/7787 20130101; H01L 29/66462 20130101 |
Class at
Publication: |
257/194 |
International
Class: |
H01L 29/739 20060101
H01L029/739 |
Claims
1. A high electron mobility transistor, comprising: a first Group
III-nitride layer having vertically grown regions, laterally grown
regions between adjacent vertically grown regions and a coalescence
region between adjacent laterally grown regions; a Group
III-nitride channel layer on the first Group III-nitride layer; a
Group III-nitride barrier layer on the Group III-nitride channel
layer; a drain contact on the barrier layer; a source contact on
the barrier layer; a gate contact on the barrier layer; and wherein
the gate contact is disposed on a portion of the barrier layer on a
laterally grown region of the first Group III-nitride layer and at
least a portion of one of the source contact and/or the drain
contact is disposed on a portion of the barrier layer on a
vertically grown region of the first Group III-nitride layer.
2. The transistor of claim 1, wherein the laterally grown region on
which the gate contact is disposed extends toward the drain contact
at least as far as a depletion region of a two-dimensional electron
gas extends from the gate contact under expected operating
conditions.
3. The transistor of claim 1, wherein the laterally grown region on
which the gate contact is disposed extends toward the drain contact
at least as far as a point where a strength of an electric field is
50% of a strength of an electric field at a drain side edge of the
gate contact under expected operating conditions.
4. The transistor of claim 1, wherein the laterally grown region on
which the gate contact is disposed extends toward the drain contact
at least as far as a point where a strength of an electric field is
an order of magnitude less than a strength of an electric field at
a drain side edge of the gate contact under expected operating
conditions.
5. The transistor of claim 1, wherein the laterally grown region on
which the gate contact is disposed extends toward the drain contact
at least as far as a point where a strength of an electric field is
two orders of magnitude less than a strength of an electric field
at a drain side edge of the gate contact under expected operating
conditions.
6. The transistor of claim 1, wherein the laterally grown region on
which the gate contact is disposed extends toward the drain contact
but not to the drain contact such that the drain contact is
disposed on a vertically grown region of the first Group
III-nitride layer.
7. The transistor of claim 1, wherein the laterally grown region on
which the gate contact is disposed extends to but not beyond the
drain contact.
8. The transistor of claim 1, wherein the laterally grown region on
which the gate contact is disposed extends beyond an edge of the
drain contact such that at least a portion of the drain contact is
disposed on the laterally grown region on which the gate contact is
disposed.
9. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and wherein a second laterally
grown region adjacent the first laterally grown region on which the
gate contact is disposed extends toward the drain contact but not
to the drain contact such that the drain contact is disposed on a
vertically grown region of the first Group III-nitride layer.
10. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and wherein a second laterally
grown region adjacent the first laterally grown region on which the
gate contact is disposed extends to but not beyond the drain
contact.
11. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and wherein a second laterally
grown region adjacent the first laterally grown region on which the
gate contact is disposed extends beyond an edge of the drain
contact such that at least a portion of the drain contact is
disposed on the second laterally grown region.
12. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and a second laterally grown
region adjacent the first laterally grown region and the second
laterally grown region extends toward the drain contact but not to
the drain contact such that the drain contact is disposed on a
vertically grown region of the first Group III-nitride layer.
13. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and a second laterally grown
region adjacent the first laterally grown region and the second
laterally grown region extends to but not beyond the drain
contact.
14. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and a second laterally grown
region adjacent the first laterally grown region and the second
laterally grown region extends beyond an edge of the drain contact
such that at least a portion of the drain contact is disposed on
the second laterally grown region.
15. The transistor of claim 1, wherein the source contact is
disposed on the barrier layer to extend across the coalescence
region of the first Group III-nitride layer so as to bridge between
two laterally grown regions of the first Group III-nitride
layer.
16. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and wherein a portion of the
source contact is disposed on a second laterally grown region
adjacent the first laterally grown region.
17. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and wherein the source contact
extends to but not beyond a second laterally grown region adjacent
the first laterally grown region.
18. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and wherein the source contact
does not extend to a second laterally grown region adjacent the
first laterally grown region such that the source contact is
disposed on a vertically grown region of the first Group
III-nitride layer.
19. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and a second laterally grown
region adjacent the first laterally grown region and wherein a
portion of the source contact is disposed on the second laterally
grown region.
20. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and a second laterally grown
region adjacent the first laterally grown region and wherein the
source contact extends to but not beyond the second laterally grown
region.
21. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and a second laterally grown
region adjacent the first laterally grown region and wherein the
source contact does not extend to the second laterally grown region
such that the source contact is disposed on a vertically grown
region of the first Group III-nitride layer.
22. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and a second laterally grown
region adjacent the first laterally grown region extends from the
first laterally grown region toward the drain contact and wherein a
portion of the source contact is disposed on the first laterally
grown region.
23. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and a second laterally grown
region adjacent the first laterally grown region extends from the
first laterally grown region toward the drain contact and wherein
the source contact extends to but not beyond the first laterally
grown region.
24. The transistor of claim 1, wherein the gate contact is disposed
on a first laterally grown region and a second laterally grown
region adjacent the first laterally grown region extends from the
first laterally grown region toward the drain contact and wherein
the source contact does not extend to the first laterally grown
region such that the source contact is disposed on a vertically
grown region of the first Group III-nitride layer.
25. The transistor of claim 1, wherein the first Group III-nitride
layer is semi-insulating or insulating.
26. The transistor of claim 1, wherein the laterally grown region
on which the gate contact is provided extends from beneath the
source contact to beneath the drain contact.
27. The transistor of claim 1, wherein the laterally grown region
on which the gate contact is provided extends from beneath the gate
contact to beneath the drain contact.
28. The transistor of claim 1, wherein the laterally grown region
on which the gate contact is provided extends from beneath the gate
contact toward but not to beneath the drain contact.
29. The transistor of claim 1, wherein the laterally grown region
on which the gate contact is provided extends from beneath the
source contact toward but not to beneath the drain contact.
30. The transistor of claim 1, wherein the laterally grown region
on which the gate contact is provided extends a majority of the
distance from source contact to the drain contact.
31. The transistor of claim 1, further comprising a substrate,
wherein the first Group III-nitride layer is provided on the
substrate.
32. The transistor of claim 31, wherein the substrate includes a
trench and wherein the laterally grown regions extend over the
trench.
33. The transistor of claim 32, wherein the substrate comprises a
silicon carbide substrate and wherein the trench extends
perpendicular or parallel to a crystal plane of the silicon carbide
substrate.
34. The transistor of claim 33, wherein the crystal plane of the
silicon carbide substrate is a plane in the {11{overscore (2)}0}
family of planes or the {10{overscore (1)}0} family of planes.
35. The transistor of claim 32, further comprising a mask layer in
the trench.
36. The transistor of claim 31, further comprising a mask pattern
on the substrate and wherein the laterally grown regions extend
over the mask pattern.
37. The transistor of claim 33, wherein the laterally grown regions
have substantially vertical growth sidewalls.
38. The transistor of claim 33, wherein the laterally grown regions
have trapezoidal growth sidewalls.
39. The transistor of claim 1, wherein the first Group III-nitride
layer comprises a gallium nitride layer having deep level
impurities therein.
40. The transistor of claim 39, wherein the deep level impurity
comprises Fe.
41. The transistor of claim 1, wherein the source contact, the gate
contact and the drain contact each comprise a plurality of contact
fingers and wherein the laterally grown regions comprise a
plurality of laterally grown regions separated by vertically grown
regions, where each gate contact finger is provided on a
corresponding one of the plurality of laterally grown regions.
42. The transistor of claim 32, wherein the trench comprises a
plurality of trenches, the source contact, the gate contact and the
drain contact each comprise a plurality of contact fingers and
where each gate contact finger is disposed above a corresponding
one of the plurality of trenches.
43. A semiconductor device, comprising: a silicon carbide die
having a Group III-nitride layer thereon, the Group III-nitride
layer having at least one vertically grown region and at least one
laterally grown region; at least one Group III-nitride transistor
on the silicon carbide die; and wherein the at least one laterally
grown region does not extend substantially beyond a region of the
silicon carbide die corresponding to the at least one Group
III-nitride transistor.
44. The semiconductor device of claim 43, wherein the at least one
Group III-nitride transistor comprises a plurality of gate fingers
and wherein the at least one laterally grown region comprises a
plurality of laterally grown regions disposed beneath respective
ones of the gate fingers of the at least on Group III-nitride
transistor.
45. The semiconductor device of claim 43, wherein the at least one
Group III-nitride transistor comprises a plurality Group-III
nitride transistors and wherein the at least one laterally grown
region comprises a plurality of laterally grown regions
corresponding to respective ones of the plurality of Group
III-nitride transistors.
46. The semiconductor device of claim 43, wherein the silicon
carbide die comprises a portion of a silicon carbide wafer.
47. The semiconductor device of claim 46, wherein the silicon
carbide wafer includes a major flat and wherein the at least one
laterally grown region has a boundary with a vertically grown
region that is perpendicular or parallel to the major flat.
48. The semiconductor device of claim 43, wherein the at least one
Group III-nitride transistor comprises a gallium nitride-based high
electron mobility transistor (HEMT).
49. The semiconductor device of claim 43, further comprising at
least one Group TIT-nitride transistor on the silicon carbide die
in a region of the die other than the region of the die with the at
least one laterally grown region.
50. The semiconductor device of claim 43, further comprising at
least one capacitor, resistor and/or inductor on the silicon
carbide die in a region of the die other than the region of the die
with the at least one laterally grown region.
52. The semiconductor device of claim 43, wherein the at least one
laterally grown region has a boundary with a vertically grown
region that is aligned perpendicular or parallel to a crystal plane
of the silicon carbide substrate.
53. The semiconductor device of claim 52, wherein the crystal plane
of the silicon carbide substrate is a plane in the {11{overscore
(2)}0} family of planes or the {10{overscore (1)}0} family of
planes.
54. A method of fabricating a transistor, comprising: forming a
first Group III-nitride layer having vertically grown regions,
laterally grown regions between adjacent vertically grown regions
and a coalescence region between adjacent laterally grown regions;
forming a Group III-nitride channel layer on the first Group
III-nitride layer; forming a Group III-nitride barrier layer on the
Group III-nitride channel layer; forming a drain contact and a
source contact on the barrier layer; forming a gate contact on the
barrier layer; and wherein the gate contact is formed to be
disposed on a portion of the barrier layer on a laterally grown
region of the first Group III-nitride layer and at least a portion
of one of the source contact and/or the drain contact is disposed
on a portion of the barrier layer on a vertically grown region of
the first Group III-nitride layer.
55. The method of claim 54, wherein the laterally grown region on
which the gate contact is disposed extends toward the drain contact
at least as far as a depletion region of a two-dimensional electron
gas extends from the gate contact under expected operating
conditions.
56. The method of claim 54, wherein the laterally grown region on
which the gate contact is disposed extends toward the drain contact
at least as far as a point where a strength of an electric field is
50% of a strength of an electric field at a drain side edge of the
gate contact under expected operating conditions.
57. The method of claim 54, wherein the laterally grown region on
which the gate contact is disposed extends toward the drain contact
at least as far as a point where a strength of an electric field is
an order of magnitude less than a strength of an electric field at
a drain side edge of the gate contact under expected operating
conditions.
58. The method of claim 54, wherein the laterally grown region on
which the gate contact is disposed extends toward the drain contact
at least as far as a point where a strength of an electric field is
two orders of magnitude less than a strength of an electric field
at a drain side edge of the gate contact under expected operating
conditions.
59. The method of claim 54, wherein the laterally grown region on
which the gate contact is disposed extends toward the drain contact
but not to the drain contact such that the drain contact is
disposed on a vertically grown region of the first Group
III-nitride layer.
60. The method of claim 54, wherein the laterally grown region on
which the gate contact is disposed extends to but not beyond the
drain contact.
61. The method of claim 54, wherein the laterally grown region on
which the gate contact is disposed extends beyond an edge of the
drain contact such that at least a portion of the drain contact is
disposed on the laterally grown region on which the gate contact is
disposed.
62. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and wherein a second laterally grown
region adjacent the first laterally grown region on which the gate
contact is disposed extends toward the drain contact but not to the
drain contact such that the drain contact is disposed on a
vertically grown region of the first Group III-nitride layer.
63. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and wherein a second laterally grown
region adjacent the first laterally grown region on which the gate
contact is disposed extends to but not beyond the drain
contact.
64. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and wherein a second laterally grown
region adjacent the first laterally grown region on which the gate
contact is disposed extends beyond an edge of the drain contact
such that at least a portion of the drain contact is disposed on
the second laterally grown region.
65. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and a second laterally grown region
adjacent the first laterally grown region and the second laterally
grown region extends toward the drain contact but not to the drain
contact such that the drain contact is disposed on a vertically
grown region of the first Group III-nitride layer.
66. The method claim 54, wherein the gate contact is disposed on a
first laterally grown region and a second laterally grown region
adjacent the first laterally grown region and the second laterally
grown region extends to but not beyond the drain contact.
67. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and a second laterally grown region
adjacent the first laterally grown region and the second laterally
grown region extends beyond an edge of the drain contact such that
at least a portion of the drain contact is disposed on the second
laterally grown region.
68. The method of claim 54, wherein the source contact is disposed
on the barrier layer to extend across the coalescence region of the
first Group III-nitride layer so as to bridge between two laterally
grown regions of the first Group III-nitride layer.
69. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and wherein a portion of the source
contact is disposed on a second laterally grown region adjacent the
first laterally grown region.
70. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and wherein the source contact
extends to but not beyond a second laterally grown region adjacent
the first laterally grown region.
71. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and wherein the source contact does
not extend to a second laterally grown region adjacent the first
laterally grown region such that the source contact is disposed on
a vertically grown region of the first Group III-nitride layer.
72. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and a second laterally grown region
adjacent the first laterally grown region and wherein a portion of
the source contact is disposed on the second laterally grown
region.
73. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and a second laterally grown region
adjacent the first laterally grown region and wherein the source
contact extends to but not beyond the second laterally grown
region.
74. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and a second laterally grown region
adjacent the first laterally grown region and wherein the source
contact does not extend to the second laterally grown region such
that the source contact is disposed on a vertically grown region of
the first Group III-nitride layer.
75. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and a second laterally grown region
adjacent the first laterally grown region extends from the first
laterally grown region toward the drain contact and wherein a
portion of the source contact is disposed on the first laterally
grown region.
76. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and a second laterally grown region
adjacent the first laterally grown region extends from the first
laterally grown region toward the drain contact and wherein the
source contact extends to but not beyond the first laterally grown
region.
77. The method of claim 54, wherein the gate contact is disposed on
a first laterally grown region and a second laterally grown region
adjacent the first laterally grown region extends from the first
laterally grown region toward the drain contact and wherein the
source contact does not extend to the first laterally grown region
such that the source contact is disposed on a vertically grown
region of the first Group III-nitride layer.
78. The method of claim 54, wherein the first Group III-nitride
layer is semi-insulating or insulating.
79. The method of claim 78, wherein forming a first Group
III-nitride layer comprises forming a GaN based layer incorporated
deep level dopants.
80. The method of claim 79, wherein the deep level dopants comprise
Fe.
81. The method of claim 54, wherein the laterally grown region on
which the gate contact is provided extends from beneath the source
contact to beneath the drain contact.
82. The method of claim 54, wherein the laterally grown region on
which the gate contact is provided extends from beneath the gate
contact to beneath the drain contact.
83. The method of claim 54, wherein the laterally grown region on
which the gate contact is provided extends from beneath the gate
contact toward but not to beneath the drain contact.
84. The method of claim 54, wherein the laterally grown region on
which the gate contact is provided extends from beneath the source
contact toward but not to beneath the drain contact.
85. The method of claim 54, wherein the laterally grown region on
which the gate contact is provided extends a majority of the
distance from source contact to the drain contact.
86. The method of claim 54, wherein the first Group III-nitride
layer is provided on a substrate, the method further comprising
forming a trench in the substrate and wherein the laterally grown
regions extend over the trench.
87. The method of claim 86, wherein the substrate comprises a
silicon carbide substrate and wherein forming a trench comprises
forming a trench that extends perpendicular or parallel to a
crystal plane of the silicon carbide substrate.
88. The method of claim 87, wherein the crystal plane of the
silicon carbide substrate is a plane in the {11{overscore (2)}0}
family of planes or the {10{overscore (1)}0} family of planes.
89. The method of claim 86, further comprising forming a mask layer
in the trench.
90. The method of claim 87, wherein the laterally grown regions
have substantially vertical growth sidewalls.
91. The method of claim 87, wherein the laterally grown regions
have trapezoidal growth sidewalls.
92. The method of claim 54, wherein the first Group III-nitride
layer is provided on a substrate, the method further comprising
forming a mask pattern on the substrate and wherein forming a first
Group III-nitride layer comprises forming a first Group III-nitride
layer on the substrate and the mask pattern such that the laterally
grown regions extend over the mask pattern.
93. The method of claim 54, wherein the source contact, the gate
contact and the drain contact each comprise a plurality of contact
fingers and wherein the laterally grown regions comprise a
plurality of laterally grown regions separated by vertically grown
regions, where each gate contact finger is provided on a
corresponding one of the plurality of laterally grown regions.
94. The method of claim 86, wherein the trench comprises a
plurality of trenches, the source contact, the gate contact and the
drain contact each comprise a plurality of contact fingers and
where each gate contact finger is disposed above a corresponding
one of the plurality of trenches.
95. A method of fabricating a semiconductor device, comprising:
forming a Group III-nitride layer on a silicon carbide die, the
Group III-nitride layer having at least one vertically grown region
and at least one laterally grown region; forming at least one Group
III-nitride transistor on the silicon carbide die; and wherein the
at least one laterally grown region does not extend substantially
beyond a region of the silicon carbide die corresponding to the at
least one Group III-nitride transistor.
96. The method of claim 95, wherein the at least one Group
III-nitride transistor comprises a plurality of gate fingers and
wherein the at least one laterally grown region comprises a
plurality of laterally grown regions disposed beneath respective
ones of the gate fingers of the at least on Group III-nitride
transistor.
97. The method of claim 95, wherein the at least one Group
III-nitride transistor comprises a plurality Group-Ill nitride
transistors and wherein the at least one laterally grown region
comprises a plurality of laterally grown regions corresponding to
respective ones of the plurality of Group III-nitride
transistors.
98. The method of claim 95, wherein the silicon carbide die
comprises a portion of a silicon carbide wafer.
99. The method of claim 98, wherein the silicon carbide wafer
includes a major flat and wherein the at least one laterally grown
region has a boundary with a vertically grown region that is
perpendicular or parallel to the major flat.
100. The method of claim 95, wherein the at least one Group
III-nitride transistor comprises a gallium nitride-based high
electron mobility transistor (HEMT).
101. The method of claim 95, further comprising forming at least
one Group III-nitride transistor on the silicon carbide die in a
region of the die other than the region of the die with the at
least one laterally grown region.
102. The method of claim 95, further forming comprising at least
one capacitor, resistor and/or inductor on the silicon carbide die
in a region of the die other than the region of the die with the at
least one laterally grown region.
103. The method of claim 95, wherein the at least one laterally
grown region has a boundary with a vertically grown region that is
aligned perpendicular or parallel to a crystal plane of the silicon
carbide substrate.
104. The method of claim 102, wherein the crystal plane of the
silicon carbide substrate is a plane in the {11{overscore (2)}0}
family of planes or the {10{overscore (1)}0} family of planes.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to semiconductor devices and,
more particularly, to transistors that incorporate nitride-based
active layers.
BACKGROUND
[0002] The present invention relates to transistors formed of
semiconductor materials that can make them suitable for high power,
high temperature, and/or high frequency applications. Materials
such as silicon (Si) and gallium arsenide (GaAs) have found wide
application in semiconductor devices for lower power and (in the
case of Si) lower frequency applications. These, more familiar,
semiconductor materials may not be well suited for higher power
and/or high frequency applications, however, because of their
relatively small bandgaps (e.g., 1.12 eV for Si and 1.42 for GaAs
at room temperature) and/or relatively small breakdown
voltages.
[0003] In light of the difficulties presented by Si and GaAs,
interest in high power, high temperature and/or high frequency
applications and devices has turned to wide bandgap semiconductor
materials such as silicon carbide (2.996 eV for alpha SiC at room
temperature) and the Group III nitrides (e.g., 3.36 eV for GaN at
room temperature). These materials, typically, have higher electric
field breakdown strengths and higher electron saturation velocities
as compared to gallium arsenide and silicon.
[0004] A device of particular interest for high power and/or high
frequency applications is the High Electron Mobility Transistor
(HEMT), which is also known as a modulation doped field effect
transistor (MODFET). These devices may offer operational advantages
under a number of circumstances because a two-dimensional electron
gas (2DEG) is formed at the heterojunction of two semiconductor
materials with different bandgap energies, and where the smaller
bandgap material has a higher electron affinity. The 2DEG is an
accumulation layer in the undoped ("unintentionally doped"),
smaller bandgap material and can contain a very high sheet electron
concentration in excess of, for example, 10.sup.13
carriers/cm.sup.2. Additionally, electrons that originate in the
wider-bandgap semiconductor transfer to the 2DEG, allowing a high
electron mobility due to reduced ionized impurity scattering.
[0005] This combination of high carrier concentration and high
carrier mobility can give the HEMT a very large transconductance
and may provide a strong performance advantage over
metal-semiconductor field effect transistors (MESFETs) for
high-frequency applications.
[0006] High electron mobility transistors fabricated in the gallium
nitride/aluminum gallium nitride (GaN/AlGaN) material system have
the potential to generate large amounts of radio frequency (RF)
power because of the combination of material characteristics that
includes the aforementioned high breakdown fields, their wide
bandgaps, large conduction band offset, and/or high saturated
electron drift velocity. A major portion of the electrons in the
2DEG is attributed to polarization in the AlGaN.
[0007] HEMTs in the GaN/AlGaN system have already been
demonstrated. U.S. Pat. Nos. 5,192,987 and 5,296,395 describe
AlGaN/GaN HEMT structures and methods of manufacture. U.S. Pat. No.
6,316,793, to Sheppard et al., which is commonly assigned and is
incorporated herein by reference, describes a HEMT device having a
semi-insulating silicon carbide substrate, an aluminum nitride
buffer layer on the substrate, an insulating gallium nitride layer
on the buffer layer, an aluminum gallium nitride barrier layer on
the gallium nitride layer, and a passivation layer on the aluminum
gallium nitride active structure.
SUMMARY OF THE INVENTION
[0008] Some embodiments of the present invention provide high
electron mobility transistors and/or methods of fabricating high
electron mobility transistors that include a first Group
III-nitride layer having vertically grown regions, laterally grown
regions and a coalescence region. A Group III-nitride channel layer
is provided on the first Group III-nitride layer and a Group
III-nitride barrier layer is provided on the Group III-nitride
channel layer. A drain contact, a source contact and a gate contact
are provided on the barrier layer. The gate contact is disposed on
a portion of the barrier layer on a laterally grown region of the
first Group III-nitride layer and at least a portion of one of the
source contact and/or the drain contact is disposed on a portion of
the barrier layer on a vertically grown region of the first Group
III-nitride layer.
[0009] In further embodiments of the present invention, the
laterally grown region on which the gate contact is disposed
extends toward the drain contact at least as far as a depletion
region of a two-dimensional electron gas extends from the gate
contact under expected operating conditions. The laterally grown
region on which the gate contact is disposed may extend toward the
drain contact at least as far as a point where a strength of an
electric field is 50% of a strength of an electric field at a drain
side edge of the gate contact under expected operating conditions.
The laterally grown region on which the gate contact is disposed
may extend toward the drain contact at least as far as a point
where a strength of an electric field is an order of magnitude less
than a strength of an electric field at a drain side edge of the
gate contact under expected operating conditions. The laterally
grown region on which the gate contact is disposed may extend
toward the drain contact at least as far as a point where a
strength of an electric field is two orders of magnitude less than
a strength of an electric field at a drain side edge of the gate
contact under expected operating conditions.
[0010] In additional embodiments of the present invention, the
laterally grown region on which the gate contact is disposed
extends toward the drain contact but not to the drain contact such
that the drain contact is disposed on a vertically grown region of
the first Group III-nitride layer. Furthermore, the source contact
may be disposed on the barrier layer to extend across the
coalescence region of the first Group III-nitride layer so as to
bridge between two laterally grown regions of the first Group
III-nitride layer. The first Group III-nitride layer may be
semi-insulating or insulating.
[0011] In still further embodiments of the present invention, the
laterally grown region on which the gate contact is provided
extends from beneath the source contact to beneath the drain
contact. In other embodiments of the present invention, the
laterally grown region on which the gate contact is provided
extends from beneath the gate contact to beneath the drain contact.
In additional embodiments, the laterally grown region on which the
gate contact is provided may extend from beneath the gate contact
toward but not to beneath the drain contact. In some embodiments,
the laterally grown region on which the gate contact is provided
may extend from beneath the source contact toward but not to
beneath the drain contact. In some embodiments of the present
invention, the laterally grown region on which the gate contact is
provided extends a majority of the distance from source contact to
the drain contact.
[0012] In some embodiments of the present invention, the laterally
grown region on which the gate contact is disposed extends toward
the drain contact but not to the drain contact such that the drain
contact is disposed on a vertically grown region of the first Group
III-nitride layer. In other embodiments, the laterally grown region
on which the gate contact is disposed extends to but not beyond the
drain contact. In still further embodiments, the laterally grown
region on which the gate contact is disposed extends beyond an edge
of the drain contact such that at least a portion of the drain
contact is disposed on the laterally grown region on which the gate
contact is disposed.
[0013] In additional embodiments of the present invention, the gate
contact is disposed on a first laterally grown region and a second
laterally grown region adjacent the first laterally grown region on
which the gate contact is disposed extends toward the drain contact
but not to the drain contact such that the drain contact is
disposed on a vertically grown region of the first Group
III-nitride layer. In further embodiments, the gate contact is
disposed on a first laterally grown region and a second laterally
grown region adjacent the first laterally grown region on which the
gate contact is disposed extends to but not beyond the drain
contact. In still further embodiments, the gate contact is disposed
on a first laterally grown region and a second laterally grown
region adjacent the first laterally grown region on which the gate
contact is disposed extends beyond an edge of the drain contact
such that at least a portion of the drain contact is disposed on
the second laterally grown region.
[0014] In other embodiments of the present invention, the gate
contact is disposed on a first laterally grown region and a second
laterally grown region adjacent the first laterally grown region
and the second laterally grown region extends toward the drain
contact but not to the drain contact such that the drain contact is
disposed on a vertically grown region of the first Group
III-nitride layer. In further embodiments, the gate contact is
disposed on a first laterally grown region and a second laterally
grown region adjacent the first laterally grown region and the
second laterally grown region extends to but not beyond the drain
contact. In some embodiments, the gate contact is disposed on a
first laterally grown region and a second laterally grown region
adjacent the first laterally grown region and the second laterally
grown region extends beyond an edge of the drain contact such that
at least a portion of the drain contact is disposed on the second
laterally grown region.
[0015] In yet further embodiments of the present invention, the
gate contact is disposed on a first laterally grown region and a
portion of the source contact is disposed on a second laterally
grown region adjacent the first laterally grown region. In
additional embodiments, the gate contact is disposed on a first
laterally grown region and the source contact extends to but not
beyond a second laterally grown region adjacent the first laterally
grown region. In other embodiments, the gate contact is disposed on
a first laterally grown region and the source contact does not
extend to a second laterally grown region adjacent the first
laterally grown region such that the source contact is disposed on
a vertically grown region of the first Group III-nitride layer.
[0016] In some embodiments of the present invention, the gate
contact is disposed on a first laterally grown region and a second
laterally grown region adjacent the first laterally grown region
and a portion of the source contact is disposed on the second
laterally grown region. In other embodiments, the gate contact is
disposed on a first laterally grown region and a second laterally
grown region adjacent the first laterally grown region and the
source contact extends to but not beyond the second laterally grown
region. In still further embodiments, the gate contact is disposed
on a first laterally grown region and a second laterally grown
region adjacent the first laterally grown region and the source
contact does not extend to the second laterally grown region such
that the source contact is disposed on a vertically grown region of
the first Group III-nitride layer.
[0017] In additional embodiments of the present invention, the gate
contact is disposed on a first laterally grown region and a second
laterally grown region adjacent the first laterally grown region
extends from the first laterally grown region toward the drain
contact. A portion of the source contact is disposed on the first
laterally grown region. In further embodiments, the source contact
extends to but not beyond the first laterally grown region. In
still further embodiments, the source contact does not extend to
the first laterally grown region such that the source contact is
disposed on a vertically grown region of the first Group
III-nitride layer.
[0018] In still further embodiments of the present invention, the
transistor further includes a substrate and the first Group
III-nitride layer is provided on the substrate. The substrate may
include a trench and the laterally grown regions extend over the
trench. The substrate may be a silicon carbide substrate and the
trench may be aligned perpendicular or parallel to a crystal plane
of the silicon carbide substrate. For example, the crystal plane of
the silicon carbide substrate may be a plane in the {11{overscore
(2)}0} family of planes or the {10{overscore (1)}0} family of
planes. A mask layer may be provided in the trench. In other
embodiments of the present invention, a mask pattern is provided on
the substrate and the laterally grown regions extend over the mask
pattern.
[0019] In some embodiments of the present invention, the laterally
grown regions have substantially vertical growth sidewalls. In
other embodiments, the laterally grown regions have trapezoidal
growth sidewalls.
[0020] In particular embodiments of the present invention, the
first Group III-nitride layer includes a gallium nitride layer
having deep level impurities therein.
[0021] In further embodiments of the present invention, the source
contact, the gate contact and the drain contact each include a
plurality of contact fingers and the laterally grown regions
include a plurality of laterally grown regions separated by
vertically grown regions, where a respective gate contact finger is
provided on a corresponding one of the plurality of laterally grown
regions.
[0022] In still further embodiments of the present invention, the
trench includes a plurality of trenches, the source contact, the
gate contact and the drain contact each include a plurality of
contact fingers and a respective gate contact finger is disposed
above a corresponding one of the plurality of trenches.
[0023] Some embodiments of the present invention provide
semiconductor devices and methods of fabricating semiconductor
devices that include a silicon carbide die having a Group
III-nitride layer thereon, the Group III-nitride layer having at
least one vertically grown region and at least one laterally grown
region and at least one Group III-nitride transistor on the silicon
carbide die. The laterally grown region does not extend
substantially beyond a region of the silicon carbide die
corresponding to the at least one Group III-nitride transistor.
[0024] In further embodiments of the present invention, the at
least one Group III-nitride transistor includes a plurality of gate
fingers and the laterally grown region includes a plurality of
laterally grown regions disposed beneath respective ones of the
gate fingers of the at least on Group III-nitride transistor. The
at least one Group III-nitride transistor may include a plurality
Group-III nitride transistors and the at least one laterally grown
region may include a plurality of laterally grown regions
corresponding to respective ones of the plurality of Group
III-nitride transistors.
[0025] In particular embodiments of the present invention, the
silicon carbide die is a portion of a silicon carbide wafer. The
silicon carbide wafer may include a major flat and the at least one
laterally grown region may have a boundary with a vertically grown
region that is perpendicular or parallel to the major flat. The at
least one Group III-nitride transistor may include a gallium
nitride-based high electron mobility transistor (HEMT).
[0026] In further embodiments of the present invention, at least
one Group III-nitride transistor on the silicon carbide die is
provided in a region of the die other than the region of the die
with the at least one laterally grown region. At least one
capacitor, resistor and/or inductor on the silicon carbide die may
be provided in a region of the die other than the region of the die
with the at least one laterally grown region.
[0027] In additional embodiments of the present invention, the at
least one laterally grown region has a boundary with a vertically
grown region that is aligned perpendicular or parallel to a crystal
plane of the silicon carbide substrate. The crystal plane of the
silicon carbide substrate may be a plane in the {11{overscore
(2)}0} family of planes or the {10{overscore (1)}0} family of
planes.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] FIG. 1 is a schematic drawing of nitride-based transistors
according to some embodiments of the present invention.
[0029] FIG. 2 is a plan view illustration of transistors according
to further embodiments of the present invention.
[0030] FIG. 3 is a plan view illustration of a wafer including dies
according to further embodiments of the present invention.
[0031] FIGS. 4A-4D are schematic illustrations of fabrication of
transistors according to further embodiments of the present
invention.
[0032] FIGS. 5-15 are schematic drawings of nitride-based
transistors according to further embodiments of the present
invention.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
[0033] The present invention now will be described more fully
hereinafter with reference to the accompanying drawings, in which
embodiments of the invention are shown. This invention may,
however, be embodied in many different forms and should not be
construed as limited to the embodiments set forth herein. Rather,
these embodiments are provided so that this disclosure will be
thorough and complete, and will fully convey the scope of the
invention to those skilled in the art. In the drawings, the size
and relative sizes of layers and regions may be exaggerated for
clarity. It will be understood that when an element or layer is
referred to as being "on", "connected to" or "coupled to" another
element or layer, it can be directly on, connected or coupled to
the other element or layer or intervening elements or layers may be
present. In contrast, when an element is referred to as being
"directly on," "directly connected to" or "directly coupled to"
another element or layer, there are no intervening elements or
layers present. Like numbers refer to like elements throughout. As
used herein, the term "and/or" includes any and all combinations of
one or more of the associated listed items.
[0034] It will be understood that, although the terms first,
second, etc. may be used herein to describe various elements,
components, regions, layers and/or sections, these elements,
components, regions, layers and/or sections should not be limited
by these terms. These terms are only used to distinguish one
element, component, region, layer or section from another region,
layer or section. Thus, a first element, component, region, layer
or section discussed below could be termed a second element,
component, region, layer or section without departing from the
teachings of the present invention.
[0035] Furthermore, relative terms, such as "lower" or "bottom" and
"upper" or "top," may be used herein to describe one element's
relationship to another elements as illustrated in the Figures. It
will be understood that relative terms are intended to encompass
different orientations of the device in addition to the orientation
depicted in the Figures. For example, if the device in the Figures
is turned over, elements described as being on the "lower" side of
other elements would then be oriented on "upper" sides of the other
elements. The exemplary term "lower", can therefore, encompasses
both an orientation of "lower" and "upper," depending of the
particular orientation of the figure. Similarly, if the device in
one of the figures is turned over, elements described as "below" or
"beneath" other elements would then be oriented "above" the other
elements. The exemplary terms "below" or "beneath" can, therefore,
encompass both an orientation of above and below.
[0036] Embodiments of the present invention are described herein
with reference to cross-section illustrations that are schematic
illustrations of idealized embodiments of the present invention. As
such, variations from the shapes of the illustrations as a result,
for example, of manufacturing techniques and/or tolerances, are to
be expected. Thus, embodiments of the present invention should not
be construed as limited to the particular shapes of regions
illustrated herein but are to include deviations in shapes that
result, for example, from manufacturing. For example, an implanted
region illustrated as a rectangle will, typically, have rounded or
curved features and/or a gradient of implant concentration at its
edges rather than a binary change from implanted to non-implanted
region. Likewise, a buried region formed by implantation may result
in some implantation in the region between the buried region and
the surface through which the implantation takes place. Thus, the
regions illustrated in the figures are schematic in nature and
their shapes are not intended to illustrate the precise shape of a
region of a device and are not intended to limit the scope of the
present invention.
[0037] Embodiments of the present invention provide Group
III-nitride based transistors having a laterally grown active
region and methods of forming such transistors.
[0038] Embodiments of the present invention may be suited for use
in nitride-based HEMTs such as Group III-nitride based devices. As
used herein, the term "Group III nitride" refers to those
semiconducting compounds formed between nitrogen and the elements
in Group III of the periodic table, usually aluminum (Al), gallium
(Ga), and/or indium (In). The term also refers to ternary and
quaternary compounds such as AlGaN and AlInGaN. As is well
understood by those in this art, the Group III elements can combine
with nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN,
AlInN), and quaternary (e.g., AlInGaN) compounds. These compounds
all have empirical formulas in which one mole of nitrogen is
combined with a total of one mole of the Group III elements.
Accordingly, formulas such as Al.sub.xGa.sub.1-xN where
0.ltoreq.x.ltoreq.1 are often used to describe them.
[0039] Suitable structures for GaN-based HEMTs that may utilize
embodiments of the present invention include but are not limited to
those described, for example, in commonly assigned U.S. Pat. No.
6,316,793 and U.S. application Ser. No. 09/904,333 filed Jul. 12,
2001 for "ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON
MOBILITY TRANSISTORS HAVING A GATE CONTACT ON A GALLIUM NITRIDE
BASED CAP SEGMENT AND METHODS OF FABRICATING SAME," U.S.
provisional application Ser. No. 60/290,195 filed May 11, 2001 for
"GROUP III NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)
WITH BARRIER/SPACER LAYER," U.S. patent application Ser. No.
10/102,272, to Smorchkova et al., entitled "GROUP-III NITRIDE BASED
HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER"
and/or Shen et al., "High-Power Polarization-Engineered
GaN/AlGaN/GaN HEMTs Without Surface Passivation," IEEE Electron
Device Letters, Vol. 25, No. 1, pp. 7-9, January 2004, the
disclosures of which are hereby incorporated herein by reference in
their entirety.
[0040] Transistors according to some embodiments of the present
invention are schematically illustrated in FIG. 1. As seen in FIG.
1, a substrate 10 is provided on which Group III-nitride based
devices may be formed. In particular embodiments of the present
invention, the substrate 10 may be a semi-insulating silicon
carbide (SiC) substrate that may be, for example, 4H polytype of
silicon carbide. Other silicon carbide candidate polytypes include
the 3C, 6H, and 15R polytypes. The term "semi-insulating" is used
descriptively rather than in an absolute sense. In particular
embodiments of the present invention, the silicon carbide bulk
crystal has a resistivity equal to or higher than about
1.times.10.sup.5 .OMEGA.-cm at room temperature.
[0041] Optional buffer, nucleation and/or transition layers (not
shown) may be provided on the substrate 10. For example, an AlN
buffer layer may be provided to provide an appropriate crystal
structure transition between the silicon carbide substrate and the
remainder of the device. Appropriate SiC substrates are
manufactured by, for example, Cree, Inc., of Durham, N.C., the
assignee of the present invention, and methods for producing are
described, for example, in U.S. Pat. Nos. Re. 34,861; 4,946,547;
5,200,022; and 6,218,680, the contents of which are incorporated
herein by reference in their entirety. Similarly, techniques for
epitaxial growth of Group III nitrides have been described in, for
example, U.S. Pat. Nos. 5,210,051; 5,393,993; 5,523,589; and
5,292,501, the contents of which are also incorporated herein by
reference in their entirety.
[0042] Although silicon carbide may be the substrate material in
some embodiments of the present invention, embodiments of the
present invention may utilize any suitable substrate, such as
sapphire, aluminum nitride, aluminum gallium nitride, gallium
nitride, silicon, GaAs, LGO, ZnO, LAO, InP, diamond and the like or
combinations thereof. For example, substrates as described in U.S.
patent application Ser. No. 10/707,898 entitled "SILICON CARBIDE ON
DIAMOND SUBSTRATES AND RELATED DEVICES AND METHODS," filed Jan. 22,
2004, the disclosure of which is incorporated herein as if set
forth in its entirety, could also be utilized. In some embodiments,
an appropriate buffer layer also may be formed.
[0043] Returning to FIG. 1, a trench 12 is provided in the
substrate 10. If a buffer layer is provided, the trench 12 may
extend into and/or through the buffer layer(s). A first Group
III-nitride layer 15 is provided on the substrate 10 and extending
over the trench 12. The first Group III-nitride layer 15 has
laterally grown portions 16 that extend over the trench and meet in
a coalescence region 18. The laterally grown portions 16 extend
from vertically grown portions and begin approximately above the
sidewalls of the trench 12 as illustrated by the dashed lines 17
and 19. Thus, the dashed lines 17 and 19 divide vertically grown
and laterally grown portions of the first Group III-nitride layer
15. The laterally grown portions 16 of the first Group III-nitride
layer 15 may have lower dislocation defect density that the
vertically grown portions.
[0044] The trench 12 should be deep enough such that the laterally
grown regions 16 coalesce before the trench 12 fills such that the
laterally grown regions 16 are cantilevered over an opening or
cavity. The depth of the trench 12 will, therefore, depend on the
width of the trench 12. Furthermore, the width of the trench 12
should be sufficiently wide to provide a laterally grown region 16
having the relationship to the active region, gate contact 34,
source contact 32 and/or drain contact 36 as described herein. As
used herein, the term "active region" refers to the region between
the source contact 32 and the drain contact 36 on which the gate
contact 34 is provided. For example, for a GaN layer, in some
embodiments of the present invention, the trench may be about 8
.mu.m wide and at least 4 .mu.m deep. Thus, if the lateral and
vertical growth rates are approximately the same the cantilevered
portions 16 of the first Group III-nitride layer 15 will meet in
the coalescence region 18 before low quality, polycrstallyine GaN
will fill the trench 12. In some embodiments, growth within the
trench 12 may be suppressed by forming a mask in the bottom of the
trench 12. Furthermore, in cantilevered growth, because a cavity
corresponding to the trench 12 remains after formation of the first
Group III-nitride layer 15, it may be beneficial to provide as
narrow a trench as results in the desired laterally grown region.
Such may be the case because, in operation, heat is typically
generated in the high field region of the transistor. If the high
field region is over a cavity, heat dissipation through the
substrate 10 may be reduced.
[0045] In some embodiments of the present invention, the trench 12
extends perpendicular or parallel to a crystal plane of the
substrate 10. For example, the trench 12 may extend parallel or
perpendicular to a plane in the {11{overscore (2)}0} family of
planes or the {10{overscore (1)}0} family of planes of a silicon
carbide substrate. In particular embodiments of the present
invention, the trench 12 extends parallel or perpendicular to a
major flat of a silicon carbide wafer that provides the substrate
10. In some embodiments of the present invention, the trench 12 may
be oriented with respect to the crystal structure to provide
vertical sidewall growth of the laterally grown regions 16 of the
first Group III-nitride layer 15. For example, the sidewall growth
may be substantially perpendicular to the surface of the substrate
10. In some embodiments of the present invention, the trench 12 may
be oriented with respect to the crystal structure to provide
trapezoidal sidewall growth of the laterally grown regions 16 of
the first Group III-nitride layer 15. For example, the sidewall
growth may be oblique to the surface of the substrate 10.
[0046] The first Group III-nitride layer 15 may be an insulating or
semi-insulating Group-III nitride layer. In some embodiments of the
present invention, the first Group III-nitride layer 15 is a
gallium nitride based layer, such as a GaN layer, incorporating
sufficient deep level dopants to provide insulating behavior. For
example, the first Group III-nitride layer 15 may be a GaN layer
doped with Fe.
[0047] A channel layer 20 is provided on the first Group
III-nitride layer 15. The channel layer 20 may be deposited on
first Group III-nitride layer 15. The channel layer may be
deposited by MOCVD or by other techniques known to those of skill
in the art, such as MBE or HVPE. In some embodiments of the present
invention, the channel layer 20 is a Group III-nitride, such as
Al.sub.xGa.sub.1-xN where 0.ltoreq.x.ltoreq.1, provided that the
bandgap of the channel layer 20 is less than the bandgap of the
barrier layer 30. In certain embodiments of the present invention,
x=0, indicating that the channel layer 20 is GaN. The channel layer
20 may also be other Group III-nitrides such as InGaN, AlInGaN or
the like. The channel layer 20 may be undoped ("unintentionally
doped"). The channel layer 20 may also be a multi-layer structure,
such as a superlattice or combinations of GaN, AlGaN or the
like.
[0048] A barrier layer 30 is provided on the channel layer 20. The
channel layer 20 may have a bandgap that is less than the bandgap
of the barrier layer 30. The barrier layer 30 may be deposited on
the channel layer 20. In certain embodiments of the present
invention, the barrier layer 30 is AlN, AlInN, AlGaN and/or
AlInGaN. In some embodiments of the present invention, the barrier
layer 30 includes multiple layers. For example, the barrier layer
30 may be about 1 nm of AlN with about 25 nm of AlGaN on the AlN
layer. Examples of barrier layers according to certain embodiments
of the present invention are described in U.S. patent application
Ser. No. 10/102,272, to Smorchkova et al., entitled "GROUP-III
NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH
BARRIER/SPACER LAYER" the disclosure of which is incorporated
herein by reference as if set forth fully herein.
[0049] The barrier layer 30 may be a Group III-nitride and has a
bandgap larger than that of the channel layer 20. Accordingly, in
certain embodiments of the present invention, the barrier layer 30
is AlGaN, AlInGaN and/or AlN or combinations of layers thereof.
Other materials may also be used for the barrier layer 30. For
example, ZnGeN.sub.2, ZnSiN.sub.2 and/or MgGeN.sub.2 could also be
used.
[0050] A source contact 32, a gate contact 34 and a drain contact
36 are provided on the barrier layer 30. The gate contact 34 may be
a Schottky gate contact. The source contact 32 and drain contact 36
may be ohmic contacts. Materials for and formation of source, drain
and gate contacts of Group III-nitride transistors are known to
those of skill in the art and, therefore, are not described in
detail herein.
[0051] The gate contact 34 is provided on the barrier layer 30 in a
region that is disposed on a laterally grown portion 16 of the
first Group III-nitride layer 15. In some embodiments or the
present invention, the laterally grown region 16 on which the gate
contact 34 is disposed extends toward the drain contact 36 a
distance "d" that is at least as far as a depletion region of a
two-dimensional electron gas extends from the edge of the gate
contact 34 on the drain side under expected operating conditions.
For example, for a gallium nitride based device with a 3.0 .mu.m
gap between the gate contact 34 and the drain contact 36, a 0.25
.mu.m long gate contact 34 and a 1.0 .mu.m gap between the gate
contact 34 and the source contact 32, the distance "d" may be about
1.5 .mu.m. By placing the gate contact and high field region over
portions of the first Group III-nitride layer 15 with lower
dislocation defect density, the regions of the layers formed on the
laterally grown regions 16 of the first Group III-nitride layer 15
may have lower dislocation density and, therefore, the gate leakage
of the device may be reduced. Furthermore, the laterally grown
regions 16 may have reduced trapping at dislocation related energy
levels in regions above, below and in the active region.
[0052] In certain embodiments of the present invention, the
laterally grown region 16 on which the gate contact 34 is disposed
extends toward the drain contact 36 at least as far as a point
where an electric field has a strength at least 50% less than a
strength of an electric field at a drain side edge of the gate
contact 34 under expected operating conditions. In further
embodiments of the present invention, the laterally grown region 16
on which the gate contact 34 is disposed extends toward the drain
contact 36 at least as far as a point where an electric field has a
strength an order of magnitude less than a strength of an electric
field at a drain side edge of the gate contact 34 under expected
operating conditions. In certain embodiments of the present
invention, the laterally grown region 16 on which the gate contact
34 is disposed extends toward the drain contact 36 at least as far
as a point where an electric field has a strength at least two
orders of magnitude less than a strength of an electric field at a
drain side edge of the gate contact 34 under expected operating
conditions.
[0053] As is further illustrated in FIG. 1, in some embodiments of
the present invention, the laterally grown region 16 on which the
gate contact 34 is disposed extends toward the drain contact 36 but
not to the drain contact 36 such that the drain contact 36 is
disposed on a vertically grown region of the first Group
III-nitride layer 15. Furthermore, the source contact 32 may be
disposed on the barrier layer 30 to extend across the coalescence
region 18 of the first Group III-nitride layer 15 so as to bridge
between two laterally grown regions 16 of the first Group
III-nitride layer 15.
[0054] While the laterally grown regions 16 are shown as extending
to a location between the gate contact 34 and the drain contact 36,
other configurations may also be utilized. For example, in some
embodiments, the laterally grown region 16 on which the gate
contact 34 is provided extends from beneath the source contact 32
to beneath the drain contact 36. The laterally grown region 16 on
which the gate contact is provided could only extend from beneath
the gate contact 34 to beneath the drain contact 36. Alternatively,
the laterally grown region 16 on which the gate contact 34 is
provided may extend from beneath the gate contact 34 toward but not
to beneath the drain contact 36. The laterally grown region on
which the gate contact 34 is provided may extend from beneath the
source contact 32 toward but not to beneath the drain contact 36.
In some embodiments of the present invention, the laterally grown
region on which the gate contact 34 is provided extends a majority
of the distance from source contact 32 to the drain contact 36.
[0055] While embodiments of the present invention have been
illustrated in FIG. 1 with reference to cantilevered growth to
provide the laterally grown portions 16 extending over the trench
12, in other embodiments of the present invention, epitaxial
lateral overgrowth over a mask or pendeo-epitaxial growth from
sidewalls of a trench in a Group III-nitride layer may also be
provided. Thus, for example, rather than etching a trench in the
substrate 10, a mask pattern could be provided on the substrate 10
and the first Group III-nitride layer grown laterally over the
mask. However, care may need to be taken in such a case to avoid
contamination of the Group III-nitride layer by the mask. For
example, if the first Group III-nitride layer is GaN and the mask
is SiO.sub.2, the silicon from the mask may contaminate the GaN to
dope the GaN conductive. However, a mask of diamond or other
thermally conductive material could be utilized. Thus, a buried
conductive layer could be unintentionally created.
[0056] As a further example, if pendeo-epitaxial growth is
utilized, a Group III-nitride layer maybe provided on the substrate
10 and trenches formed in the Group III-nitride layer. The
laterally grown portions 16 would then be grown from the sidewalls
of the trenches in the first Group III-nitride layer.
[0057] Techniques for cantilevered growth, pendeo-epitaxial growth
and/or epitaxial lateral overgrowth are known to those of skill in
the art and need not be described further herein. However, examples
of such growth are described, for example, in U.S. Pat. Nos.
6,582,906, 6,706,114, 6,686,261, 6,621,148, 6,608,327, 6,602,764,
6,602,763, 6,586,778, 6,582,986, 6,570,192, 6,545,300, 6,521,514,
6,489,221, 6,486,042, 6,462,355, 6,380,108, 6,376,339, 6,261,929,
6,255,198, 6,177,688 and 6,051,849, the disclosures of which are
incorporated herein by reference as if set forth fully herein.
[0058] FIG. 2 is a plan view of a portion of a transistor having
multiple gate, source and drain fingers according to some
embodiments of the present invention. As seen in FIG. 2, a
plurality of gate contacts 34 are provided between corresponding
source contacts 32 and drain contacts 36. The gate contacts 34 are
connected together by a gate metal interconnect 34', the drain
contacts 36 are connected together by a drain contact interconnect
36' and the source contacts 32 are connected together in another
interconnect metal layer (not shown) utilizing techniques known to
those of skill in the art. The active area of the transistor is
defined laterally by an isolation edge 40 as shown in FIG. 2, where
current flows between the terminals nominally within the region
defined by the isolation edge 40. The isolation edge 40 may, for
example, be provide by an implanted region or mesa termination. The
trenches 12 may extend beyond the isolation edge 40 and may extend
beyond the isolation edge 40 a distance sufficient so that edge
effects of the lateral growth do not extend substantially into the
active region of the device. For example, a distance of several
microns may be sufficient.
[0059] In some embodiments of the present invention, the trench 12
may be provided in an active device region, such as between the
source and drain contacts 32, 36 and extends under the source
contact 32 as illustrated in FIG. 2. Thus, the trenches 12 need not
be provided in all regions of the substrate 10 but may be limited
to regions where the lower dislocation density may provide the most
benefit. For example, the trenches 12 could, but need not, extend
to beneath the gate interconnect 34' that interconnects the fingers
34 of the gate or to beneath the region of the source or drain
interconnects 36' that interconnects the fingers of the source or
drain contacts 34, 36. Thus, the trenches 12 may be somewhat wider
than the active region but need not be so large as to extend to
other areas where, for example, other devices, such as passive
devices or discrete devices including, for example, resistors,
capacitors or inductors, may be formed.
[0060] FIG. 3 is a plan view of a wafer 100 having die 110
according to some embodiments of the present invention. As seen in
FIG. 3, the die 110 may have a particular region 120 where trenches
are formed to make transistors as described above with reference to
FIGS. 1 and/or 2. The region 120 may be less than the entire die
110. Thus, according to some embodiments of the present invention,
a silicon carbide die having at least one trench and at least one
Group III-nitride transistor on the silicon carbide die is
provided. The trench is disposed only in a region of the silicon
carbide die corresponding to an active region of the Group
III-nitride transistor. Other devices, including other transistors
that are not formed on laterally grown regions, may be provided in
other regions of the die 110 outside of the region 120.
Furthermore, multiple trenches to provide multiple transistors may
be provided in the region 120. Also, while the wafer 100 is
illustrated as having multiple die 110, that may be subsequently
singulated to provide a plurality of chips, in some embodiments,
the wafer 100 may be a single die such that the wafer-provides the
die. Furthermore, multiple regions 120 may be provided in a single
die 110.
[0061] The trenches in the region 120 of the die 110 may be aligned
to the major flat or the minor flat of the wafer 100. In some
embodiments of the present invention, the trenches are aligned
perpendicular or parallel to the major flat of the wafer 100.
[0062] Fabrication of transistors according to some embodiments of
the present invention will now be described with reference to FIGS.
4A-4D and FIG. 1. FIGS. 4A-4D and FIG. 1 illustrate fabrication of
transistors utilizing cantilevered growth of the first Group
III-nitride layer. However, as discussed above, other lateral
growth techniques, such as ELO or pendeo-epitaxial growth could
also be utilized. Furthermore, fabrication of transistors according
to some embodiments of the present invention will be described with
reference to a silicon carbide substrate and a GaN first Group
III-nitride layer, however, other materials may be utilized as
described above. If other materials or growth techniques are
utilized, modifications in the fabrication described herein may be
needed in light of the different materials and/or growth technique.
Such modifications should be apparent those of skill in the art in
light of the present disclosure and, therefore, will not be
described further herein. For example, as described below,
cantilevered growth may be provided for forming the epitaxial
layers in-situ in a continuous process in an epitaxial growth
reactor by varying the source materials during growth. However, if
pendeo-epitaxial growth is utilized, a Group III-nitride layer is
first formed on a substrate, removed from the reactor, masked and
etched and then returned to the reactor to grow the remaining
layers. Thus, the use of cantilevered growth may provide for fewer
fabrication steps.
[0063] Turning to FIG. 4A, a substrate 10, such as a
semi-insulating silicon carbide substrate, has a trench 12 formed
therein. The trench 12 may be formed by forming and patterning a
mask on the substrate 10, etching the substrate 10 utilizing the
patterned mask and, subsequently, removing the patterned mask. For
example, a reactive ion etch may be used to etch the substrate 10
if the substrate 10 is silicon carbide. Other etching techniques
could also be utilized. As discussed above, the mask may be aligned
to the flats of the wafer to assure that the trench is aligned to a
crystal plane of the substrate 10. Furthermore, alignment marks may
also be etched into the substrate 10 so that subsequent fabrication
of, for example, ohmic contacts and/or the gate contact may be
aligned to the trench 12. Such alignment marks may be provided in
the substrate 10 as the subsequent GaN-based layers may be
transparent and, therefore, the alignment marks may be visible
through the subsequently formed layers for use in subsequent
fabrication steps.
[0064] FIG. 4B illustrates the growth of the first Group
III-nitride layer 15, such as a GaN layer. Typically, the first
layer 15 would be preceded by the deposition of a thin nucleation
layer such as AlN in the case of a SiC substrate and a GaN first
layer. A GaN layer having insulating properties may be grown, for
example, by metal organic chemical vapor deposition (MOCVD)
incorporating sufficient deep level dopants, such as Fe, into the
layer to provide insulating properties to the GaN layer. Techniques
for incorporating deep level dopants are described, for example, in
U.S. patent application Ser. No. 10/752,970, entitled "CO-DOPING
FOR FERMI LEVEL CONTROL IN SEMI-INSULATING GROUP III NITRIDES"
filed Jan. 7, 2004, the disclosure of which is incorporated herein
by reference as if set forth fully herein. Techniques for growing
cantilevered Group III-nitrides are discussed above and known to
those of skill in the art and, therefore, need not be described
further herein.
[0065] After the first Group III-nitride layer 15 coalesces over
the trench 12, the deep level dopant source may be discontinued and
the channel layer 20 may be grown on the first Group III-nitride
layer 15 as illustrated in FIG. 4C. The coalescence region may not
extend into and/or through layers subsequently formed on the first
Group III-nitride layer 15. In the example described above, the Fe
source may be discontinued and a GaN layer grown on the Fe doped
GaN layer in-situ. Likewise, the source materials may be altered
and the barrier layer 30 grown on the channel layer 20. For
example, Al may be added to the GaN source materials and AlGaN
grown as the barrier layer 30. Such layers may be formed by MOCVD
as described above. Other growth techniques may also be utilized.
Thus, in some embodiments of the present invention, the first Group
III-nitride layer 15, the channel layer 20 and the barrier layer 30
may be formed in a continuous process without the need for
additional growth, mask and/or etching steps.
[0066] FIG. 4D illustrates the formation of the ohmic contacts for
the source contact 32 and the drain contact 36. These contacts may,
for example, be formed by depositing and patterning an ohmic
contact material utilizing conventional techniques. The particular
technique of forming ohmic contacts may depend on the structure of
the transistor device. For example, the contacts may be formed in a
recess or on a regrown layer. Furthermore, anneals or other
processing to form the source contact 32 and the drain contact 36
may be provided. For example, encapsulation layers may be provided
to protect the barrier layer 30 from damage during contact anneals.
The formation of ohmic contacts for Group III-nitride devices is
known to those of skill in the art and, therefore, need not be
described further herein. The ohmic contacts may be patterned, for
example, utilizing the alignment marks etched in the substrate 10
as described above.
[0067] The gate contact 34 may also be formed as illustrated in
FIG. 1. The gate contact 34 may, for example, be formed by
depositing and patterning a Schottky contact material utilizing
conventional techniques. The formation of gate contacts for Group
III-nitride devices is known to those of skill in the art and,
therefore, need not be described further herein. The gate contact
34 may be patterned, for example, utilizing the alignment marks
etched in the substrate 10 as described above.
[0068] Any suitable technique for forming the ohmic contacts and
the gate contact may be utilized while providing the alignment to
the laterally grown regions described herein. For example,
techniques and/or structures such as those described in the above
referenced United States Patents, Patent Applications and/or
publications as well as U.S. patent application Ser. No. ______
(Attorney Docket No. 5308-413), entitled "METHODS OF FABRICATING
NITRIDE-BASED TRANSISTORS HAVING REGROWN OHMIC CONTACT REGIONS AND
NITRIDE-BASED TRANSISTORS HAVING REGROWN OHMIC CONTACT REGIONS,"
filed May 20, 2004, U.S. patent application Ser. No. ______
(Attorney Docket No. 5308-392), entitled "METHODS OF FABRICATING
NITRIDE-BASED TRANSISTORS WITH A CAP LAYER AND A RECESSED GATE,"
filed Jul. 23, 2004, U.S. patent application Ser. No. 10/617,843,
entitled "NITRIDE-BASED TRANSISTORS AND METHODS OF FABRICATION
THEREOF USING NON-ETCHED CONTACT RECESSES," filed Jul. 11, 2003,
the disclosures of which are incorporated by reference as if set
forth fully herein, may be utilized.
[0069] FIGS. 5 through 15 illustrate different configurations of
source contact 32, drain contact 36 and gate contact 34 with
reference to the laterally grown regions 16 and coalescence region
18 according to further embodiments of the present invention. In
FIG. 5, the drain contact 36 is provided on the vertically grown
portion of the first Group III-nitride layer 15 and extends to but
not substantially beyond the boundary 17 between the laterally
grown region 16 and the vertically grown region of the first Group
III-nitride layer 15. Thus, the active region of the device in FIG.
5 is provided in a single laterally grown region 16.
[0070] In FIG. 6, the drain contact 36 is provided on the
vertically grown portion of the first Group III-nitride layer 15
and extends beyond the boundary 17 between the laterally grown
region 16 and the vertically grown region of the first Group
III-nitride layer 15. Thus, the active region of the device in FIG.
6 is provided in a single laterally grown region 16.
[0071] In FIG. 7, the drain contact 36 is provided on the
vertically grown portion of the first Group III-nitride layer 15
and does not extend to the boundary 17 between the laterally grown
region 16 and the vertically grown region of the first Group
III-nitride layer 15. The source contact 32 does not bridge the
coalescence region 18. The gate contact 34 is provided on the
laterally grown region 16 adjacent the drain contact 36. Thus, the
active region of the device in FIG. 7 is provided in two adjacent
laterally grown regions 16 and portion of a vertically grown region
adjacent one of the laterally grown regions 16.
[0072] In FIG. 8, the drain contact 36 is provided on the
vertically grown portion of the first Group III-nitride layer 15
and extends to but not beyond the boundary 17 between the laterally
grown region 16 and the vertically grown region of the first Group
III-nitride layer 15. The source contact 32 does not bridge the
coalescence region 18. The gate contact 34 is provided on the
laterally grown region 16 adjacent the drain contact 36. Thus, the
active region of the device in FIG. 8 is provided in two adjacent
laterally grown regions 16.
[0073] In FIG. 9, the drain contact 36 is provided on the
vertically grown portion of the first Group III-nitride layer 15
and extends beyond the boundary 17 between the laterally grown
region 16 and the vertically grown region of the first Group
III-nitride layer 15. The source contact 32 does not bridge the
coalescence region 18. The gate contact 34 is provided on the
laterally grown region 16 adjacent the drain contact 36. Thus, the
active region of the device in FIG. 9 is provided in two adjacent
laterally grown regions 16.
[0074] In FIG. 10, the drain contact 36 is provided on the
vertically grown portion of the first Group III-nitride layer 15
and does not extend to the boundary 17 between the laterally grown
region 16 and the vertically grown region of the first Group
III-nitride layer 15. The source contact 32 does not bridge the
coalescence region 18. The gate contact 34 is provided on the
laterally grown region 16 adjacent the source contact 32. Thus, the
active region of the device in FIG. 10 is provided in two adjacent
laterally grown regions 16 and portion of a vertically grown region
adjacent one of the laterally grown regions 16.
[0075] In FIG. 11, the drain contact 36 is provided on the
vertically grown portion of the first Group III-nitride layer 15
and extends to but not beyond the boundary 17 between the laterally
grown region 16 and the vertically grown region of the first Group
III-nitride layer 15. The source contact 32 does not bridge the
coalescence region 18. The gate contact 34 is provided on the
laterally grown region 16 adjacent the source contact 32. Thus, the
active region of the device in FIG. 11 is provided in two adjacent
laterally grown regions 16.
[0076] In FIG. 12, the drain contact 36 is provided on the
vertically grown portion of the first Group III-nitride layer 15
and extends beyond the boundary 17 between the laterally grown
region 16 and the vertically grown region of the first Group
III-nitride layer 15. The source contact 32 does not bridge the
coalescence region 18. The gate contact 34 is provided on the
laterally grown region 16 adjacent the source contact 32. Thus, the
active region of the device in FIG. 12 is provided in two adjacent
laterally grown regions 16.
[0077] In FIG. 13, the drain contact 36 is provided on the
vertically grown portion of the first Group III-nitride layer 15
and does not extend to the boundary 17 between the laterally grown
region 16 and the vertically grown region of the first Group
III-nitride layer 15. The source contact 32 does not bridge the
coalescence region 18. The gate contact 34 is provided on both the
laterally grown regions 16 and bridges the coalescence region 18.
Thus, the active region of the device in FIG. 13 is provided in two
adjacent laterally grown regions 16 and portion of a vertically
grown region adjacent one of the laterally grown regions 16.
[0078] In FIG. 14, the drain contact 36 is provided on the
vertically grown portion of the first Group III-nitride layer 15
and extends to but not beyond the boundary 17 between the laterally
grown region 16 and the vertically grown region of the first Group
III-nitride layer 15. The source contact 32 does not bridge the
coalescence region 18. The gate contact 34 is provided on both the
laterally grown regions 16 and bridges the coalescence region 18.
Thus, the active region of the device in FIG. 14 is provided in two
adjacent laterally grown regions 16.
[0079] In FIG. 15, the drain contact 36 is provided on the
vertically grown portion of the first Group III-nitride layer 15
and extends beyond the boundary 17 between the laterally grown
region 16 and the vertically grown region of the first Group
III-nitride layer 15. The source contact 32 does not bridge the
coalescence region 18. The gate contact 34 is provided on both the
laterally grown regions 16 and bridges the coalescence region 18.
Thus, the active region of the device in FIG. 15 is provided in two
adjacent laterally grown regions 16.
[0080] While the embodiments illustrated in FIGS. 1 and 5 through
15 illustrate variations in the gate contact 34, source contact 32
and drain contact 36 placement, additional variations may be
provided. For example, the embodiments illustrated in FIGS. 7
through 15 could be provided with the source contact 32 extending
to but not beyond the boundary 19 between the laterally grown
region 16 and the vertically grown region of the first Group
III-nitride layer 15. Likewise, the embodiments illustrated in
FIGS. 7 through 15 could be provided with the source contact 32 not
extending to the boundary 19 between the laterally grown region 16
and the vertically grown region of the first Group III-nitride
layer 15.
[0081] While embodiments of the present invention have been
illustrated with reference to a particular HEMT structure, other
structures that may allow for the formation of the gate over a
laterally grown region of a Group III-nitride may also be provided.
For example, an insulating layer may be provided between the gate
and the barrier layer to provide a MISHEMT. Accordingly,
embodiments of the present invention should not be construed as
limited to the particular transistor structure described
herein.
[0082] Furthermore, while embodiments of the present invention have
been described with reference to a particular sequence of
fabrication steps, a different sequence of steps may be utilized
while still falling within the scope of the present invention.
Accordingly, embodiments of the present invention should not be
construed as limited to the particular sequence of steps described
herein.
[0083] In the drawings and specification, there have been disclosed
typical embodiments of the invention, and, although specific terms
have been employed, they have been used in a generic and
descriptive sense only and not for purposes of limitation, the
scope of the invention being set forth in the following claims.
* * * * *