U.S. patent application number 10/982782 was filed with the patent office on 2005-06-02 for inductor for a system-on-a-chip and method for manufacturing the same.
Invention is credited to Hah, Sang-Rok, Kim, Il-Ryong, Kim, Yi-Gwon, Lee, Hyo-Jong, Lee, Ui-Hyoung, Son, Hong-Seong.
Application Number | 20050116317 10/982782 |
Document ID | / |
Family ID | 34431727 |
Filed Date | 2005-06-02 |
United States Patent
Application |
20050116317 |
Kind Code |
A1 |
Lee, Hyo-Jong ; et
al. |
June 2, 2005 |
Inductor for a system-on-a-chip and method for manufacturing the
same
Abstract
An inductor for a system-on-a-chip and a method for
manufacturing the inductor are disclosed. The inductor comprises a
conductive line formed by connecting a plurality of conductive
patterns grown from a seed layer formed on a lower wiring. The
method comprises using an electrolytic plating process or an
electroless plating process to grow the plurality of adjacent
conductive patterns from the seed layer until they become
connected. The method also enables adjusting the height and width
of the conductive line to desired levels.
Inventors: |
Lee, Hyo-Jong; (Seoul,
KR) ; Son, Hong-Seong; (Suwon-si, KR) ; Lee,
Ui-Hyoung; (Seoul, KR) ; Hah, Sang-Rok;
(Seoul, KR) ; Kim, Il-Ryong; (Suwon-si, KR)
; Kim, Yi-Gwon; (Seoul, KR) |
Correspondence
Address: |
VOLENTINE FRANCOS, & WHITT PLLC
ONE FREEDOM SQUARE
11951 FREEDOM DRIVE SUITE 1260
RESTON
VA
20190
US
|
Family ID: |
34431727 |
Appl. No.: |
10/982782 |
Filed: |
November 8, 2004 |
Current U.S.
Class: |
257/531 ;
257/E21.022; 257/E27.046; 438/618 |
Current CPC
Class: |
H01L 28/10 20130101;
H01F 2017/0046 20130101; H01L 23/5227 20130101; H01F 41/041
20130101; H01L 27/08 20130101; H01L 2924/0002 20130101; H01L
2924/0002 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/531 ;
438/618 |
International
Class: |
H01L 021/00; H01L
021/8238; H01L 029/00; H01L 021/4763 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 6, 2003 |
KR |
2003-78195 |
Claims
What is claimed is:
1. An inductor comprising: a seed layer formed on a substrate; and
a conductive line formed on the seed layer, wherein the conductive
line is formed by a plurality of connected conductive patterns
grown from the seed layer.
2. The inductor of claim 1, further comprising: a diffusion
prevention layer formed between the substrate and the seed
layer.
3. The inductor of claim 1, further comprising: a protection layer
formed on the conductive line.
4. The inductor of claim 3, wherein the protection layer comprises
silicon carbide or silicon nitride.
5. The inductor of claim 3, wherein the protection layer has a
thickness of about 100 to 1,000 .ANG..
6. The inductor of claim 1, further comprising: a mold layer
comprising hole arrays respectively filled with one of the
plurality of conductive patterns.
7. The inductor of claim 6, wherein the plurality of conductive
patterns filling the hole arrays are connected to one another on
the mold layer to form the conductive line.
8. The inductor of claim 6, wherein the mold layer comprises oxide
or photoresist.
9. The inductor of claim 6, wherein the mold layer has a thickness
of about 500 to 30,000 .ANG..
10. The inductor of claim 6, wherein each of the hole arrays has a
depth of about 500 to 30,000 .ANG..
11. The inductor of claim 1, further comprising: a mold layer
comprising trenches respectively filled with one of the plurality
of conductive patterns.
12. The inductor of claim 11, wherein the plurality of conductive
patterns filling the trenches are connected to one another on the
mold layer to form the conductive line.
13. The inductor of claim 11, wherein the mold layer comprises
oxide or photoresist.
14. The inductor of claim 11, wherein the mold layer has a
thickness of about 500 to 30,000 .ANG..
15. The inductor of claim 11, wherein each of the trenches has a
depth of about 500 to 30,000 .ANG..
16. The inductor of claim 1, wherein the conductive line has a
rounded upper portion.
17. An inductor comprising: a substrate comprising a conductive
structure; a seed layer formed on the substrate; a mold layer
formed on the seed layer, wherein the mold layer includes hole
arrays exposing the seed layer; and a conductive line formed on the
seed layer, wherein the conductive line is electrically connected
to the conductive structure and is formed by a plurality of
connected conductive patterns grown from the seed layer.
18. The inductor of claim 17, further comprising: a diffusion
prevention layer formed between the substrate and the seed
layer.
19. The inductor of claim 17, further comprising: a protection
layer formed on the conductive line.
20. The inductor of claim 17, wherein the conductive line has an
upper portion having a mushroom shaped structure.
21. An inductor comprising: a substrate including a conductive
structure; a mold layer formed on the substrate, wherein the mold
layer comprises hole arrays having inner surfaces; a seed layer
formed on the inner surfaces of the hole arrays; and a conductive
line formed on the seed layer, wherein the conductive line is
electrically connected to the conductive structure and is formed by
a plurality of connected conductive patterns grown from the seed
layer.
22. The inductor of claim 21, further comprising: a diffusion
prevention layer formed between the seed layer and the substrate
including the conductive structure.
23. The inductor of claim 21, further comprising: a protection
layer formed on the conductive line.
24. The inductor of claim 21, wherein the conductive line has a
rounded upper portion.
25. An inductor comprising: a substrate including a conductive
structure; a mold layer formed on the substrate, wherein the mold
layer comprises trenches having inner surfaces; a seed layer formed
on the inner surfaces of the hole arrays; and a conductive line
formed on the seed layer, wherein the conductive line is
electrically connected to the conductive structure and is formed by
a plurality of connected conductive patterns grown from the seed
layer.
26. The inductor of claim 25, further comprising: a diffusion
prevention layer formed between the seed layer and the substrate
including the conductive structure.
27. The inductor of claim 25, further comprising: a protection
layer formed on the conductive line.
28. The inductor of claim 25, wherein the conductive line has a
rounded upper portion.
29. An inductor comprising: a substrate including a conductive
structure; a mold layer formed on the substrate, wherein the mold
layer comprises hole arrays having inner surfaces; a first seed
layer formed on the inner surfaces of the hole arrays and on the
mold layer; a capping layer formed on the first seed layer; a
second seed layer formed on portions of the capping layer
positioned in the hole arrays; and, a conductive line formed on the
second seed layer, wherein the conductive line is electrically
connected to the conductive structure and is formed by a plurality
of connected conductive patterns grown from the second seed
layer.
30. The inductor of claim 29, further comprising: a diffusion
prevention layer formed between the first seed layer and the
substrate including the conductive structure, and between the first
seed layer and the mold layer.
31. The inductor of claim 29, wherein the first seed layer
comprises an element selected from the group consisting of copper
(Cu), platinum (Pt), palladium (Pd), nickel (Ni), silver (Ag), gold
(Au) and any alloy thereof.
32. The inductor of claim 29, wherein the capping layer comprises
aluminum (Al).
33. The inductor of claim 32, wherein the capping layer has a
thickness of about 100 to 500 .ANG..
34. The inductor of claim 29, wherein the second seed layer
comprises an element selected from the group consisting of copper,
platinum, palladium, nickel, silver, gold and any alloy
thereof.
35. The inductor of claim 29, further comprising a protection layer
formed on the conductive line.
36. The inductor of claim 29, wherein the conductive line has a
rounded upper portion.
37. A method for manufacturing an inductor, comprising: forming a
mold layer on a seed layer, wherein the mold layer comprises hole
arrays exposing the seed layer; forming conductive patterns on the
mold layer from the seed layer to fill the hole arrays; and forming
a conductive line on the mold layer by growing the conductive
patterns on the mold layer and connecting the conductive
patterns.
38. The method of claim 37, wherein forming the mold layer
comprises: forming a photoresist film on the seed layer; and
forming a photoresist pattern on the seed layer by patterning the
photoresist film, wherein the photoresist pattern includes the hole
arrays that expose the seed layer.
39. The method of claim 38, wherein forming the photoresist pattern
comprises: placing a mask over the photoresist film, the mask
comprising a pattern having hole arrays arranged substantially in
parallel; and, exposing the photoresist film using the mask.
40. The method of claim 38, further comprising: forming an
anti-reflective layer on the photoresist film.
41. The method of claim 40, further comprising: removing the
photoresist pattern and the anti-reflective layer after forming the
conductive line.
42. The method of claim 41, wherein the photoresist pattern and the
anti-reflective layer are removed using an organic stripper, a
solution including ozone at a relatively high concentration, or a
standard cleaning solution including carbon dioxide.
43. The method of claim 37, wherein forming the mold layer
comprises: forming an oxide layer on the seed layer; forming a
photoresist film on the oxide layer; forming a photoresist pattern
on the oxide layer by patterning the photoresist film; and, forming
the hole arrays through the mold layer by etching the mold layer
using the photoresist pattern as an etching mask.
44. The method of claim 37, further comprising: forming a diffusion
prevention layer between the seed layer and an underlying
structure.
45. The method of claim 44, further comprising: partially removing
the seed layer and the diffusion prevention layer except for
portions of the seed layer and the diffusion prevention layer
positioned beneath the conductive line after forming the conductive
line.
46. The method of claim 45, wherein the seed layer and the
diffusion prevention layer are partially removed using a solution
including hydrogen fluoride and hydrogen peroxide or hydrogen
fluoride and nitric acid.
47. The method of claim 37, further comprising: forming a
protection layer on the conductive line.
48. The method of claim 37, wherein the conductive line is formed
by an electrolytic plating process or an electroless plating
process.
49. The method of claim 48, wherein the electrolytic plating
process is performed with a current density of about 20 to 40
mA/cm.sup.2 using a plating solution including a copper sulfate
solution, a sulfuric acid solution and a solution including
chlorine ions.
50. A method for manufacturing an inductor, comprising: forming a
mold layer on a seed layer, wherein the mold layer comprises
trenches exposing the seed layer; forming conductive patterns on
the mold layer from the seed layer to fill the trenches; and
forming a conductive line on the mold layer by growing the
conductive patterns on the mold layer and connecting the conductive
patterns.
51. The method of claim 50, wherein forming the mold layer
comprises: forming a photoresist film on the seed layer; and
forming a photoresist pattern on the seed layer by patterning the
photoresist film, wherein the photoresist pattern includes the
trenches that expose the seed layer.
52. The method of claim 51, wherein forming the photoresist pattern
comprises: placing a mask over the photoresist film, the mask
comprising a pattern having trenches substantially in parallel; and
exposing the photoresist film using the mask.
53. A method of manufacturing an inductor comprising: forming a
mold layer on a substrate comprising a conductive structure,
wherein the mold layer comprises hole arrays having inner surfaces;
forming a diffusion prevention layer on the inner surfaces of the
hole arrays and on the mold layer; forming seed layer patterns on
portions of the diffusion prevention layer positioned in the hole
arrays; forming conductive patterns from the seed layer patterns to
fill the hole arrays; forming a conductive line on the mold layer
by growing the conductive patterns on the mold layer and by
connecting the conductive patterns; and forming a protection layer
on the conductive line.
54. The method of claim 53, wherein forming the seed layer patterns
comprises: forming a seed layer on the diffusion prevention layer;
and removing portions of the seed layer positioned on the mold
layer.
55. The method of claim 54, wherein removing the portions of the
seed layer is performed by a chemical mechanical polishing (CMP)
process, an etch back process, or a combination of a CMP process
and an etch back process.
56. The method of claim 53, wherein forming the conductive line is
performed by an electrolytic plating process or an electroless
plating process.
57. A method of manufacturing an inductor comprising: forming a
mold layer on a substrate comprising a conductive structure,
wherein the mold layer comprises hole arrays having inner surfaces;
forming a diffusion prevention layer on the inner surfaces of the
hole arrays and on the mold layer; forming a first seed layer on
the diffusion prevention layer; forming a capping layer on the
first seed layer; forming second seed layer patterns on portions of
the capping layer positioned in the hole arrays; forming conductive
patterns from the second seed layer patterns to fill the hole
arrays; forming a conductive line on the mold layer by growing the
conductive patterns on the mold layer and by connecting the
conductive patterns; and forming a protection layer on the
conductive line.
58. The method of claim 57, wherein forming the second seed layer
patterns comprises: forming a second seed layer on the capping
layer; and removing portions of the second seed layer positioned on
the mold layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates generally to an inductor and a
method for manufacturing the inductor. More particularly, the
present invention relates to an inductor for radio frequency (RF)
devices for a system-on-a-chip (SOC), and a method for
manufacturing the inductor.
[0003] A claim of priority is made to Korean Patent Application No.
2003-78195 filed on Nov. 6, 2003, the disclosure of which is
incorporated herein by reference in its entirety.
[0004] 2. Description of the Related Art
[0005] An SOC comprises a single microchip integrating together all
of the elements of a system. The elements of the system generally
comprise independently operating semiconductor devices or circuits.
For example, an SOC for wireless communications typically includes
a microprocessor, a digital signal processor (DSP), a random access
memory (RAM) device, and a read only memory (ROM). Generally, the
elements of an SOC are integrated on a large scale integrated (LSI)
circuit or an integrated circuit (IC).
[0006] In an SOC for RF communication, semiconductor devices and RF
circuits are generally integrated on a single chip. Inductors are
typically formed on integrated circuits of the SOC after the
integrated circuits are formed on a semiconductor substrate. A thin
film type inductor having a spiral or solenoid construction is
commonly employed in an SOC because it is easily combined with
integrated circuits. In addition, thin film type inductors are
employed for various devices such as a voltage controlled
oscillator (VCO), a filter, or a converter.
[0007] A conventional thin film type inductor is disclosed in
various international patent publications, including, for example,
Korean Laid Open Patent Publication No. 2003-20,603, Korean Patent
No. 348,250, and Japanese Laid Open Patent Publication No.
1998-241,983.
[0008] FIGS. 1A to 1C are cross-sectional views illustrating a
method of manufacturing a conventional inductor disclosed in the
above-mentioned Korean Laid Open Patent Publication.
[0009] Referring to FIG. 1A, a soft magnetic thin film 15 is formed
on a substrate 10 formed on a silicon wafer. Soft magnetic thin
film 15 has a double-layer structure comprising an iron-tantalum
nitride (FeTaN) layer and a titanium (Ti) layer.
[0010] An insulation film 20 of silicon oxide is formed on soft
magnetic thin film 15 and a seed layer 25 for an electroplating
process is formed on insulation film 20. Seed layer 25 has a
double-layer structure comprising a copper (Cu) layer and a
chromium (Cr) layer.
[0011] A photosensitive film 30 is deposited on the seed layer 25,
and then a mask 35 is formed over the photosensitive film 30. The
photosensitive film 30 is exposed through a pattern in mask 35. The
pattern of the mask 35 defines an inductor having a coil
structure.
[0012] Referring to FIG. 1B, a plurality of holes are formed
through the photosensitive film 30 by developing the exposed
portions of the photosensitive film 30. The holes expose the seed
layer 25 which is positioned beneath the photosensitive film 30. A
coil 40 of the inductor is formed from the seed layer 25 to fill
the holes. The coil 40 is formed by an electroplating process using
a plating solution including copper.
[0013] Referring to FIG. 1C, the photosensitive film 30 is removed
and portions of the seed layer 25 exposed between the loops of the
coil 40 are etched away using a wet etching process to complete the
coil 40 on insulation film 20. The coil 40 is attached to an upper
magnetic film 50 using an adhesive film 45 of epoxy resin to form
the inductor on the substrate 10.
[0014] In the above-described method for manufacturing a
conventional inductor, the rate at which the coil 40 grows from the
seed layer 25 to fill the holes in the photosensitive film 30
decreases significantly as the size of the holes increases. As the
width and height of the inductor increase, the rate of coil growth
slows accordingly, thus driving up the time and cost of
manufacturing for the inductor and the related RF device. However,
it is important for the inductor to have sufficient width and
height to ensure the desired electrical characteristics of the
inductor.
SUMMARY OF THE INVENTION
[0015] The present invention provides an inductor for an SOC
manufactured according to a simplified process. The present
invention also provides a low-cost method for manufacturing an
inductor for an SOC using a simplified process.
[0016] According to one aspect of the present invention, an
inductor comprises a seed layer formed on a substrate and a
conductive line formed on the seed layer. The conductive line is
formed by connecting a plurality of conductive patterns grown from
the seed layer. A diffusion prevention layer is preferably formed
between the substrate and the seed layer, and a protection layer is
preferably formed on the conductive line. Additionally, a mold
layer including hole arrays is preferably filled with the
respective conductive patterns.
[0017] According to another aspect of the present invention, an
inductor comprises a substrate including a conductive structure, a
seed layer formed on the substrate, a mold layer formed on the seed
layer, and a conductive line formed on the seed layer. The mold
layer includes hole arrays exposing the seed layer, and the
conductive line is electrically connected to the conductive
structure. The conductive line is formed by connecting a plurality
of conductive patterns grown from the seed layer. A protection
layer is preferably formed on the conductive line.
[0018] According to still another aspect of the present invention,
an inductor comprises a substrate including a conductive structure,
a mold layer including hole arrays having inner surfaces formed on
the substrate, a seed layer formed on the inner surfaces of the
hole arrays, and a conductive line formed on the seed layer. The
conductive line is electrically connected to the conductive
structure and is formed by connecting a plurality of conductive
patterns grown from the seed layer.
[0019] According to still another aspect of the present invention,
an inductor comprises a substrate having a conductive structure, a
mold layer including hole arrays having inner surfaces formed on
the substrate, a first seed layer formed on the inner surfaces of
the hole arrays and on the mold layer, a capping layer formed on
the first seed layer, a second seed layer formed on portions of the
capping layer positioned in the hole arrays, and a conductive line
formed on the second seed layer. The conductive line is
electrically connected to the conductive structure and is formed by
connecting a plurality of conductive patterns grown from the second
seed layer.
[0020] According to still another aspect of the present invention,
there is provided a method for manufacturing an inductor. The
method comprises forming a mold layer on a seed layer, wherein the
mold layer includes hole arrays exposing the seed layer. The method
further comprises forming conductive patterns on the mold layer
from the seed layer to fill the hole arrays. The method further
comprises forming a conductive line on the mold layer by growing
the conductive patterns on the mold layer and connecting the
conductive patterns. Preferably, the method further comprises
forming an anti-reflective layer on the mold layer and forming a
protection layer on the conductive line.
[0021] According to still another aspect of the present invention,
there is provided a method for manufacturing an inductor. The
method comprises forming a mold layer including hole arrays having
inner surfaces on a substrate including a conductive structure and
forming a diffusion prevention layer on the inner surfaces of the
hole arrays and on the mold layer. The method further comprises
forming seed layer patterns on portions of the diffusion prevention
layer positioned in the hole arrays and forming conductive patterns
from the seed layer patterns to fill the hole arrays. The method
also further comprises forming a conductive line on the mold layer
by growing the conductive patterns on the mold layer and by
connecting the conductive patterns and forming a protection layer
on the conductive line.
[0022] According to still another aspect of the present invention,
there is provided a method for manufacturing an inductor. The
method comprises forming a mold layer including hole arrays on a
substrate including a conductive structure and forming a diffusion
prevention layer on the inner surfaces of the hole arrays and on
the mold layer. The method further comprises forming a first seed
layer on the diffusion prevention layer, forming a capping layer on
the first seed layer, and forming second seed layer patterns on
portions of the capping layer positioned in the hole arrays. The
method further comprises forming conductive patterns from the
second seed layer patterns to fill the hole arrays, growing the
conductive patterns on the mold layer and connecting the conductive
patterns, thereby forming a conductive line on the mold layer, and
forming a protection layer on the conductive line.
[0023] According to the present invention, an inductor including
spiral conductive lines may be readily manufactured at relatively
low cost by employing an electrolytic process or an electroless
plating process. The width and height of the conductive lines are
adjusted to desired values by adjusting the growth rate of the
conductive patterns using the electrolytic plating process or the
electroless plating process. The desired height of the conductive
lines is often relatively high compared to the height of a
conventional inductor. Adjusting the height of the conductive lines
permits the inductor formed by the present invention to have a
relatively high spiral structure on the substrate.
[0024] The manufacturing time and cost associated with forming the
inductor are potentially reduced by a significant margin because an
additional process for electrically connecting the inductor to a
lower wiring structure formed on the substrate is not required.
Accordingly, the inductor is preferably formed directly on a
conventional substrate without any additional process so that an
inductor having a relatively high spiral structure is readily
formed on the substrate at low cost using a conventional apparatus
for manufacturing the inductor.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The accompanying drawings illustrate several selected
embodiments of the present invention. In the drawings:
[0026] FIGS. 1A to 1C are cross-sectional views illustrating a
method for manufacturing a conventional inductor;
[0027] FIG. 2 is a planar view illustrating an exemplary inductor
formed in accordance with one aspect of the present invention;
[0028] FIGS. 3A to 3E are cross-sectional views of the inductor
shown in FIG. 2 taken along the line from I to I' in FIG. 2.
[0029] FIGS. 3A to 3E illustrate a method for manufacturing the
inductor shown in FIG. 2;
[0030] FIG. 4A is a planar view further illustrating the mask
element shown in FIG. 3B;
[0031] FIG. 4B is a planar view further illustrating a mask for
forming conductive patterns according to one aspect of the present
invention;
[0032] FIG. 5A is an electron micrograph image illustrating
cross-sections of the conductive patterns in FIG. 3C;
[0033] FIG. 5B is an electron micrograph image illustrating a
planar view of the inductor in FIG. 3E;
[0034] FIG. 6 is a cross-sectional view illustrating an exemplary
inductor according to another aspect of the present invention;
[0035] FIGS. 7A to 7E are cross-sectional views illustrating a
method for manufacturing the exemplary inductor in FIG. 6;
[0036] FIG. 8 is an electron micrograph image illustrating
cross-sections of conductive patterns in FIG. 7C;
[0037] FIGS. 9A to 9E are cross-sectional views illustrating a
method for manufacturing an inductor according to yet another
aspect of the present invention;
[0038] FIGS. 10A and 10B are electron micrograph images
illustrating cross-sections of conductive patterns in FIG. 9D;
[0039] FIG. 11 is a planar view illustrating an exemplary inductor
according to still another aspect of the present invention;
[0040] FIG. 12 is a cross-sectional view illustrating a section of
the inductor shown in FIG. 11 taken along the line from II to II';
and,
[0041] FIGS. 13A to 13D are cross-sectional views illustrating a
method for manufacturing the inductor in FIG. 12.
DETAILED DESCRIPTION OF THE INVENTION
[0042] The present invention will now be described more fully with
reference to the accompanying drawings, in which several
embodiments of the present invention are shown. In the drawings,
the thickness of layers and regions are exaggerated for clarity and
like reference numerals refer to like elements throughout. It will
be understood that when an element such as a layer, region or
substrate is referred to as being "on" or "onto" another element,
the layer is either directly on the other element or intervening
elements may also be present.
[0043] FIG. 2 is a planar view illustrating an inductor according
to one aspect of the present invention. In FIG. 2, an inductor 200
includes a spiral conductive line 190. The spiral conductive line
190 is electrically connected to a contact 160 formed as a part of
a lower wiring element formed on a substrate. Thus, the spiral
conductive line 190 is positioned over the lower wiring including
the contact 160 and formed in a spiral structure. The conductive
line 190 is preferably formed by connecting a plurality of
conductive patterns grown from a seed layer (not shown).
[0044] The inductor 200 typically includes the seed layer formed
over the substrate. A multi-layer structure including an insulating
interlayer or a conductive layer is typically formed between the
substrate and the seed layer.
[0045] FIGS. 3A to 3E are cross-sectional views taken along a line
extending from I to I' in FIG. 2. FIGS. 3A to 3E illustrate a
method for manufacturing the inductor of FIG. 2.
[0046] Referring to FIG. 3A, an insulation layer 150 is formed on a
substrate (not shown) including a lower conductive structure. An
opening 155 is formed through the insulation layer 150 by partially
etching the insulation layer 150 using a photolithography process.
The lower conductive structure typically includes a word line, a
bit line, a conductive pattern, and a pad. The opening 155 exposes
a portion of a lower wiring (not shown) electrically connected to
the lower conductive structure.
[0047] A conductive layer is formed on insulation layer 150 to fill
the opening 155. The conductive layer is typically formed using
conductive material such as metal or polysilicon doped with
impurities. The conductive layer is partially removed by a chemical
mechanical polishing (CMP) process, an etch back process, a
combination of a CMP process and an etch back process, or a
photolithography process, until the insulation layer 150 is
exposed. As a result of partially removing the conductive layer, a
contact 160 electrically connected to the lower wiring is formed in
the opening 155. The lower wiring including the contact 160 is
electrically connected to the lower conductive structure positioned
on the substrate.
[0048] A diffusion prevention layer 165 is formed on the contact
160 and the insulation layer 150. The diffusion prevention layer
165 typically has a single-layer structure or a multi-layer
structure. The single layer structure typically uses tantalum (Ta),
tantalum nitride (TaN), tantalum-aluminum nitride (TaAlN), tantalum
silicide (TaSi.sub.2), titanium (Ti), titanium nitride (TiN),
titanium-silicon nitride (TiSiN), or tungsten nitride (WN). The
multi-layer structure typically uses a mixture including at least
two elements from the group consisting of tantalum (Ta), tantalum
nitride (TaN), tantalum-aluminum nitride (TaAlN), tantalum silicide
(TaSi.sub.2), titanium (Ti), titanium nitride (TiN),
titanium-silicon nitride (TiSiN), and tungsten nitride (WN). The
diffusion prevention layer 165 typically has a thickness of about
50 to 1,000 .ANG.. The diffusion prevention layer 165 prevents
copper included in a conductive pattern 185 (see FIG. 3C) from
diffusing into the underlying structure.
[0049] A seed layer 170 is formed on the diffusion prevention layer
165. The seed layer 170 is typically formed by a chemical vapor
deposition (CVD) process or a physical vapor deposition (PVD)
process such as a sputtering process or a vacuum evaporation
process. Preferably, the seed layer 170 is formed by a PVD process
and has a thickness of about 100 to 5,000 .ANG.. Alternatively, the
seed layer 170 is formed using a conductive material that
substantially prevents formation of a surface insulation film such
as an oxide film or a nitride film. For example, the seed layer 170
is formed using platinum (Pt), palladium (Pd), nickel (Ni), silver
(Ag), gold (Au) or an alloy thereof.
[0050] A photoresist film is coated on the seed layer 170. The
photoresist film is exposed to light through a mask 220 having a
plurality of holes as shown in FIG. 3B. The photoresist film serves
as a mold layer for forming the conductive line 190, as shown in
FIG. 3D. The photoresist film typically has a thickness of about
500 to 30,000 .ANG. so as to sufficiently grow conductive patterns
185 (See, FIG. 3C).
[0051] FIG. 4A is a planar view further illustrating the mask 220
in FIG. 3B.
[0052] Referring to FIGS. 3B and 4A, the mask 220 includes a
pattern 215 having a plurality of hole arrays arranged in a spiral
shape so as to form the inductor 200 having the conductive lines
190. When the photoresist film is exposed using the mask 220, the
photoresist film forms a plurality of hole arrays in the spiral
shape of the mask 220. After the exposed photoresist film is
developed, a photoresist pattern 175 including a plurality of
trenches or hole arrays 180 arranged in the spiral shape of the
mask 220 is formed on the seed layer 170.
[0053] Although FIG. 4 shows a pair of spiral-shaped hole arrays
formed in the mask 220, the number and size of the hole arrays is
variable, and it changes in accordance with the size and structure
of the inductor 200.
[0054] FIG. 4B is a planar view illustrating a mask 230 for forming
a conductive line according to one particular embodiment of the
present invention.
[0055] Referring to FIG. 4B, mask 230 includes a pattern 225 having
a plurality of trenches spirally arranged according to a structure
of an inductor. The size and number of trenches varies according to
the size and structure of the inductor.
[0056] Referring now to FIG. 3B, the photoresist film is exposed
and developed using mask 220 and as a result, a photoresist pattern
175 having hole arrays 180 is formed on seed layer 170. Trenches or
hole arrays 180 partially expose seed layer 170. Trenches or hole
arrays 180 preferably have a depth of about 500 to 30,000
.ANG..
[0057] According to one aspect of the present invention an
anti-reflective layer (ARL) is formed on the photoresist film so as
to ensure a process margin in a photolithography process. The
photoresist pattern 175 is then formed on the seed layer 170 by
patterning the photoresist film using the ARL as an etching mask.
The ARL typically has a thickness of about 50 to 1,000 .ANG..
[0058] In another aspect of the present invention, an etch-stop
layer is formed on the seed layer 170 in consideration of a
successive etching process. The photoresist pattern 175 is then
formed on the etch-stop layer. The etch-stop layer is typically
formed using nitride such as silicon nitride.
[0059] Referring to FIG. 3C, a plurality of conductive patterns 185
is formed on the photoresist pattern 175 from the seed layer 170 by
an electrolytic plating process to fill trenches or hole arrays
180. The electrolytic plating process is typically performed with a
current density of about 20 to 40 mA/cm.sup.2 using a plating
solution including a copper sulfate (CuSO.sub.4) solution, a
sulfuric acid (H.sub.2SO.sub.4) solution, and a solution including
chlorine ions (Cl.sup.-). The conductive patterns 185 are grown
from the seed layer 170 in a direction indicated by arrows in FIG.
3C so that upper portions of the conductive patterns 185 are formed
on the photoresist pattern 175. When the conductive patterns 185
are grown in the hole arrays 180 from the seed layer 170, growth
within the hole arrays 180 accelerates in a vertical direction
relative to the substrate, whereas the growth within the hole
arrays 180 is limited along a horizontal direction relative to the
substrate. Once the conductive patterns 185 fill the hole arrays
180, upper portions of the conductive patterns 185 form protrusions
on the photoresist pattern 175.
[0060] Referring to FIG. 3D, the electrolytic plating process used
to form the conductive patterns 185 of FIG. 3C is extended to form
conductive line 190 on the photoresist pattern 175. In other words,
the conductive patterns 185 are vertically and horizontally grown
on the photoresist pattern 175 until the conductive patterns 185
become connected to each other, thus forming the conductive line
190 on the photoresist pattern 175. When the conductive line 190 is
formed by extending the electrolytic plating process, an upper
portion of the conductive line 190 typically has a mushroom
shape.
[0061] A summary of the process used to form the conductive line
190, including some additional details, is now given. The
conductive patterns 185 are vertically grown from the seed layer
170. Next, the conductive patterns 185 are horizontally and
vertically grown on the photoresist pattern 175 as shown in FIGS.
3C and 3D. Then, adjacent conductive patterns 185 are connected to
each other on the photoresist pattern 175 according to their
vertical and horizontal growth, resulting in the formation of the
conductive line 190. The width and thickness of the conductive line
190 are adjusted to desired values by adjusting the vertical and
horizontal growth of the conductive patterns 185. To achieve this
result, the electrolytic plating process is extensively performed
to further grow the conductive patterns 185 once they have already
filled the hole arrays 180. The further growth causes adjacent
conductive patterns 185 to become connected to each other, thus
forming the conductive line 190 on the photoresist pattern 175. In
order to form the conductive line 190 with the desired width and
thickness, the growth of the conductive patterns 185 is
advantageously adjusted after filling the hole arrays 180. The
conductive line 190 preferably has a thickness of about 1,000 to
100,000 .ANG.. The conductive line 190 typically has a sufficient
thickness on the photoresist pattern 175 because the horizontal
growth of the conductive patterns 185 is limited in the hole arrays
180.
[0062] Referring to FIG. 3E, the photoresist pattern 175 is
partially removed except for a portion of the photoresist pattern
175 positioned beneath the conductive line 190. When the
photoresist pattern 175 is partially removed, the seed layer 170 is
partially exposed. The exposed seed layer 170 and the diffusion
prevention layer 165 are partially removed to complete the
conductive lines 190 having spiral structures. The photoresist
pattern 175, the seed layer 170 and the diffusion prevention layer
165 are partially removed by a wet etching process. The wet etching
process is executed using an organic stripper, a solution including
ozone (O.sub.3) at a relatively high concentration, or a standard
cleaning (SC) solution including carbon dioxide (CO.sub.2).
Alternatively, the photoresist pattern 175 may be partially removed
by an ashing process and/or a stripping process. In one embodiment
of the present invention, the seed layer 170 and the diffusion
prevention layer 165 may be partially removed using a mixture of a
hydrogen fluoride (HF) solution and a hydrogen peroxide
(H.sub.2O.sub.2) solution or a mixture of a hydrogen fluoride (HF)
solution and a nitric acid (HNO.sub.3) solution. When the ARL is
formed on the photoresist pattern 175, the ARL and the photoresist
pattern 175 are simultaneously removed.
[0063] A protection layer 195 is formed to enclose the conductive
line 190, thereby completing the inductor 200, which preferably
comprises a plurality of the conductive lines 190. The inductor 200
has a spiral structure formed by the plurality of the conductive
lines 190. The protection layer 195 is typically formed using
silicon carbide (SiC) or silicon nitride (SiN). Alternatively, the
protection layer 195 has a multi-layer structure including at least
two films of silicon carbide, silicon nitride and silicon
oxycarbide. The protection layer 195 preferably has a thickness of
about 100 to 1,000 .ANG.. The protection layer 195 is formed on a
sidewall of a remaining portion of the diffusion prevention layer
165, a sidewall of a remaining portion of the seed layer 170, a
sidewall of a remaining portion of the photoresist pattern 175, and
on the conductive lines 190 of the spiral structure.
[0064] FIG. 5A is an electron micrograph image displaying cross
sections of conductive patterns in FIG. 3C. FIG. 5B is an electron
micrograph image showing a plan view of the inductor in FIG.
3E.
[0065] Referring to FIGS. 5A and 5B, the conductive patterns 185
are vertically and horizontally grown by the above-described
electrolytic plating process to form the inductor 200 including
spiral conductive lines 190 on the photoresist pattern 175. Each of
the conductive patterns 185 has an upper portion with a mushroom
shape.
[0066] FIG. 6 is a cross sectional view illustrating an inductor
according to one aspect of the present invention. According to this
aspect, a method for manufacturing conductive lines comprises
processes identical to the processes described with reference to
FIGS. 3A to 3D.
[0067] Referring to FIG. 6, a method for manufacturing an inductor
300 is described. The inductor 300 is manufactured on a substrate
having an insulation layer 250, which has a contact 260 running
through it as previously described. A photoresist pattern for
forming conductive lines 290 is completely removed and a seed layer
270 and a diffusion prevention layer 265 are partially removed.
Thus, lower portions of conductive lines 290 are exposed.
[0068] A protection layer 295 is formed on the insulation layer
250, on sidewalls of the exposed seed layer 270 and diffusion
prevention layer 265, and on the conductive lines 290. The
protection layer 295 typically has a single-layer structure of
silicon carbide, silicon oxycarbide, or silicon nitride or a
multi-layer structure having layers chosen from the group
consisting of silicon carbide, silicon oxycarbide and silicon
nitride. The protection layer 295 is formed from the upper portions
of the conductive lines 290 to the insulation layer 265 to thereby
entirely enclose the conductive lines 290.
[0069] FIGS. 7A to 7E are cross-sectional views illustrating a
method of manufacturing the inductor in FIG. 6. In FIGS. 7A to 7E,
a substrate including a lower conductive structure having word
lines, bit lines and pads is not shown.
[0070] Referring to FIG. 7A, an insulation layer 350 is formed on
the substrate. The insulation layer 350 is partially etched to form
an opening 355 that exposes a lower wiring electrically connected
to the lower conductive structure.
[0071] A conductive layer is formed on the insulation layer 350 to
fill the opening 355. The conductive layer may be formed using
metal or doped polysilicon. The conductive layer is then partially
removed by a CMP process, an etch back process or a combination of
a CMP process and an etch back process. The conductive layer is
partially removed until the insulation layer 350 is exposed. Thus,
a contact 360 electrically connected to the lower wiring is formed
in the opening 355. The lower wiring including the contact 360 is
electrically connected to the lower conductive structure formed on
the substrate.
[0072] A mold layer 365 is formed on the insulation layer 350 and
the contact 360. The mold layer 365 may be formed using oxide or
photoresist. The mold layer 365 is partially etched to form a
plurality of trenches or hole arrays 370 that expose the contact
360 as described above. The mold layer 365 typically has a
thickness of about 500 to 30,000 .ANG. so as to easily form a
conductive line 400 (see FIG. 7D) and to sufficiently isolate the
lower conductive structure from the conductive line 400.
[0073] When the mold layer 365 is formed using oxide, a photoresist
film is additionally formed on the mold layer 365. The photoresist
film is exposed using the mask shown in FIG. 4A or FIG. 4B to form
a photoresist pattern including a plurality of hole arrays or
trenches. After an ARL having a thickness of about 50 to 1,000
.ANG. is additionally formed on the photoresist film, the
photoresist pattern is formed on the mold layer 365. Subsequently,
the mold layer 365 is etched using the photoresist pattern as an
etching mask to thereby form trenches or hole arrays 370 having
depth of about 500 to 1,000 .ANG. through the mold layer 365.
[0074] When the mold layer 365 is formed using photoresist, the
mold layer 365 is preferably directly exposed using the mask in
FIG. 4A or FIG. 4B to thereby form the trenches or hole arrays 370
through the mold layer 365, wherein the trenches or hole arrays 370
have inner surfaces.
[0075] Referring to FIG. 7B, a diffusion prevention layer 375 is
formed on the mold layer 365, on the contact 360, and on the inner
surfaces of the trenches or hole arrays 370. The diffusion
prevention layer 375 has a thickness of about 50 to 1,000 .ANG..
The diffusion prevention layer 375 typically has a single-layer
structure or a multi-layer structure. The single-layer structure
typically includes tantalum, tantalum nitride, tantalum-aluminum
nitride, tantalum-silicon nitride, tantalum silicide, titanium,
titanium nitride, tungsten nitride, titanium-silicon nitride, or an
alloy thereof. The multi-layer structure typically includes at
least two elements from the group consisting of tantalum, tantalum
nitride, tantalum-aluminum nitride, tantalum-silicon nitride,
tantalum silicide, titanium, titanium nitride, tungsten nitride,
titanium-silicon nitride, and any alloy thereof.
[0076] A first seed layer 380 is formed on diffusion prevention
layer 375 by a CVD process or a PVD process such as a sputtering
process or a vacuum evaporation process. The first seed layer 380
has a thickness of about 100 to 5,000 .ANG.. The first seed layer
380 is preferably formed using copper, platinum, palladium, nickel,
silver, gold, or an alloy thereof.
[0077] A capping layer 385 is formed on the first seed layer 380
using a metal such as aluminum. The capping layer 385 has a
thickness of about 100 to 500 .ANG.. When a portion of a second
seed layer 390 on the mold layer 365 is removed, a metal oxide film
is formed on the capping layer 385 as a result of oxidation in
metal in the capping layer 385. That is, an upper portion of the
capping layer 385 except other portion of the capping layer 385
formed in the hole arrays 370 is converted into an insulation film
of metal oxide so that the capping layer 385 may selectively
restrain growth of conductive patterns 395. (See, FIG. 7C).
Therefore, the conductive patterns 395 may rapidly grow in the hole
arrays 370, whereas the conductive patterns 395 may slowly grow on
the metal oxide film of the capping layer 385. The second seed
layer 390 is formed on capping layer 385 using copper, platinum,
palladium, nickel, silver, gold or an alloy thereof.
[0078] Referring to FIG. 7C, to perform a selective electrolytic
plating process, a portion of the second seed layer 390 positioned
on the mold layer 365 is removed by a CMP process, an etch back
process or a combination of a CMP process and an etch back process.
As a result, the second seed layer patterns 393 are formed on the
inner surfaces of the hole arrays 370. The diffusion prevention
layer 375, the first seed layer 380, the capping layer 385 and the
second seed layer patterns 393 are successively formed on the inner
surfaces of the hole arrays 370, whereas the second seed layer
patterns 393 are not formed on the mold layer 365.
[0079] The conductive patterns 395 selectively and vertically grow
from the second seed layer patterns 393 to fill the hole arrays 370
using the selective electrolytic plating process. The selective
electrolytic plating process is carried out with a current density
of about 20 to 40 mA/cm.sup.2 using a plating solution that
includes a copper sulfate solution, a sulfuric acid solution, and a
solution including chlorine ions. As described above, since the
horizontal growth of the conductive patterns 395 is limited in the
hole arrays 370, the conductive patterns 395 are vertically grown
from the second seed layer patterns 393 in the hole arrays 370.
When the selective electrolytic plating process is continually
performed, the conductive patterns 395 filling the hole arrays 370
grow horizontally and vertically on the mold layer 365. The capping
layer 385 including the metal oxide film restrains the horizontal
growth of the conductive patterns 395 in the hole arrays 370.
However, because a bottleneck structure is formed at upper portions
of the hole arrays 370 due to the capping layer 385, the conductive
patterns 395 grow horizontally and vertically after the hole arrays
370 are filled with conductive patterns 395. The conductive
patterns 395 filling the hole arrays 370 continuously grow in
horizontal and vertical directions as indicated by arrows so that
adjacent conductive patterns 395 become connected to one another to
form the conductive line 400 having a desired width and height.
[0080] FIG. 8 is an electron micrograph image displaying
cross-sections of conductive patterns in FIG. 7C.
[0081] As shown in FIGS. 7C and 8, although the horizontal growth
of the conductive patterns 395 is restrained in the hole arrays
370, the conductive patterns 395 grow both vertically and
horizontally after filling hole arrays 370. As a result, adjacent
conductive patterns 395 become connected to one another, thereby
forming a conductive line 400.
[0082] Referring to FIG. 7D, the conductive line 400 having a
desired width and height is formed on the mold layer 365 from the
second seed layer patterns 393 by connecting adjacent conductive
patterns 395. The conductive patterns 395 are connected by
continuously performing the electrolytic plating process. After the
conductive patterns 395 fill the hole arrays 370, the growth rate
of the conductive patterns 395 may be advantageously adjusted to
form the conductive line 400 having a height of about 1,000 to
100,000 .ANG..
[0083] Referring to FIG. 7E, the capping layer 385, the first seed
layer 380 and the diffusion prevention layer 375 are partially
removed except for portions covered by conductive line 400. A
protection layer 405 is formed to cover the conductive line 400,
thereby forming an inductor 430 having a spiral structure including
a plurality of conductive lines 400. The capping layer 385, the
first seed layer 380 and the diffusion prevention layer 375 may be
partially removed using a mixture of a hydrogen fluoride solution
and a hydrogen peroxide solution, or a mixture of a hydrogen
fluoride solution and a nitric acid solution.
[0084] In one embodiment of the present invention, after the mold
layer 365 is removed, the protection layer 405 is formed on the
conductive line 400. When the mold layer 365 is formed using
photoresist, the mold layer 365 is preferably removed using an
organic stripper, a solution including ozone at relatively high
concentration, or an SC solution including carbon dioxide. When the
mold layer 365 is formed using oxide, the mold layer 365 is
preferably removed by a wet etching process using a sulfuric acid
solution or a dry etching process such as a reactive ion etching
process or a plasma etching process.
[0085] Referring now to FIG. 7E, the protection layer 405 is
preferably formed using silicon carbide or silicon nitride. The
protection layer 405 has a thickness of about 100 to 1,000 .ANG..
The protection layer 405 encloses exposed sidewalls of the capping
layer 385, the first seed layer 380 and the diffusion prevention
layer 375 beneath the conductive line 400.
[0086] In one embodiment of the present invention, the protection
layer 405 has a multi-layer structure including at least elements
from the group consisting of silicon carbide, silicon nitride and
silicon oxycarbide.
[0087] FIGS. 9A through 9E are cross-sectional views illustrating a
method of manufacturing an inductor according to one aspect of the
present invention.
[0088] Referring to FIG. 9A, an insulation layer 450 is formed on a
substrate including a lower conductive structure. The insulation
layer 450 is preferably formed using oxide or nitride. The
insulation layer 450 is partially etched by a photolithography
process and then an opening 455 is formed through the insulation
layer 450. The lower conductive structure typically includes word
lines, bit lines and pads. The opening 455 exposes a lower wiring
electrically connected to the lower conductive structure.
[0089] A conductive layer of metal or doped polysilicon is formed
on the insulation layer 450 to fill the opening 455. The conductive
layer is partially removed by a CMP process, an etch back process,
or a combination of a CMP process and an etch back process, thereby
forming a contact 460 in the opening 455. The contact 460 is
electrically connected to the lower wiring. Hence, the lower wiring
including the contact 460 is electrically connected to the lower
conductive structure.
[0090] A mold layer 465 having a thickness of about 500 to 30,000
.ANG. is formed on the insulation layer 450 and the contact 460.
The mold layer 465 may be formed using oxide or photoresist. The
mold layer 465 is partially etched to form a plurality of trenches
or hole arrays 470 exposing the contact 460 as described above. The
trenches or the hole arrays 470 have depth of about 1,000 to 30,000
.ANG..
[0091] When the mold layer 465 is formed using oxide, a photoresist
film is additionally formed on the mold layer 465. The photoresist
film is exposed using one of the masks shown in FIG. 4A and FIG. 4B
to form a photoresist pattern including a plurality of hole arrays
or trenches. An ARL having a thickness of about 50 to 1,000 .ANG.
is typically also formed on the photoresist film and then the
photoresist pattern is formed on the mold layer 465. Subsequently,
the mold layer 465 is etched using the photoresist pattern as an
etching mask to thereby form the trenches or hole arrays 470
through the mold layer 465.
[0092] When mold layer 465 is formed using photoresist, the mold
layer 465 is preferably directly exposed using one of the masks in
FIG. 4A and FIG. 4B without forming an additional photoresist film,
thereby forming the trenches or hole arrays 470 through the mold
layer 465, wherein the trenches or hole arrays 470 have inner
surfaces. An additional ARL is preferably formed on the mold layer
465 to ensure a process margin for a photolithography process.
[0093] Referring to FIG. 9B, a diffusion prevention layer 475
having a thickness of about 50 to 1,000 .ANG. is formed on the mold
layer 465, on vcontact 460 and on the inner surfaces of the hole
arrays 470. The diffusion prevention layer 475 typically has a
single-layer structure or a multi-layer structure. The single-layer
structure typically includes tantalum, tantalum nitride,
tantalum-aluminum nitride, tantalum-silicon nitride, tantalum
silicide, titanium, titanium nitride, tungsten nitride,
titanium-silicon nitride, or an alloy thereof. The multi-layer
structure typically includes at least two elements from the group
consisting of tantalum, tantalum nitride, tantalum-aluminum
nitride, tantalum-silicon nitride, tantalum silicide, titanium,
titanium nitride, tungsten nitride, titanium-silicon nitride, and
any alloy thereof.
[0094] A seed layer 480 having a thickness of about 100 to 5,000
.ANG. is formed on the diffusion prevention layer 475 by a CVD
process or a PVD process such as a sputtering process or a vacuum
evaporation process. The seed layer 480 is preferably formed using
copper, platinum, palladium, nickel, silver, gold, or an alloy
thereof.
[0095] Referring to FIG. 9C, seed layer patterns 483 are formed on
the contact 460 and on the diffusion prevention layer 475
positioned on the inner surfaces of the hole arrays 470 to achieve
a selective electroless plating process. The seed layer patterns
483 are formed by partially removing the seed layer 480 using a CMP
process, an etch back process or a combination of a CMP process and
an etch back process until the diffusion prevention layer 475 is
exposed. As a result, the diffusion prevention layer 475 and the
seed layer patterns 483 are positioned on the inner surfaces of the
hole arrays 470, whereas only the diffusion prevention layer 475 is
positioned on the mold layer 465.
[0096] Referring to FIG. 9D, using the selective electroless
plating process, conductive patterns 485 are formed from the seed
layer patterns 483 to fill the hole arrays 470. The electroless
plating process is carried out using a copper sulfate solution
including a reducing agent such as formaldehyde or hydrazine. As
described above, since the horizontal growth of the conductive
patterns 485 is limited in the hole arrays 470, the conductive
patterns 485 are vertically grown from the seed layer patterns 483
in the hole arrays 470. When the electroless plating process is
continually performed, the conductive patterns 485 fill the hole
arrays 470 and then grow horizontally and vertically on the mold
layer 465. The conductive patterns 485 filling the hole arrays 470
continuously grow in the horizontal and vertical directions
indicated by arrows so that adjacent conductive patterns 485 become
connected to one another to form a conductive line 490 having a
desired width and height.
[0097] FIGS. 10A and 10B are electron micrograph images
illustrating cross sections of conductive patterns 485 in FIG.
9D.
[0098] Referring to FIGS. 9D, 10A and 10B, as the electroless
plating process proceeds, the conductive patterns 485 grow
vertically from the seed layer patterns 483 to fill the hole arrays
470. Then, the conductive patterns 485 grow vertically and
horizontally on the mold layer 465. In the present embodiment, the
conductive patterns 485 are formed by the electroless plating
process, causing conductive patterns 485 have relatively dense
structures.
[0099] Referring to FIG. 9E, the electroless plating process is
continually performed to connect adjacent conductive patterns 485
grown from the seed layer patterns 483. The conductive patterns 485
grow continuously on the mold layer 465 in vertical and horizontal
directions and as a result adjacent conductive patterns 485 become
connected to one another on the mold layer 465. As shown in FIGS.
9D, 10A and 10B, after the conductive patterns 485 grow from the
seed layer patterns 483 in the vertical direction, they grow on the
mold layer 465 in vertical and horizontal directions. The
conductive line 490 is formed by connecting the conductive patterns
485. The growth rate of the conductive patterns 485 is typically
adjusted after the conductive patterns 485 fill the hole arrays
470, in order to form the conductive line 490 with a desired width
and height.
[0100] Referring now to FIG. 9E, a protection layer 495 having a
thickness of about 100 to 1,000 .ANG. is formed on the mold layer
465 to enclose the conductive line 490. The protection layer 495
may be formed using silicon carbide or silicon nitride.
[0101] A portion of the protection layer 495 positioned on the mold
layer 465 is removed to complete the protection layer 495 enclosing
the conductive line 490. As a result, an inductor 500 having spiral
conductive lines 490 is formed on the substrate.
[0102] In one embodiment of the present invention, after the mold
layer 465 is removed, the protection layer 495 is formed to enclose
the conductive line 490. Since the diffusion prevention layer 475
positioned beneath the conductive line 490 is not removed, a
sidewall of the diffusion protection layer 475 is also enclosed by
the protection layer 495.
[0103] FIG. 11 is a planar view illustrating an inductor in
accordance with one embodiment of the present invention and FIG. 12
is a cross-sectional view illustrating a section of the inductor in
FIG. 11 taken along the line extending from II to II'.
[0104] Referring to FIGS. 11 and 12, an inductor 600 includes a
spiral conductive line 590 directly connected to a lower wiring 560
including pads 570 for input-output of electrical signals. In other
words, in the inductor 600, spiral conductive line 590 is directly
connected to end portions (pads 570) of the lower wiring 560
without an additional electrical contact connecting it to the lower
wiring 560. Omitting the additional electrical contact facilitates
a simpler, lower-cost manufacturing processes because it eliminates
the need for processes forming the contact.
[0105] An opening 515 is formed through a portion of the lower
wiring 560 where the spiral conductive line 590 passes over it so
as to prevent the spiral conductive line 590 from connecting to the
lower wiring 560. The spiral conductive line 590 is directly
connected to the end portions (pads 570) of the lower wiring 560,
whereas the spiral conductive line 590 has no contact with the
lower wiring 560 because the opening 515 is formed through the
portion of the lower wiring 560.
[0106] FIGS. 13A to 13D are cross-sectional views illustrating a
method for manufacturing the inductor in FIG. 12.
[0107] Referring to FIG. 13A, an insulation layer 550 is formed on
a substrate including a lower conductive structure. The insulation
layer 550 is typically formed using oxide or nitride.
[0108] A conductive layer is formed on the insulation layer 550
using metal or doped polysilicon to form a lower wiring 560 on the
insulation layer 560. As shown in FIG. 11, the conductive layer is
patterned to form the lower wiring 560, which is electrically
connected to the lower conductive structure. An opening 515 having
a predetermined width is simultaneously formed through a portion of
the lower wiring 560 where a spiral conductive line 590 (see FIG.
13C) passes over it. The opening 515 preferably has a width
slightly greater than a width of the spiral conductive line
590.
[0109] Referring to FIG. 13B, a mold layer 565 having a thickness
of about 500 to 30,000 .ANG. is formed on the lower wiring 560 to
fill the opening 515. The mold layer 565 may be formed using oxide
or photoresist. The mold layer 565 is partially etched to form a
plurality of holes that simultaneously expose end portions (that
is, pads) of the lower wiring 560 and a portion of the insulation
layer 550 through the opening 515. Each of the holes formed through
the mold layer 565 has a depth of about 500 to 30,000 .ANG.. As
described above, a photoresist film is additionally formed on the
mold layer 565 when the mold layer 565 is formed using oxide. The
photoresist film is exposed using a mask substantially similar to
that of FIG. 4A or FIG. 4B to form a photoresist pattern including
a plurality of holes. An ARL having a thickness of about 50 to
1,000 .ANG. is typically additionally formed on the photoresist
film. The mold layer 565 is then etched using the photoresist
pattern as an etching mask to form the holes through the mold layer
565. When the mold layer 565 is formed using photoresist, the mold
layer 565 may be directly exposed using a mask substantially
similar to that of FIG. 4A or FIG. 4B without forming an additional
photoresist film, thereby forming the holes through the mold layer
565, wherein the holes have inner surfaces. An additional ARL may
be directly formed on the mold layer 565 to ensure a process margin
of a photolithography process.
[0110] A diffusion prevention layer 575 having a thickness of about
50 to 1,000 .ANG. is formed on the exposed end portions of the
lower wiring 560, on the exposed portion of the insulation layer
550, on the inner surfaces of the holes, and on the mold layer 565.
The diffusion prevention layer 575 typically has a single-layer
structure or a multi-layer structure. The single-layer structure
typically includes tantalum, tantalum nitride, tantalum-aluminum
nitride, tantalum-silicon nitride, tantalum silicide, titanium,
titanium nitride, tungsten nitride, titanium-silicon nitride, or an
alloy thereof. The multi-layer structure typically includes at
least two elements from the group consisting of tantalum, tantalum
nitride, tantalum-aluminum nitride, tantalum-silicon nitride,
tantalum silicide, titanium, titanium nitride, tungsten nitride,
titanium-silicon nitride, and any alloy thereof.
[0111] A seed layer having a thickness of about 100 to 5,000 .ANG.
is formed on the diffusion prevention layer 575 by a CVD process or
a PVD process. The seed layer is preferably formed using copper,
platinum, palladium, nickel, silver, gold, or an alloy thereof.
[0112] To achieve a selective electrolytic or electroless plating
process, seed layer patterns 580 are formed on the inner surfaces
of the holes and the end portions of the lower wiring 560 by
removing a portion of the seed layer positioned on mold layer 565.
The Seed layer patterns 580 may be formed by a CMP process, an etch
back process, or a combination of a CMP process and an etch back
process. Here, the diffusion prevention layer 575, which is
positioned on the mold layer 565, is not etched. Hence, the seed
layer patterns 580 and the diffusion prevention layer 575 are
positioned on the inner surfaces of the holes, whereas only the
diffusion prevention layer 575 is positioned on the mold layer
565.
[0113] Conductive patterns 585 are formed from the seed layer
patterns 580 to fill the holes by a selective electrolytic or
electroless plating process. The selective electrolytic plating
process is preferably performed with a current density of about 20
to about 40 mA/cm.sup.2 using a plating solution that includes a
copper sulfate solution, a sulfuric acid solution, and a solution
including chlorine ions. The selective electroless plating process
is preferably carried out using copper sulfate solution that
includes a reducing agent such as formaldehyde or hydrazine.
[0114] Because horizontal growth of the conductive patterns 585 may
be limited in the holes, the conductive patterns 585 are vertically
grown from the seed layer patterns 580 in the holes. The selective
electrolytic or electroless plating process is continuously
performed until the conductive patterns 585 fill the holes and then
it is continued in order to grow the conductive patterns 585 in
horizontal and vertical directions on the mold layer 565. The
conductive patterns 585 are continuously grown in horizontal and
vertical directions indicated by arrows so that adjacent conductive
patterns 585 become connected to one another.
[0115] The conductive patterns 585 are electrically connected to
the end portions of the lower wiring 560, whereas the conductive
patterns 585 are separated from another portion of the lower wiring
560 due to the opening 515. That is, the conductive patterns 585
are electrically isolated from the lower wiring 560 except for the
end portions of the lower wiring 560. As a result, the method of
manufacturing an inductor 600 (see FIG. 13C) may be simplified and
performed at lower cost by omitting an additional process involved
in the formation of a contact that electrically connects the
conductive patterns 585 to the lower wiring 560.
[0116] Referring to FIG. 13C, as the selective electrolytic or
electroless plating process proceeds, after the conductive patterns
585 vertically grow from the seed layer patterns 580 to fill the
holes, the conductive patterns 585 grow vertically and horizontally
on the mold layer 565. As a result, a conductive line 590 having a
desired width and height is formed on the mold layer 565 from the
seed layer patterns 580 by connecting the conductive patterns 585.
When the conductive patterns 585 are formed by the selective
electroless plating process, the conductive patterns 585 may have
relatively dense structures. Particularly, the conductive patterns
585 continuously grow on the mold layer 565 in the vertical and
horizontal directions so that adjacent conductive patterns 585 are
connected to one another on the mold layer 565. After the
conductive patterns 585 grow vertically from the seed layer
patterns 580, they grow vertically and horizontally on mold layer
565. The conductive line 590 is formed by the horizontal and
vertical growth of the conductive patterns 585. The growth rate of
the conductive patterns 585 is preferably adjusted after the
conductive patterns 585 fill the holes to form the conductive line
590 with a desired width and height on the mold layer 565.
[0117] Referring now to FIG. 13D, after a portion of the diffusion
prevention layer 575 positioned on the mold layer 565 is removed, a
protection layer 595 having a thickness of about 100 to 1,000 .ANG.
is formed on the mold layer 565 to enclose the conductive line 590.
The protection layer 595 may be formed using silicon carbide or
silicon nitride. Thus, the inductor 600, which has a plurality of
spiral conductive lines 590, is formed on the substrate. In one
embodiment of the present invention, after the mold layer 565 is
removed, the protection layer 595 is formed to entirely enclose the
conductive line 590.
[0118] In summary, according to the present invention, an inductor
including spiral conductive lines may be readily manufactured at a
relatively low cost by employing an electrolytic process or an
electroless plating process.
[0119] The inductor preferably includes a conductive line having a
desired width and height obtained by adjusting a growth rate of
conductive patterns grown with the electrolytic plating process or
the electroless plating process.
[0120] Because the desired height of the conductive line is
typically greater than that of a conventional inductor, the
inductor may have a spiral structure characterized by a large
height on a substrate.
[0121] The manufacturing time and cost required to form the
inductor may be greatly reduced because an additional process
typically required to electrically connect the inductor to a lower
wiring formed on the substrate is omitted. The inductor may be
directly formed on a conventional substrate without any additional
process so that the inductor having the large height may be readily
formed at low cost on the substrate using a conventional apparatus
for manufacturing an inductor.
[0122] The preferred embodiments disclosed in the drawings and the
corresponding written description are teaching examples. Those of
ordinary skill in the art will understand that various changes in
form and details may be made to the exemplary embodiments without
departing from the scope of the present invention which is defined
by the following claims.
* * * * *