U.S. patent application number 10/938478 was filed with the patent office on 2005-03-03 for fram capacitor stack clean.
Invention is credited to Hall, Lindsey H., Summerfelt, Scott R..
Application Number | 20050045590 10/938478 |
Document ID | / |
Family ID | 33451269 |
Filed Date | 2005-03-03 |
United States Patent
Application |
20050045590 |
Kind Code |
A1 |
Hall, Lindsey H. ; et
al. |
March 3, 2005 |
FRAM capacitor stack clean
Abstract
An embodiment of the invention is a method of cleaning a
material stack 2 that has a hard mask top layer 8. The method
involves cleaning the material stack 2 with a fluorine-based plasma
etch. The method further involves rinsing the material stack 2 with
a wet clean process.
Inventors: |
Hall, Lindsey H.; (Plano,
TX) ; Summerfelt, Scott R.; (Garland, TX) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
|
Family ID: |
33451269 |
Appl. No.: |
10/938478 |
Filed: |
September 10, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10938478 |
Sep 10, 2004 |
|
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10447581 |
May 28, 2003 |
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Current U.S.
Class: |
216/67 ; 134/1.1;
134/26; 216/83; 257/E21.009; 257/E21.253; 257/E21.311 |
Current CPC
Class: |
H01L 21/32136 20130101;
H01L 21/31122 20130101; G03F 7/423 20130101; H01L 21/02054
20130101; G03F 7/428 20130101; G03F 7/427 20130101; H01L 28/55
20130101; Y10S 134/902 20130101; G03F 7/42 20130101 |
Class at
Publication: |
216/067 ;
134/001.1; 134/026; 216/083 |
International
Class: |
C23F 001/00; B08B
006/00 |
Claims
1-16. (Cancelled)
17. A method of manufacturing a semiconductor wafer having a
ferroelectric capacitor stack having a hard mask top layer
comprising: forming a layer of bottom electrode material; forming a
layer of dielectric material over said layer of bottom electrode
material; forming a layer of top electrode material over said layer
of dielectric material; forming a layer of hard mask material over
said layer of top electrode material; forming a layer of
photoresist over said layer of hard mask material; patterning said
photoresist; etching said photoresist; etching said hard mask
material; ashing said photoresist; etching said layer of top
electrode material, said layer of dielectric material, and said
layer of bottom electrode material to form said ferroelectric
capacitor stack; cleaning said ferroelectric capacitor stack with a
fluorine-based plasma etchant; and rinsing said ferroelectric
capacitor stack with a wet clean process.
18. The method of claim 17 wherein said fluorine-based plasma
etchant is CF.sub.4/O.sub.2.
19. The method of claim 17 wherein said fluorine-based plasma
etchant is NF.sub.3.
20. The method of claim 17 wherein said fluorine-based plasma
etchant is C.sub.2F.sub.6.
21. The method of claim 17 wherein said wet clean process is a
deionized water rinse.
22. The method of claim 17 wherein said wet clean process is a
deionized water rinse followed by a hydrochloric acid rinse.
23. The method of claim 17 wherein said wet clean process is a
deionized water rinse followed by a phosphoric acid rinse.
24. The method of claim 17 wherein said wet clean process is a
deionized water rinse followed by an organic solvent rinse.
25. The method of claim 17 wherein said wet clean process is an
organic solvent rinse.
26. The method of claim 17 wherein said wet clean process is a
phosphoric acid rinse.
27. The method of claim 17 wherein said wet clean process is a
dilute HCl acid rinse.
28. The method of claim 17 wherein said rinsing step further etches
said ferroelectric capacitor stack.
29. The method of claim 17 wherein said rinsing step further
includes the use of ultrasonic energy.
30. The method of claim 17 wherein said layer of hard mask material
comprises a bottom layer of TiAlN, a middle layer of TiAlON, and a
top layer of TiAlN.
31. The method of claim 17 wherein said layer of dielectric
material is PZT.
32. A method of manufacturing a semiconductor wafer having a
ferroelectric capacitor stack comprising: sputter depositing a
first layer of iridium; metal organic chemical vapor depositing a
layer of PZT over said first layer of iridium; physical vapor
depositing a second layer of iridium over said layer of PZT;
reactive physical vapor depositing a layer of iridium oxide over
said second layer of iridium; sputter depositing a first layer of
TiAlN over said layer of iridium oxide; sputter depositing a layer
of TiAlON over said first layer TiAlN; sputter depositing a second
layer of TiAlN over said layer of TiAlON; forming a layer of
photoresist over said second layer of TiAlN; patterning said
photoresist; etching said photoresist; etching said second layer of
TiAlN said layer of TiAlON, and said first layer of TiAlN; ashing
said photoresist; etching said layer of iridium oxide, said second
layer of iridium, said layer of PZT, and said first layer of
iridium to form said ferroelectric capacitor stack; cleaning said
ferroelectric capacitor stack with a CF.sub.4/O.sub.2 plasma
etchant; rinsing said ferroelectric capacitor stack with deionized
water; and rinsing said ferroelectric capacitor stack with dilute
hydrochloric acid.
Description
BACKGROUND OF THE INVENTION
[0001] This invention relates to a method of cleaning the surface
of a ferroelectric capacitor stack in ferroelectric random access
memories.
BRIEF DESCRIPTION OF THE DRAWINGS
[0002] FIG. 1 is a cross-section view of semiconductor wafer having
a ferroelectric capacitor stack.
[0003] FIG. 2 is a flow diagram illustrating the process flow of
the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0004] The present invention is described with reference to the
attached figures, wherein similar reference numerals are used
throughout the figures to designate like or equivalent elements.
The figures are not drawn to scale and they are provided merely to
illustrate the instant invention. Several aspects of the invention
are described below with reference to example applications for
illustration. It should be understood that numerous specific
details, relationships, and methods are set forth to provide a full
understanding of the invention. One skilled in the relevant art,
however, will readily recognize that the invention can be practiced
without one or more of the specific details or with other methods.
In other instances, well-known structures or operations are not
shown in detail to avoid obscuring the invention.
[0005] Referring to the drawings, FIG. 1 depicts a cross-section
view of a ferroelectric capacitor stack 2. The ferroelectric
capacitor stack 2 is located within a ferroelectric random access
memory ("FRAM") array. In turn, the FRAM array is located between
the standard logic front-end 3 and back-end (not shown) of an
integrated circuit. The front-end 3 of the wafer (i.e. the portion
closest to the substrate) contains the transistor logic while the
FRAM array contains non-volatile memory. The device's interconnects
and metal lines--used to move electrical signals and power
throughout the device--are contained in the back-end portion of the
integrated circuit (i.e. fabricated over the FRAM array). Other
than the process for cleaning the ferroelectric capacitor stack 2
(described herein), the processing steps for creating the
ferroelectric memory array is any known fabrication process, such
as the fabrication process described in the commonly assigned
patent U.S. Pat. No. 6,548,343 (Ser. No. 09/702,985, TI Docket
Number TI-29970, filed Oct. 31, 2000), incorporated herein by
reference and not admitted to be prior art with respect to the
present invention by its mention in this section.
[0006] In general, a single capacitor memory cell (referred to as a
"1T/1C" or "1C" memory cell) has one transistor and one storage
capacitor. Furthermore, as shown in FIG. 1, the bottom electrode 5
of the ferroelectric storage capacitor is generally electrically
connected to the drain of a transistor. In the example application
shown in FIG. 1, the FRAM memory array is located between the
front-end module and the back-end module. However, other locations
for the FRAM memory array are within the scope of this invention.
For example, the FRAM array may be placed over the first level of
metallization or near the top end of the back-end module.
Furthermore, it is within the scope of this invention to have a
FRAM array containing a dual capacitor memory cell (comprising two
transistors and two ferroelectric capacitors) instead of a single
capacitor memory cell.
[0007] In the example wafer structure shown in FIG. 1, a barrier
layer 4 is located between the front-end module 3 and the bottom
electrode 5 of the ferroelectric capacitor. However, the use of a
barrier layer is optional. If a barrier layer is used, it may
protect the conductive material located in the front-end module 3.
Furthermore, a barrier layer may allow the oxygen stable bottom
electrode material to be thinner or allow a higher process
temperature to be used. In example application, the barrier layer 4
is comprised of TiAlN.
[0008] The FRAM memory array contains numerous FRAM memory cells.
The ferroelectric capacitor stack 2 within a FRAM memory cell
contains ferroelectric material, such as lead zirconate titanate
(called "PZT" based on its chemical formula: Pb(Zr, Ti)O.sub.3)
that functions as a capacitor dielectric 6 situated between a
bottom electrode 5 and a top electrode 7. In an example
application, the bottom electrode 5 is comprised of Ir and the top
electrode 7 is comprised of a stack of IrOx 9 and Ir 10.
[0009] Together, layers 11, 12, and 13 form a hard mask 8. The hard
mask 8 facilitates the proper shaping of the ferroelectric
capacitor stack 2 during the fabrication process. In the example
application the hard mask 8 is comprised of a material stack of
TiAlN 11, TiAlON 12, and TiAlN 13. The hard mask 8 is made thick
enough to retain its integrity during all etch processes (i.e.
50-500 nm thick). Furthermore, the hardmask is comprised of layers
of conductive material in order to electrically couple the
ferroelectric capacitor's top electrode 7 to the rest of the FRAM
array and/or the back-end module. In this example application, the
hard mask 8 is comprised of a top and bottom layer of TiIAlN
separated by a middle layer of TiAlON; however the hardmask may be
comprised of TiN, AlN, Ti, TiO.sub.2, Al, AlOx, TiAl, TiAlOx, or
any stack or combination thereof.
[0010] Referring again to the drawings, FIG. 2 is a flow diagram
illustrating the process flow of the invention. Other than process
steps 212 and 214, the process steps should be those that are
standard in the industry.
[0011] Step 200 is the optional formation of a barrier layer 4 over
the front-end module 3. Preferably, the barrier layer 4 is formed
by depositing TiAlN by reactive sputter deposition. However, other
deposition techniques such as chemical vapor deposition ("CVD") or
plasma enhanced CVD ("PECVD") may be used.
[0012] Next, the bottom electrode layer 5 is formed (step 202) on
the barrier layer 4 or directly on the front-end module 3. In the
example application, the bottom electrode is comprised of iridium
that is deposited by sputter deposition.
[0013] The capacitor dielectric layer 6 is formed on the bottom
electrode layer 5 (step 204). The capacitor dielectric is PZT in
the example application because it has the highest polarization and
the lowest processing temperature of the available ferroelectric
materials. However, other ferroelectric materials may be used, such
as doped PZT, doped and alloyed PZT, or strontium tantalite and
other layered perovskites. The preferred deposition technique for
PZT is metal organic chemical vapor deposition ("MOCVD"). However
other deposition techniques may be used, such as sol-gel or metal
organic decomposition.
[0014] The top electrode layer 7 is formed (step 206) on the
capacitor dielectric layer 6. In the example application, the top
electrode is comprised of two layers (9, 10). However, the top
electrode can be formed using just one layer. In the example
application, the iridium layer 9 is deposited by physical vapor
deposition ("PVD") and the iridium oxide layer is deposited by
reactive PVD.
[0015] In step 208, the hard mask layer 8 is formed, patterned, and
etched. In the example application the hard mask 8 is formed by a
material stack consisting of TiAlN 11, TiAlON 12, and TiAlN13.
Preferably, all of these layers are deposited by sputter deposition
in the same chamber where the film composition is changed during
the deposition process by varying the gas composition.
[0016] Any conventional form of patterning can be used to pattern
the hard mask 8, but a photoresist mask is preferable. After the
photoresist is patterned then the hard mask 8 is etched (for
example, using chlorine chemistries). After the hard mask 8 is
etched the photoresist is removed with a conventional ash
process.
[0017] Using the patterned hard mask 8 as a template, a plasma
chamber is now used to etch (step 210) the remaining layers of the
ferroelectric capacitor stack 2. Generally multiple etch processes
are used to etch the various layers of the ferroelectric capacitor
stack 2.
[0018] The plasma etch process leaves contamination on the FRAM
capacitor stack 2; therefore, the next step is to remove the etch
damage and/or residues with a post-etch clean. In accordance with
the present invention, the unwanted material is removed from the
semiconductor wafer using a cleaning process comprised of a plasma
etch (step 212) and a wet clean (step 214). In the best mode
application, the plasma etch clean (step 212) is performed in the
same machine as the capacitor stack etch (step 210). As an example,
the machine used for the stack etch and the plasma etch clean may
be the Mattson Asher. In an alternative application, an etcher made
by Applied Materials ("AMT) uses a directional etch process to form
the capacitor stack and then a Mattson Asher uses an isotropic
plasma etch to perform the plasma etch clean.
[0019] In the best mode application, the plasma etch clean (step
212) is performed using CF.sub.4/O.sub.2 as the etchant. More
specifically, a diluted CF.sub.4/O.sub.2 etchant (i.e. 0.5-2%
CF.sub.4) is used under low pressure (.about.1.0 mTorr), moderate
source power (i.e. 1200 W), no bias power, and a low temperature
(.about.60.degree. C.) for a moderate period of time (i.e. 40-80
seconds). However, it is within the scope of this invention to use
any isotropic fluorine-based plasma etch with appropriate
processing conditions to accomplish the stack etch clean.
[0020] After the fluorine-based plasma etch (step 212) a wet clean
process (step 214) is performed in order to remove fluorine and any
remaining unwanted material (such as IrF, PbF, and TiF). In the
best mode application, the wet clean is a two step process
comprising a rinse with deionized water followed by a rinse with an
aqueous acidic solution such as a dilute hydrochloric acid
solution.
[0021] During the wet clean process (step 214) the wafers are
rinsed in a tank using an appropriate process such as a quick dump
rinse. The tank contains deionized water that removes fluorine and
other soluble etch residues. After the deionized water rinse, the
wafers are transferred to another tank that contains a solution of
dilute hydrochloric acid. For example, the solution may be +1:10
HCl:H.sub.2O at 30.degree. C. and the wafers may be held in the
tank for approximately 200 seconds. The dilute HCl process is
followed by an appropriate deionized water rinse process such as a
quick dump rinse. The hydrochloric acid rinse removes remaining
fluorine and other unwanted materials. However, the hydrochloric
acid rinse may also cause a slight additional etching of the
surface of the ferroelectric capacitor stack 2.
[0022] The use of solutions containing other concentrations of
hydrochloric acid is with in the scope of this invention. Moreover,
the use of other wet clean processes is within the scope of this
invention. For example, after the deionized water rinse the wafers
may be further rinsed with an organic solvent (i.e. ethyl alcohol),
sulfuric acid, or phosphoric acid instead of hydrochloric acid.
[0023] Alternatively, the wet clean process may be only a deionized
water rinse. Furthermore, the wet clean process may consist of only
a phosphoric acid rinse, only a hydrochloric acid rinse, only a
sulfuric acid rinse, or only an organic solvent rinse.
[0024] Other modifications to the invention as described above are
within the scope of the claimed invention. As an example, the wet
clean process (step 214) may be performed in an ultrasonic tank. In
addition, the wet clean process may consist of numerous rinses in
solvent, acid or aqueous solutions.
[0025] The clean up plasma etch (step 212) described above may be
performed using any other well known machine generating an
isotropic plasma. In addition, the same chamber of the plasma
etcher may be used for more than one of the above described etch
processes. In addition, instead of CF.sub.4/O.sub.2, any other
fluorine-based etchant, such as C.sub.2F.sub.6 or NF.sub.3, may be
used for the clean up etch.
[0026] Instead of using PZT as the ferroelectric material, other
materials such as SrBi.sub.2Ta.sub.2O.sub.9 may be used.
Furthermore, instead of using this invention to fabricate planar
ferroelectric capacitors, it may be used to fabricate the three
dimensional cup-shaped capacitor. As an example, this invention
could be used to fabricate capacitor under bitline structures.
[0027] Instead of forming the bottom electrode, 5, on the barrier
layer, 9, the bottom electrode, 5, may be formed directly on the
front-end module 3. In addition, instead of SiC, the barrier
material 4 may be silicon nitride, silicon oxide, nitrogen-doped
silicon carbide, or oxygen-doped silicon carbide. Furthermore,
instead of Ir, the bottom electrode may be comprised of other
materials such as Pt, IrO.sub.2 or SrRuO.sub.3. Similarly, instead
of Ir/IrOx, the top electrode may be comprised of other materials
such as Pt, IrO.sub.2, or SrRuO.sub.3.
[0028] This invention can be used in the fabrication of stand-alone
FRAM devices or FRAM devices integrated into a semiconductor chip
that has many device functions other than those described herein.
Moreover, the invention is applicable to semiconductor wafers
having different well and substrate technologies, transistor
configurations, and metal connector materials or configurations.
The invention is also applicable to other semiconductor
technologies such as BiCMOS, bipolar, SOI, strained silicon,
pyroelectric sensors, opto-electronic devices, microelectrical
mechanical system ("MEMS"), or SiGe.
[0029] While various embodiments of the present invention have been
described above, it should be understood that they have been
presented by way of example only, and not limitation. Numerous
changes to the disclosed embodiments can be made in accordance with
the disclosure herein without departing from the spirit or scope of
the invention. Thus, the breadth and scope of the present invention
should not be limited by any of the above described embodiments.
Rather, the scope of the invention should be defined in accordance
with the following claims and their equivalents.
* * * * *