U.S. patent application number 10/849191 was filed with the patent office on 2004-10-28 for semiconductor device including a wiring board with a three-dimensional wiring pattern.
Invention is credited to Amami, Kazuyoshi, Bessho, Yoshihiro, Mitani, Tsutomu, Shiraishi, Tsukasa.
Application Number | 20040212075 10/849191 |
Document ID | / |
Family ID | 26539724 |
Filed Date | 2004-10-28 |
United States Patent
Application |
20040212075 |
Kind Code |
A1 |
Shiraishi, Tsukasa ; et
al. |
October 28, 2004 |
Semiconductor device including a wiring board with a
three-dimensional wiring pattern
Abstract
A semiconductor device is made by mounting semiconductor
elements on both sides of a wiring board having three-dimensional
wiring including inner-via holes. A high operating speed and
smaller size are made possible by employing a laminated structure
of semiconductor elements without using the chip-on-chip
configuration. Semiconductor elements are mounted on both sides of
a wiring board having three-dimensional wiring including inner via
holes so that the semiconductor elements oppose each other via the
wiring board. The electrodes of the semiconductor elements are
connected with each other by the three-dimensional wiring of the
wiring board.
Inventors: |
Shiraishi, Tsukasa; (Osaka,
JP) ; Mitani, Tsutomu; (Hyogo, JP) ; Amami,
Kazuyoshi; (Osaka, JP) ; Bessho, Yoshihiro;
(Osaka, JP) |
Correspondence
Address: |
WENDEROTH, LIND & PONACK, L.L.P.
2033 K STREET N. W.
SUITE 800
WASHINGTON
DC
20006-1021
US
|
Family ID: |
26539724 |
Appl. No.: |
10/849191 |
Filed: |
May 20, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10849191 |
May 20, 2004 |
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10337879 |
Jan 8, 2003 |
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6756663 |
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10337879 |
Jan 8, 2003 |
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09725283 |
Nov 29, 2000 |
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6525414 |
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09725283 |
Nov 29, 2000 |
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09153069 |
Sep 15, 1998 |
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Current U.S.
Class: |
257/700 ;
257/698; 257/784; 257/E21.503; 257/E23.172; 257/E25.011;
438/617 |
Current CPC
Class: |
H01L 2224/32225
20130101; H01L 2224/45144 20130101; H05K 2201/10386 20130101; H01L
2924/01079 20130101; H05K 3/363 20130101; H01L 2224/16225 20130101;
H01L 2924/19106 20130101; H01L 2224/05573 20130101; H05K 2201/056
20130101; H01L 2924/14 20130101; H01L 2224/48091 20130101; H01L
24/45 20130101; H01L 2924/19107 20130101; H01L 25/0652 20130101;
H01L 21/563 20130101; H05K 2203/1572 20130101; H05K 1/189 20130101;
H01L 2924/15174 20130101; H05K 3/3442 20130101; H01L 2924/19041
20130101; H05K 3/3421 20130101; H01L 2224/05571 20130101; H01L
2224/06131 20130101; H05K 2203/049 20130101; H01L 24/48 20130101;
H01L 2224/73204 20130101; H01L 2224/06135 20130101; H05K 1/141
20130101; H01L 2924/15192 20130101; H01L 2224/73203 20130101; H05K
2201/10674 20130101; H05K 1/0284 20130101; H05K 3/368 20130101;
H01L 2924/00014 20130101; H05K 1/147 20130101; H05K 3/328 20130101;
H01L 23/5385 20130101; H01L 2224/73204 20130101; H01L 2224/16225
20130101; H01L 2224/32225 20130101; H01L 2924/00 20130101; H01L
2224/48091 20130101; H01L 2924/00014 20130101; H01L 2224/45144
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
2224/05599 20130101; H01L 2924/14 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
257/700 ;
257/698; 257/784; 438/617 |
International
Class: |
H01L 029/74; H01L
021/44 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 16, 1997 |
JP |
P 09-250304 |
Claims
We claim:
1. A semiconductor device module comprising: a semiconductor device
including: a multi-layer wiring board which comprises insulation
layers and circuit pattern layers laminated alternately and is
provided with a three-dimensional wiring comprising said circuit
pattern layers provided on both sides of the insulation layer and a
plurality of inner via holes penetrating through each of said
insulation layers and electrically connecting; at least a first
semiconductor element mounted on the one side of the multi-layer
wiring board and a second semiconductor element mounted an the
other side of said multi-layer wiring board wherein electrodes of
said semiconductor elements are connected with each other by means
of said three-dimensional wiring; and a mother multi-layer wiring
board having a circuit pattern formed on said surface thereof,
wherein said semiconductor device is mounted on said mother
multi-layer wiring board and said semiconductor device and said
mother multi-layer wiring board are connected by electrical
connection means.
2. The module of the semiconductor device according to claim 1,
wherein said electrical connection means is a projecting electrode
which is interposed between said multi-layer wiring board of said
semiconductor device and said mother multi-layer wiring board by
bonding said back surface of said second semiconductor element onto
said mother multi-layer wiring board thus placing said
semiconductor device on said mother multi-layer wiring board,
thereby to connect said circuit pattern provided on said
multi-layer wiring board and said circuit pattern provided on said
mother multi-layer wiring board.
3. The module of the semiconductor device according to claim 1,
wherein said electrical connection means is an electrically
conductive supporting body which is electrically connected to said
wiring in said multi-layer wiring board of said semiconductor
device and is also used to fasten said semiconductor device onto
said mother multi-layer wiring board, so as to establish electrical
connection between said wiring of said multi-layer wiring board of
said semiconductor device and said circuit pattern provided on said
mother multi-layer wiring board by fastening said semiconductor
device onto said mother multi-layer wiring board via said
electrically conductive supporting body.
Description
[0001] This application is a Divisional application of Ser. No.
10/337,879, now allowed, which is a Divisional application of Ser.
No. 09/725,283, filed Nov. 29, 2000, now U.S. Pat. No. 6,525,414,
which is a Continuation-in-Part application of Ser. No. 09/153,069,
filed Sep. 15, 1998, now abandoned.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device
formed by mounting semiconductor elements on both sides of a wiring
board having three-dimensional wiring which uses inner via
holes.
[0004] 2. Description of the Related Art
[0005] Attempts have been made to develop a semiconductor element
in which a plurality of electronic circuits are incorporated in a
single semiconductor element (for example IC chip, MIC chip and
OEIC chip) in order to make electronic apparatuses having
semiconductor elements used therein more compact. In practice,
however, it is difficult to make a single semiconductor element
having all necessary functions due to limitations related to
semiconductor material, production process, design rule and other
factors, and it is often necessary to use a plurality of
semiconductor elements. In such a case, in order to make the device
smaller in size and run at a higher speed, a chip-on-chip
configuration is employed in which the semiconductor elements are
directly connected with each other by of electrodes as shown in
FIG. 19. In the drawing, numeral 1 denotes a first semiconductor
element, 2 denotes electrodes formed on the first semiconductor
element 1, 3 denotes a second semiconductor element, 4 denotes
electrodes formed on the second semiconductor elements, 10 denotes
junctions made mainly of an electrically conductive metallic
material such as solder, and 11 denotes a cured insulating resin.
When such a chip-on-chip configuration is employed, length of
wiring between the semiconductor elements can be made shorter,
transmission delay of electric signals is reduced, operation speed
of the semiconductor device can be made faster and, because the
semiconductor elements are mounted in laminated configuration, it
is also possible to make the semiconductor device smaller.
[0006] If the first semiconductor element 1 and the second
semiconductor element 3 are electrically connected via the
junctions 10 in such a chip-on-chip configuration as described
above, it is necessary to position the electrodes 2, 4 of the
semiconductor elements so that they oppose each other. For this
reason, general-purpose semiconductor elements cannot be used and
it is required to use semiconductor elements which are designed by
taking the positions of the electrodes 2, 4 into consideration.
Consequently, it is impossible to design the semiconductor elements
separately.
[0007] Also because the positions of the electrodes 2, 4 of the
first and the second semiconductor elements are restricted, it
becomes difficult to reduce the size of the semiconductor device in
some cases, eventually resulting in lower production yield.
SUMMARY OF THE INVENTION
[0008] An object of the present invention is to provide a
semiconductor device which is capable of operating at a higher
speed and is smaller in size by employing general-purpose
semiconductor devices without using the chip-on-chip
configuration.
[0009] Particularly, an object of the present invention is to
provide a semiconductor device capable of operating at a higher
speed and is smaller in size. This is because the wiring length
does not increase even when using semiconductor elements such as a
CPU, wherein the electrodes are formed in an array arrangement.
Although the examples below utilize a multi-layer wiring board, the
objects discussed above can also be achieved by using a wiring
board including a single insulation layer.
[0010] The present inventors have found that it becomes possible to
produce semiconductor devices of smaller size while maintaining a
high operating speed of the semiconductor elements by mounting
general-purpose semiconductor elements so that they oppose each
other via a multi-layer wiring board, in which both sides of the
multi-layer wiring board has a three-dimensional wiring layout
employing inner via holes for connecting electrodes of the
semiconductor elements with each other. Particularly, the
semiconductor device can be produced without making the wiring
longer even when the semiconductor element has an area array type
electrode arrangement by employing the three-dimensional wiring as
described above. Thus, the present invention has been
completed.
[0011] That is, the present invention provides a semiconductor
device comprising a multi-layer wiring board having at least first
and second semiconductor elements mounted on the respective sides
of the multi-layer wiring board. Electrodes of the semiconductor
element are connected with each other by the three-dimensional
wiring. The multi-layer wiring board is made by laminating
insulation layers, which comprise resin-impregnated fiber sheets
and circuit pattern layers alternately, and has three-dimensional
wiring for electrically connecting the circuit pattern layers
provided on both sides of the insulation layer via a plurality of
inner via holes that are provided through each of the insulation
layers.
[0012] The semiconductor device according to the present invention
can be made smaller in size in a configuration similar to
chip-on-chip configuration by employing the general-purpose
semiconductor elements because the semiconductor elements are
mounted face down by flip chip bonding via the multi-layer wiring
board of thin layers. Particularly because the three-dimensional
wiring employing the inner via holes is used in the multi-layer
wiring board, the semiconductor elements mounted on both sides of
the multi-layer wiring board can be connected by the
three-dimensional wiring. Therefore, it is possible to make the
wiring shorter compared to a case where a conventional wiring board
is used in which lead wires are arranged to run over the substrate
surface in two-dimensional wiring.
[0013] Consequently, according to the present invention, it becomes
possible to achieve a high operating speed of the elements by
making the semiconductor device smaller in size so as to prevent a
delay in electric signals from occurring by using a reduced wiring
length. This is similar to the case of employing the conventional
chip-on-chip configuration even when the general-purpose
semiconductor elements are used.
[0014] Also, because the multi-layer wiring board is disposed
between the semiconductor elements, the semiconductor element can
be mounted or removed without causing a stress in the other
semiconductor elements. Thus, it is possible to prevent the
semiconductor elements from being damaged.
[0015] It is preferable that projections of one or more
semiconductor element mounted on either surface of the multi-layer
wiring board in a direction perpendicular to the multi-layer wiring
board overlap each other.
[0016] When the semiconductor elements are mounted on the
respective surfaces of the multi-layer wiring board so that
projections thereof in a direction perpendicular to the multi-layer
wiring board overlap each other, a potential of the multi-layer
wiring board 107 to warp in the perpendicular direction (Z axis
direction) can be reduced even in a case in which the insulating
substrate constituting the multi-layer wiring board is made of a
fiber sheet impregnated with a thermosetting resin which has a low
rigidity and is liable to warp.
[0017] The present invention also provides a semiconductor device
comprising first, second and third semiconductor elements laminated
via the multi-layer wiring board. The multi-layer wiring board is
bonded to cover the back surface of the second semiconductor
element by bending the multi-layer wiring board whereon the first
and the second semiconductor elements are mounted at specified
positions on either side thereof. The third semiconductor element
is mounted by flip chip bonding, so as to oppose the back surface
of the second semiconductor element via the multi-layer wiring
board.
[0018] When the multi-layer wiring board of thin layers is bent and
the semiconductor device and the multi-layer wiring board are
laminated alternately as described above, the semiconductor device
can be made small in size even when a large number of semiconductor
elements are mounted.
[0019] The present invention also provides a module for mounting
semiconductor devices comprising the semiconductor device mounted
on a mother multi-layer wiring board having a circuit pattern
formed on the surface thereof, with the semiconductor device and
the mother multi-layer wiring board being connected by electrical
connection means.
[0020] By mounting the semiconductor elements on the mother
multi-layer wiring board, it becomes possible to form a
high-density module. It is also possible to improve the
productivity of the module by producing the semiconductor devices
in advance and by mounting only qualified semiconductor devices on
the mother multi-layer wiring board after testing the semiconductor
devices for the quality and reliability.
[0021] The electrical connection device is preferably a projecting
electrode which is interposed between the multi-layer wiring board
of the semiconductor device and the mother multi-layer wiring board
by bonding the back surface of the second semiconductor element
onto the mother multi-layer wiring board so as to place the
semiconductor device on the mother multi-layer wiring board.
Therefore, the circuit pattern provided on the multi-layer wiring
board and the circuit pattern provided on the mother multi-layer
wiring board are connected.
[0022] By using the projecting electrode for the electrical
connection means, it becomes possible to form the connection means
which utilizes the empty space between the multi-layer wiring board
of the semiconductor device and the mother multi-layer wiring
board. Thus, the module of the semiconductor device is smaller in
size.
[0023] The electrical connection device preferably establishes an
electrical connection between the circuit pattern provided on the
multi-layer wiring board of the semiconductor device and the
circuit pattern provided on the mother multilayer wiring board.
This connection is established because the back surface of the
second semiconductor element is bonded onto the mother multi-layer
wiring board, and the multi-layer wiring board of the semiconductor
device mounted on the mother multi-layer wiring board is bent.
[0024] By bending the multi-layer wiring board of the semiconductor
device and thereby forming the connection means, it becomes
possible to reduce the number of electrode forming processes and
thus reduce the production cost.
[0025] The electrical connection device is preferably an
electrically conductive supporting body which is electrically
connected to the wiring in the multi-layer wiring board of the
semiconductor device and is also used to fasten the semiconductor
device onto the mother multi-layer wiring board. As a result, an
electrical connection is established between the wiring of the
multi-layer wiring board of the semiconductor device and the
circuit pattern provided on the mother multi-layer wiring board by
fastening the semiconductor device onto the mother multi-layer
wiring board via the electrically conductive supporting body.
[0026] By using the semiconductor device having an electrically
conductive supporting body such as metal which is electrically
connected to the multi-layer wiring board, it becomes possible to
handle the supporting body as if it is a pin of QFP and to mount
the device onto the mother multi-layer wiring board or remove the
device therefrom easily.
[0027] The electrical connection device preferably establishes an
electrical connection between the circuit pattern provided on the
multi-layer wiring board and the circuit pattern provided on the
mother multi-layer wiring board as the semiconductor device is
mounted on the mother multi-layer wiring board. Therefore, the
multi-layer wiring board, which is bonded to cover the back surface
of the second semiconductor element by bending the multi-layer
wiring board whereon at least the first and the second
semiconductor elements are mounted at specified positions on either
side thereof, makes contact with the mother multi-layer wiring
board.
[0028] By using such a connection device as described above, it
becomes possible to make a connection by using the lower region of
the mounting surface of the semiconductor element and thereby make
the module of the semiconductor device smaller in size.
[0029] The present invention also provides a module of the
semiconductor device wherein an alternate lamination of the
semiconductor device and the multi-layer wiring board is mounted on
the mother multi-layer wiring board which has a circuit pattern
formed on the surface thereof. Furthermore, the circuit pattern
provided on the multi-layer wiring board of the semiconductor
device and the circuit pattern provided on the mother multi-layer
wiring board are electrically connected to each other.
[0030] By using such a module as described above, the semiconductor
device can be mounted on the mother multi-layer wiring board with a
high density.
[0031] The present invention also provides a semiconductor device
wherein the electrodes of at least one of the first and the second
semiconductor elements are formed in an area array arrangement.
[0032] In the multi-layer wiring board according to the present
invention, use of the three-dimensional wiring which employs the
inner via holes makes it possible to connect between the
semiconductor elements mounted on both sides of the multi-layer
wiring board in three-dimensional wiring. Consequently, the wiring
length can be made shorter compared to a case such as the
conventional wiring board in which lead wires are arranged so as to
run over the surface of the wiring board in two-dimensional wiring.
This configuration is effective for mounting semiconductor elements
which have electrodes near the center as well as in the peripheral
portions thereof, such as a semiconductor device having electrodes
arranged in an area array arrangement.
[0033] The present invention also provides a semiconductor device
comprising a first semiconductor element having the electrodes
arranged in area array arrangement and a second semiconductor
element having the electrodes arranged in peripheral arrangement.
Both semiconductor elements are mounted face down on the respective
surfaces of the multi-layer wiring board by flip chip bonding,
wherein the electrodes of both semiconductor elements are connected
to each other by the three-dimensional wiring.
[0034] As the semiconductor elements are mounted face down by flip
chip bonding via the thin layer multi-layer wiring board in the
semiconductor device of the present invention, it becomes possible
to mount the semiconductor elements by flip chip bonding and make
the semiconductor device smaller in size.
[0035] In the multi-layer wiring board according to the present
invention, use of the three-dimensional wiring comprising inner via
holes makes it possible to connect between the semiconductor
elements mounted on both sides of the multi-layer wiring board in
three-dimensional vertical wiring. Consequently, the wiring can be
made shorter compared to a case such as the conventional wiring
board in which lead wires are arranged to run over the surface of
the wiring board in two-dimensional wiring.
[0036] Therefore, the present invention makes it possible to make
the semiconductor device smaller in size even when mounting the
semiconductor elements having electrodes arranged in area array
arrangement. Reduction of the wiring length also makes it possible
to increase the operating speed by preventing delay in electrical
signals, and to reduce the power consumption by decreasing the
resistance of the wiring.
[0037] The present invention also provides a semiconductor device
wherein the semiconductor element having the electrodes arranged in
an area array arrangement is mounted face down on one surface of
the multi-layer wiring board by flip chip bonding and electronic
components are mounted on the other surface of the multi-layer
wiring board. In this arrangement, the electrodes of the
semiconductor element and the electrodes of the electronic
components are connected with each other by the three-dimensional
wiring.
[0038] Because the three-dimensional wiring by inner via holes is
employed in the multi-layer wiring board of the semiconductor
device according to the present invention, the semiconductor
element and the electronic components, such as a bypass capacitor
mounted on either side of the multi-layer wiring board, can be
connected to each other by three-dimensional wiring. In addition,
the wiring length can be made shorter compared to a case such as
the conventional wiring board in which lead wires are arranged to
run over the surface of the wiring board in two-dimensional
wiring.
[0039] Therefore, noise can be effectively removed during
high-speed operation. In particular, when connecting the central
electrode of the semiconductor element having electrodes arranged
in an area array arrangement and the electronic component, the
wiring length can be made far shorter than in the conventional
wiring board.
[0040] The electronic component is preferably a bypass capacitor.
When a bypass capacitor is used as the electronic component, it
becomes possible to effectively remove noise due to the bypass
capacitor by reducing the wiring length and thereby reducing the
noise in the wiring.
[0041] As will be clear from the above description, the
semiconductor device according to the present invention has
semiconductor elements mounted so as to oppose each other via the
multi-layer wiring board with the electrodes of the semiconductor
elements being connected to each other by means of the
three-dimensional wiring of the multi-layer wiring board.
Therefore, the elements can be connected with each other regardless
of the arrangement of the electrodes of the semiconductor elements,
thus making it possible to connect the general-purpose
semiconductor elements without modification by a method similar to
the chip-on-chip connection and to provide a semiconductor device
of smaller size and higher operating speed.
[0042] According to the present invention, since a multi-layer
wiring board is used instead of the conventional printed circuit
board and because connection between the semiconductor elements is
made by using the three-dimensional wiring based on the inner via
holes which makes it easier to run the lead wires, wiring length
can be reduced. Thus, delays are prevented from occurring in the
circuit response due to the wiring length, so that the operating
speed of the semiconductor device can be increased.
[0043] Because the semiconductor elements are not connected
directly with each other, it becomes possible to remove or mount
any of the semiconductor elements without causing damage to the
other semiconductor elements. Also, because the semiconductor
device is mounted on the mother multi-layer wiring board,
high-density packaging is made possible, thereby contributing to
the size reduction of electronic apparatuses.
[0044] Further in case the semiconductor element having electrodes
of area array arrangement is mounted face down by flip chip
bonding, connecting by the multi-layer wiring board 105 having the
inner via holes 109 therein makes it possible to reduce the wiring
length, increase the operating speed of the semiconductor device,
and reduce the power consumption.
[0045] In the case of the semiconductor element having electrodes
of area array arrangement, in particular, wiring length of the
electrode located near the center of the semiconductor element can
be greatly reduced compared to a semiconductor device which employs
the conventional wiring board.
[0046] Also by connecting the bypass capacitors and the
semiconductor elements by the three-dimensional wiring comprising
the inner via holes, it becomes possible to reduce the wiring
length and reduce the noise generated in the semiconductor
device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0047] FIG. 1A is a perspective view of the semiconductor device
according to a first embodiment of the present invention, and FIG.
1B is a cross sectional view taken along lines I-I' of FIG. 1A.
[0048] FIGS. 2A, 2B, 2E are view showing the arrangement of the
bumps formed on the semiconductor element according to the first
embodiment of the present invention, and FIGS. 2C, 2D are views
showing the circuit pattern of the multi-layer wiring board
according to the first embodiment of the present invention.
[0049] FIG. 3 is a top view of the semiconductor device according
to the first embodiment of the present invention.
[0050] FIG. 4 is a cross sectional view of the module of the
semiconductor device according to a second embodiment of the
present invention.
[0051] FIG. 5 is a cross sectional view of the module of the
semiconductor device according to a third embodiment of the present
invention.
[0052] FIG. 6 is a cross sectional view of the module of the
semiconductor device according to a fourth embodiment of the
present invention.
[0053] FIG. 7 is a cross sectional view of the module of the
semiconductor device according to a fifth embodiment of the present
invention.
[0054] FIG. 8 is a cross sectional view of the module of the
semiconductor device according to a sixth embodiment of the present
invention.
[0055] FIG. 9 is a cross sectional view of the semiconductor device
according to a seventh embodiment of the present invention.
[0056] FIG. 10 is a cross sectional view of the module of the
semiconductor device according to an eighth embodiment of the
present invention.
[0057] FIG. 11 is a perspective view of the semiconductor device
according to a ninth embodiment of the present invention.
[0058] FIG. 12 is a cross sectional view taken along lines II-II'
of FIG. 11.
[0059] FIGS. 13A, 13B are views showing the arrangement of the
electrodes of the semiconductor element.
[0060] FIG. 14A is a view showing the arrangement of the electrodes
of the semiconductor element having the area array electrode
arrangement, and FIG. 14B is a view showing the circuit pattern of
the multi-layer wiring board whereon the semiconductor element
having the area array electrode arrangement is mounted.
[0061] FIG. 15A shows the circuit pattern of the multi-layer wiring
board whereon the semiconductor element having a peripheral
electrode arrangement is mounted, and FIG. 15B shows the
arrangement of the electrodes of the semiconductor element having
the peripheral electrode arrangement.
[0062] FIG. 16 is a cross sectional view of the semiconductor
device according to a tenth embodiment of the present
invention.
[0063] FIG. 17A shows the arrangement of the electrodes of the
semiconductor element having an area array electrode arrangement,
and FIG. 17B shows the circuit pattern of the multi-layer wiring
board whereon the semiconductor element having the area array
electrode arrangement is mounted.
[0064] FIG. 18A shows the circuit pattern of the multi-layer wiring
board whereon the bypass capacitor is mounted, and FIG. 18B shows
the lead arrangement of the bypass capacitor.
[0065] FIG. 19 is a cross sectional view of the semiconductor
device of the chip-on-chip connection of the prior art.
[0066] FIG. 20 is a cross sectional view of the semiconductor
device according to a variation of the seventh embodiment of the
present invention, in which a wiring board with a single insulation
layer is utilized.
DETAILED DESCRIPTION OF THE INVENTION
EMBODIMENT 1
[0067] FIGS. 1A, 1B show a semiconductor device according to the
first embodiment of the present invention. This semiconductor
device has two semiconductor elements on one side and one
semiconductor element on the other side.
[0068] FIG. 1A is a perspective view of the semiconductor device
and FIG. 1B is a cross sectional view taken along lines I-I' of the
semiconductor device shown in FIG. 1A. In the drawing, numeral 101
denotes a first semiconductor element, 102 denotes an electrode
formed on an element forming surface of the semiconductor element
101, 103 denotes a second semiconductor element, 105 denotes a
third semiconductor element, 104 and 106 denote electrodes formed
on the respective semiconductor elements, 107 denotes a multi-layer
wiring board, 108 denotes a circuit pattern formed on the surface
layer of the multi-layer wiring board, and 109 denotes inner via
holes. Numeral 110 denotes junctions which provide electrical
connection between the semiconductor elements 101, 103, 105 and the
circuit pattern formed on the surface layer of the multi-layer
wiring board 107, and 111 denotes an electrically insulating
thermosetting resin. In the following embodiments, it is also
possible to utilize a wiring board 207 which has only a single
insulation layer, as shown in FIG. 20.
[0069] In the process of producing the semiconductor device shown
in FIG. 1, first the three semiconductor elements 101, 103, 105 are
prepared and ball bumps made of Au are formed on the surfaces of
the electrodes 102, 104, 106, and then a required amount of an
electrically conductive adhesive is applied onto the tips of the
ball bumps. The electrically conductive adhesive is a mixture of a
powder of electrically conductive metal such as Ag, Cu or Ni and a
resin.
[0070] The semiconductor elements 101, 103 having the ball bumps
made of Au or the like formed thereon with the electrically
conductive adhesive applied thereto are mounted on the front
surface of the multi-layer wiring board 107, and the semiconductor
element 105 is mounted on the back surface of the multi-layer
wiring board 107. Each of the elements is mounted face down by flip
chip bonding so that the semiconductor elements on both sides
oppose each other via the multi-layer wiring board 107, with the
adhesive cured by a heat treatment.
[0071] FIGS. 2A, 2B, 2E show the layout of bumps provided on the
back surfaces of the first semiconductor element 101, the second
semiconductor element 103 and the third semiconductor element 105.
FIGS. 2C, 2D show the circuit patterns formed on the top surface
and the back surface of the multi-layer wiring board 107,
respectively, whereon the semiconductor elements are mounted.
[0072] Bumps a1, a2, a3 and so on formed on the back surface of the
first semiconductor element 101 and bumps b1, b2, b3 and so on
formed on the back surface of the second semiconductor element 103
are connected to the electrodes x1, x2, x3 and so on. The
electrodes x11, x12, x13 and so on are formed on the top surface of
the multi-layer wiring board 107, respectively.
[0073] Bumps c1, c2, c3 and so on formed on the back surface of the
third semiconductor element 105 are connected to the electrodes y1,
y2, y3 and so on formed on the bottom surface of the multi-layer
wiring board 107.
[0074] The three-dimensional wiring of the multi-layer wiring board
107 establishes the electrical connection between the electrodes x1
and y1, between x2 and y2, between x3 and y3 and so on which are
formed on the top and bottom surfaces of the multi-layer wiring
board 107, respectively.
[0075] Consequently, because the first and the second semiconductor
elements 101, 102 are mounted on one side, and the third
semiconductor element 105 is mounted on the other side of the
multi-layer wiring board 107, the electrodes of the semiconductor
elements are connected with each other by the three-dimensional
wiring of the multi-layer wiring board 107. Thus, a laminated
construction similar to the conventional chip-on-chip configuration
is achieved.
[0076] After the electrically conductive adhesive is cured si as to
fasten the semiconductor elements 101, 103, 105 onto the
multi-layer wiring board 107, the semiconductor elements are
subjected to electrical tests to make sure of normal functions
thereof.
[0077] Then after filling the gap between the semiconductor
elements 101, 103, 105 and the multi-layer wiring board 107 with an
insulating thermosetting resin 111, the insulating thermosetting
resin 111 is completely cured by a heat treatment. As a result, the
mechanical strength and quality of connection is increased.
[0078] In case any of the semiconductor elements is found to be
defective in the electrical test, only the defective semiconductor
element is removed and replaced with a new semiconductor element.
In this regard, bonding strength of the semiconductor elements is
controlled to a minimum necessary level thereby to make it easy to
remove the semiconductor element. Proper bonding strength per one
bump for this purpose is about 3.times.10.sup.6 to
30.times.10.sup.6 N/m.sup.2.
[0079] The multi-layer wiring board 107 comprises insulating
substrates made of resin-impregnated fiber sheets described in
Japanese Patent Kokai Publication No. 6-268345 and circuit patterns
laminated alternately. The three-dimensional wiring is formed so as
to connect the electrically conductive inner via holes formed
through the insulating substrates and the circuit patterns.
[0080] The insulating substrate of the multi-layer wiring board 107
preferably consists of a fiber sheet made of glass fiber, aramid
fiber or the like impregnated with a thermosetting resin. This is
for the purpose of reducing the stress generated in the
semiconductor elements to be mounted thereon and in the junctions
by taking advantage of the Young's modulus of the resin-impregnated
fiber sheet being lower than that of a wiring board which uses an
inorganic material such as ceramics for the insulating
substrate.
[0081] The material such as glass fiber and aramid fiber included
in the substrate decreases the value of the thermal expansion
coefficient, and also contributes to the reduction of the stress
generated in the semiconductor elements to be mounted thereon and
in the junctions.
[0082] Use of the fiber sheet such as glass fiber and aramid fiber
impregnated with the thermosetting resin for the insulating
substrate of the multi-layer wiring board 107 reduces the stress
generated in the semiconductor elements and in the junctions,
thereby making it possible to produce high-quality semiconductor
devices.
[0083] FIG. 3 is a plan view of the semiconductor device according
to this embodiment viewed from the side of the first semiconductor
element 101, wherein reference numerals identical to those of FIG.
1 denote the identical or corresponding portions.
[0084] As will be seen from FIG. 3, the projection of the
semiconductor elements 101, 103 in the direction (hereinafter
called Z axis direction) perpendicular to the wiring forming
surface of the multi-layer wiring board 107 overlaps at least
partially with the projection of the semiconductor element 105,
which is mounted on the back surface, in the direction
perpendicular to the wiring forming surface of the multi-layer
wiring board 107. By arranging the semiconductor elements 101, 103,
105 in this configuration, the semiconductor device of the present
invention becomes substantially symmetrical in the Z-axis direction
with respect to the multi-layer wiring board 107.
[0085] As the semiconductor elements are disposed substantially
symmetrically in the Z axis direction with respect to the
multi-layer wiring board 107, the possibility that the insulating
substrate of the multi-layer wiring board 107 will warp in the Z
axis direction can be reduced even when the insulating substrate is
made of the fiber sheet impregnated with the thermosetting resin
which has a low rigidity and is liable to warp.
[0086] Because the semiconductor device of the present invention
can be made with less warping, it is easier to mount the
semiconductor device on the other wiring board and reduce the
residual stress after mounting.
[0087] According to this embodiment, as described above, electrical
connection between the first and the second semiconductor elements
101, 103 and the third semiconductor element 105 is made by means
of the multi-layer wiring board 107. Therefore, it becomes possible
to connect the elements with each other regardless of the positions
of the electrodes formed on the semiconductor elements.
Consequently, a connection similar to that of chip-on-chip mounting
can be made by using the general-purpose semiconductor elements
without modification.
[0088] When compared to a case of connecting semiconductor elements
by using a wiring board of the conventional in which an inter-layer
connection is made by forming the conventional through holes, use
of the multi-layer wiring board 107 makes it possible to form
three-dimensional wiring by inner via holes, increase the wiring
density, and increase the degree of freedom in the design of inter
layer connection. As a result, it becomes easier to run the lead
wires. Thus, because the use of the multi-layer wiring board 107 in
wiring between similar semiconductor elements makes it possible to
reduce the number of insulating layers to be laminated and to
reduce the wiring length, the semiconductor device can be made
smaller in size. It is advantageous to make the semiconductor
device of shorter wiring length and higher operating speed.
[0089] Also, because the semiconductor elements are not directly
connected with each other, any of the semiconductor elements can be
mounted or removed without causing damage to the other
semiconductor elements (for example damage due to stress generated
in the leads of the semiconductor elements).
[0090] Further, because the semiconductor elements 101, 103, 105
are arranged in a substantially symmetrical configuration in the Z
axis direction with respect to the multi-layer wiring board 107,
the possibility that the multi-layer wiring board 107 will warp in
the Z axis direction can be reduced even when the insulating
substrate of the multi-layer wiring board 107 is made of the fiber
sheet impregnated with the thermosetting resin which has a low
rigidity and is liable to warp.
[0091] Although the junctions 110 of the semiconductor elements are
made from the Au ball bumps formed on the electrodes of the
semiconductor elements and the electrically conductive adhesive in
this embodiment, the bumps may also be formed by soldering or a
process other than wire bonding. The bumps may be formed on the
multi-layer wiring board 107, and the electrically conductive
adhesive may also be replaced with cream solder.
[0092] The similar effect may be obtained by using another flip tip
mounting technique, such as a solder bump method employed by
Motorola Corp., or a method using an anisotropically conductive
film (ACF). If an anisotropically conductive film is used,
replacement of a defective semiconductor element is done by locally
heating the anisotropically conductive film.
EMBODIMENT 2
[0093] FIG. 4 is a cross sectional view of a module of the
semiconductor device according to a second embodiment of the
present invention. In the drawing, reference numerals identical to
those of FIG. 1 denote the identical or corresponding portions.
Numeral 112 denotes a mother wiring board whereon the semiconductor
device is to be mounted, 113 denotes a circuit pattern formed in
the surface layer of the mother wiring board, 114 denotes an Au
wire for electrically connecting the multi-layer wiring board and
the mother multilayer wiring board.
[0094] The module according to this embodiment is produced by such
processes as shown in FIG. 4, the semiconductor device comprising
the multi-layer wiring board 107, whereon the semiconductor
elements which have passed electrical tests are mounted, is
fastened on the mother multi-layer wiring board 112 at a specified
position by bonding the back surface of the third semiconductor
element 105 onto the mother multi-layer wiring board 112 by means
of an adhesive or the like. Then the circuit pattern 108 on the
front surface of the multi-layer wiring board 107 and the circuit
pattern 113 on the front surface of the mother multi-layer wiring
board 112 are connected with each other by the Au wire 114.
[0095] According to this embodiment, because the high-quality
semiconductor device with less warp in the Z axis direction is
mounted on the mother multi-layer wiring board, a semiconductor
device module of extremely high quality and high productivity can
be produced.
[0096] Also, because the semiconductor elements 101, 103, 105
mounted on the semiconductor device are made in such a
configuration as to be laminated in the Z axis direction, the
surface area of the mother wiring board can be made smaller and the
present invention can be applied to electronic apparatuses which
are required to be smaller in size.
[0097] Although the Au wire 114 is used for the electrical
connection means between the multi-layer wiring board 107 and the
mother multi-layer wiring board 112 in FIG. 4, TAB (tape--automated
bonding) or the like may also be used instead of the Au wire
114.
[0098] Particularly in this embodiment, because the multi-layer
wiring board 107 and the mother wiring board 112 are made of the
same material, physical constants such as thermal expansion
coefficients of the two wiring boards are the same. Consequently,
the stress generated in the third semiconductor element 105 which
is interposed between both wiring boards is decreased and the
quality of the module can be improved.
EMBODIMENT 3
[0099] FIG. 5 is a cross sectional view of a module of the
semiconductor device according to the third embodiment of the
present invention. In the drawing, reference numerals identical to
those of FIG. 4 denote the identical or corresponding portions.
[0100] As can be seen in FIG. 5, a second semiconductor element 301
is mounted on the second side of the first wiring board 107, and
the second semiconductor element 301 can be larger than the first
semiconductor element 101, which is mounted on the first side of
the first wiring board 107. In addition, the semiconductor device
can include a third semiconductor element 302, which is also
mounted on the first side of the first wiring board and is
electrically connected to both the first and second semiconductor
elements.
[0101] In the module according to this embodiment, the
semiconductor device (including the first wiring board, the first
semiconductor element, and the second semiconductor element) is
mounted on the mother (second) multi-layer wiring board 112 by a
method similar to that of the second embodiment.
[0102] The first multi-layer wiring board 107 which forms part of
the semiconductor device has a thickness of about 200 mm, for
example, and has a certain level of elasticity. Thus, it becomes
possible to connect the first multi-layer wiring board 107 directly
to the mother (second) wiring board by bending the multi-layer
wiring board 107. For example, both the first end and second end of
the first multi-layer wiring board are bent toward the second
wiring board.
[0103] Therefore, the multi-layer wiring board 107 of the
semiconductor device mounted on the mother multi-layer wiring board
112 is bent and the circuit pattern provided on the multi-layer
wiring board 107 and the circuit pattern provided on the mother
multi-layer wiring board 112 are directly connected to each other.
Consequently, the electrical connection between both wiring boards
is established, and the module for the semiconductor device is
produced.
[0104] This process reduces the amount of connection material such
as Au wire to be used and reduces the number of processes for
producing the module. Thus, it is possible to provide the module
for the semiconductor device at a low cost with high
productivity.
EMBODIMENT 4
[0105] FIG. 6 is a cross sectional view of a module of the
semiconductor device according to a fourth embodiment of the
present invention. In the drawing, reference numerals identical to
those of FIG. 4 denote the identical or corresponding portions.
Numeral 115 denotes an electrical junction such as bump
electrode.
[0106] In the module according to this embodiment, the
semiconductor device is mounted on the mother multi-layer wiring
board 112 by a method similar to that of the second embodiment.
[0107] Protruding electrodes 115 as shown in FIG. 6 are used as the
means for connecting the multi-layer wiring board 107 of the
semiconductor device and the mother multi-layer wiring board 112.
The protruding electrode 115 has a configuration similar to that of
the junction 110 used in connecting the semiconductor element 101
or the like and the multi-layer wiring board 107. That is, after
forming the ball bumps made of Au on the circuit pattern of the
mother multi-layer wiring board 112, a required amount of
electrically conductive adhesive is applied to the tips of the
bumps, and the circuit pattern formed on the multi-layer wiring
board 107 is placed thereon so as to electrically connect the two
wiring boards. If some of the electrodes 102, 104 of the first
semiconductor element 101 or the second semiconductor element 103
are exposed without being covered by the multi-layer wiring board
107, it may be connected with the junction layer 115 of the
protruding electrode.
[0108] According to this embodiment, the two wiring boards can be
connected to each other by utilizing the narrow space between the
semiconductor device and the mother multi-layer wiring board 112.
Therefore, the semiconductor devices can be mounted on the mother
multi-layer wiring board 112 in a high density, thereby
contributing to the size reduction of electronic apparatuses.
EMBODIMENT 5
[0109] FIG. 7 is a cross sectional view of a module of the
semiconductor device according to a fifth embodiment of the present
invention. In the drawing, reference numerals identical to those of
FIG. 4 denote identical or corresponding portions. Numeral 116
denotes an electrically conductive supporting body.
[0110] In the module of the semiconductor device according to this
embodiment, the semiconductor device is mounted on the mother
multi-layer wiring board 112 by using the electrically conductive
body 116 such as a metal frame which is electrically connected to
the multi-layer wiring board 107 of the semiconductor device.
[0111] Electrical connection and mechanical fastening of the
electrically conductive body 116 are made by holding the circuit
pattern 108 of the multi-layer wiring board 107 at an edge of the
multi-layer wiring board 107 and soldering or the like.
[0112] The semiconductor device is connected with the mother
multi-layer wiring board 112 via the electrically conductive body
116.
[0113] According to this embodiment, it becomes possible to handle
the semiconductor device equipped with the electrically conductive
body 116 as if it is a QFP (quad flat module), and to mount the
semiconductor device on the mother multi-layer wiring board 112.
Thus, it becomes easier to inspect and mount the semiconductor
device and to replace the semiconductor device in case of a
failure.
EMBODIMENT 6
[0114] FIG. 8 is a cross sectional view of a module of the
semiconductor device according to a sixth embodiment of the present
invention. In the drawing, reference numerals identical to those of
FIG. 4 denote the identical or corresponding portions.
[0115] In this embodiment, as shown in FIG. 8, the first
semiconductor element 101 and the second semiconductor element 103
are mounted so as to oppose each other via the multi-layer-wiring
board 107. In other words, the front surface of first semiconductor
element 101 faces the first side of wiring board 107, and the front
surface of second semiconductor element 103 faces the second side
of wiring board 107. As shown in FIG. 8, at least a portion of the
front surface of the second semiconductor element 103 opposes
(faces) at least a portion of the front surface of the first
semiconductor element 101 via wiring board 107. The multi-layer
wiring board 107 is also bent to cover the back surface of the
second semiconductor element 103 and is bonded onto the back
surface by an adhesive or the like.
[0116] The semiconductor device is mounted on the mother
multi-layer wiring board 112 so that the circuit pattern formed on
the multi-layer wiring board 107 is electrically connected to the
circuit pattern formed on the mother multilayer wiring board
112.
[0117] Since this configuration makes it unnecessary to provide
particular means for electrically connecting the semiconductor
device and the mother multi-layer wiring board 112, the amount of
electrode material and the number of producing processes can be
reduced. In addition, since the portion under the semiconductor
device becomes the electrical connection means, the surface area of
the mother multi-layer wiring board 112 can be effectively utilized
thereby making it possible to mount the semiconductor devices in a
high density and contribute to the size reduction of electronic
apparatuses.
EMBODIMENT 7
[0118] FIG. 9 is a cross sectional view of a semiconductor device
according to a seventh embodiment of the present invention. In the
drawing, reference numerals identical to those of FIG. 4 denote the
identical or corresponding portions.
[0119] According to this embodiment, as shown in FIG. 9, the first
semiconductor element 101 and the second semiconductor element 103
are mounted so as to oppose each other via the multi-layer wiring
board 107 by flip chip bonding. The multi-layer wiring board 107 is
bent to cover the back surface of the second semiconductor element
103 and is bonded onto the back surface of the second semiconductor
element 103 by means of an adhesive or the like. Then the third
semiconductor element 105 is mounted by flip chip bonding on the
multi-layer wiring board 107 which is bonded to the back surface of
the second semiconductor element 103 so that the third
semiconductor element 105 and the second semiconductor element 103
oppose each other via the multi-layer wiring board 107.
[0120] In the semiconductor device of this embodiment, the three
semiconductor elements 101, 103, 105 are laminated by bending the
multi-layer wiring board 107. Therefore, packaging space can be
effectively utilized, thus making it possible to minimize the size
of electronic apparatuses.
[0121] Although three semiconductor elements are laminated in this
embodiment, the semiconductor elements can be mounted in larger
number of levels by bending the multi-layer wiring board 107
furthermore.
[0122] Furthermore, as shown in FIG. 20, the wiring board 207 may
also have only a single insulation layer with circuit patterns
formed on each side of the single insulation layer. Inner via holes
109 which extend through the single insulation layer electrically
connect the circuit patterns formed on each side. In this
embodiment, the wiring board 207 is arranged so that the
semiconductor elements 101, 103, and 105 can be arranged as
described above with reference to FIG. 9. Thus, packaging space can
be effectively utilized so that the size of an electronic apparatus
can be minimized.
EMBODIMENT 8
[0123] FIG. 10 is a cross sectional view of a module of the
semiconductor device according to an eighth embodiment of the
present invention. In the drawing, reference numerals identical to
those of FIG. 4 denote the identical or corresponding portions.
[0124] According to this embodiment, as shown in FIG. 10, the
semiconductor device mounted by lamination using the multi-layer
wiring board 107 which is bent over the first, second and third
semiconductor elements according to the seventh embodiment is
mounted on the mother multi-layer wiring board 112. The multi-layer
wiring board 107 and the mother multi-layer wiring board 112 are
then electrically connected with each other, thereby making the
module.
[0125] Electrical connection between the multi-layer wiring board
107 and the mother multi-layer wiring board 112 is further made by
directly connecting the circuit pattern formed on the multi-layer
wiring board 107 bonded to cover the back surface of the third
semiconductor element and the circuit pattern formed on the mother
multi-layer wiring board 112.
[0126] According to this embodiment, since an electrical connection
is made by using the portion under the semiconductor device, the
packaging area of the mother multi-layer wiring board 112 can be
effectively utilized. As a result, it is possible to further
improve the packaging efficiency because the semiconductor devices
can be mounted in multiple layers. Thus, it becomes possible to
provide a module for semiconductor devices which is very
advantageous for the size reduction of electronic apparatuses.
EMBODIMENT 9
[0127] FIG. 11 is a perspective view of a semiconductor device
according to a ninth embodiment of the present invention, wherein a
semiconductor element 201 having electrodes arranged in area array
arrangement is mounted on the top surface of a multi-layer wiring
board 105. A semiconductor element 203 (not shown) having
electrodes arranged in peripheral arrangement is then mounted on
the back surface.
[0128] FIG. 12 is a cross sectional view taken along lines II-II'
in FIG. 11. In the drawing, numeral 201 denotes a first
semiconductor element, 202 denotes electrodes arranged in area
array arrangement on the element forming surface of the first
semiconductor element 201, 203 denotes a second semiconductor
element and 204 denotes electrodes arranged in peripheral
arrangement on the element forming surface of the second
semiconductor element 203. Numeral 107 denotes the multi-layer
wiring board, 108 denotes a circuit pattern formed on the surface
of the multi-layer wiring board 107, and 109 denotes inner via
holes. Numeral 110 denotes junctions for electrically connecting
the semiconductor elements 201, 203 and the circuit pattern 108
provided on the surface of the multi-layer wiring board 107, and
111 denotes an insulating thermosetting resin.
[0129] According to this embodiment, as shown in FIGS. 13A, 13B,
the semiconductor element having the electrodes arranged in
peripheral arrangement and the semiconductor element having the
electrodes arranged in area array arrangement are mounted on both
sides of the multi-layer wiring board 107.
[0130] The area array arrangement of electrodes has recently been
increasingly employed in high-performance integrated circuits such
as a CPU in order to increase the operating speed of the
semiconductor elements and decrease the power consumption.
[0131] However, if semiconductor elements having the electrodes
arranged in the area array arrangement as described above are
mounted on a conventional multi-layer wiring board, a lead wire
connecting a central electrode among the electrodes arranged in the
area array arrangement becomes too long. Thus, the effort to
increase the operating speed of the semiconductor elements is
hindered.
[0132] According to this embodiment, therefore, the electrodes
arranged in the area array arrangement are connected to the other
semiconductor elements via the inner via holes 109 which are formed
in the multi-layer wiring board 107, thereby reducing the wiring
length.
[0133] In the process of producing the semiconductor device shown
in FIG. 11, the semiconductor element 201 having the electrodes
arranged in the area array arrangement and the semiconductor
element 203 having the electrodes arranged in the peripheral
arrangement are prepared and, after forming the Au ball bumps on
the electrodes 201, 204 by using a wire bonding apparatus, a
required amount of electrically conductive adhesive is applied to
the tips of the ball bumps. The electrically conductive adhesive is
made of a mixture of electrically conductive metal powder such as
Ag, Cu or Ni and a resin.
[0134] The semiconductor element 201 with the ball bumps made of Au
or the like and covered with the electrically conductive adhesive
is mounted on the top surface of the multi-layer wiring board 107,
and the semiconductor element 203 is mounted on the back surface of
the multi-layer wiring board 105. Both semiconductor elements are
mounted face down by flip chip bonding so as to oppose each other
via the multi-layer wiring board 107. The two semiconductor
elements are fastened onto the respective sides of the multi-layer
wiring board 107 as the adhesive is cured by a heat treatment.
[0135] FIG. 14A shows the arrangement of the electrodes of the
semiconductor element 201 having the electrodes arranged in area
array arrangement, and FIG. 14B shows the circuit pattern formed on
the multi-layer wiring board 107 whereon the semiconductor element
201 is mounted. Numeral 205 denotes the Au ball bumps.
[0136] As shown in FIG. 14B, use of the multi-layer wiring board
107 having the inner via holes 109 makes it possible to reduce the
wiring length by providing the inner via holes 109 just below the
circuit pattern located at the center of the circuit pattern of the
area array arrangement or in the vicinity thereof. Thus, the
three-dimensional wiring is also provides this circuit pattern.
[0137] FIG. 15A shows the circuit pattern 108 provided on the back
surface of the multi-layer wiring board 107 whereon the
semiconductor element 203 is mounted, and FIG. 15B shows the
configuration of the electrodes of the semiconductor element 203
having the peripheral electrode arrangement.
[0138] The semiconductor element having the electrodes arranged in
the area array arrangement is also checked to make sure of normal
functions in electrical tests after the semiconductor elements 201,
203 are fastened onto the multi-layer wiring board 107 by curing
the electrically conductive adhesive, similarly to the
semiconductor element having the electrodes of peripheral
arrangement.
[0139] Then after filling the gap between the semiconductor
elements 201, 203 and the multi-layer wiring board with the
thermosetting resin, the thermosetting resin is completely cured by
a heat treatment, thereby increasing the mechanical strength and
the junction strength.
[0140] If any of the semiconductor elements is found to be
defective during the electrical test, only the defective
semiconductor element is removed and replaced with a new
semiconductor element. In this regard, bonding strength of the
electrically conductive adhesive is controlled to a minimum
necessary level thereby to make it easy to remove the semiconductor
element. Proper bonding strength per one bump for this purpose is
about 3.times.10.sup.6 to 30.times.10.sup.6 N/m.sup.2.
[0141] As described above, this embodiment has the effects of, in
addition to the effects described in conjunction with the first
embodiment, reducing the wiring length, increasing the operating
speed of the semiconductor device, and decreasing the power
consumption. These effects are created because the semiconductor
element 201 having the electrodes of the area array arrangement and
the semiconductor element 203 having the electrodes of the
peripheral arrangement mounted on both sides by flip chip bonding
are electrically connected via the multi-layer wiring board 105
having the inner via holes 109 formed therein.
[0142] Particularly for the semiconductor element having the
electrodes arranged in the area array arrangement, wiring length of
the electrodes located near the center of the semiconductor element
can be greatly reduced compared to a semiconductor device which
employs the conventional wiring board.
[0143] Another flip chip mounting technique described in
conjunction with the first embodiment may also be applied.
[0144] It is also possible to mount the semiconductor elements
having the electrodes of area array arrangement on both sides of
the multi-layer wiring board 107.
EMBODIMENT 10
[0145] FIG. 16 is a cross sectional view of a module of the
semiconductor device according to a tenth embodiment of the present
invention. In the drawing, reference numerals identical to those of
FIG. 1 denote the identical or corresponding portions. Numeral 130
denotes a bypass capacitor and 131 denotes leads of the bypass
capacitor.
[0146] According to this embodiment, the semiconductor element 201
having the electrodes of the area array arrangement is mounted on
the top surface of the multi-layer wiring board 107 and one or more
bypass capacitors 131 is mounted on the back surface of the
multi-layer wiring board 107.
[0147] FIG. 17A shows the configuration of the electrodes of the
semiconductor element 201 having the electrodes of the area array
arrangement, and FIG. 17B shows the circuit pattern formed on the
multi-layer wiring board 107 whereon the semiconductor element 201
is mounted. Numeral 205 denotes the Au ball bumps.
[0148] FIG. 18A shows the circuit pattern 108 formed on the back
surface of the multi-layer wiring board 107 whereon six bypass
capacitors 131 are mounted, and FIG. 18B shows the lead arrangement
of the six bypass capacitors.
[0149] Although the number of bypass capacitors 131 is six in this
embodiment, the number may be arbitrarily set as required.
[0150] In the semiconductor device of this embodiment, the use of
the multi-layer wiring board 107 having the inner via holes 109
similarly to the case of the ninth embodiment makes it possible to
reduce the wiring length and thereby increase the operating speed
of the semiconductor device and decrease the power consumption, by
providing the inner via holes 109 just below the circuit pattern
located at the center of the circuit pattern of the area array
arrangement or in the vicinity thereof, in order to make
three-dimensional wiring also for this circuit pattern.
[0151] Particularly in the case of bypass capacitor 131 which is
provided for the purpose of reducing the noise generated in the
semiconductor device, elongation of the wiring between the bypass
capacitor 131 and the semiconductor element 201 leads to increased
noise due to the wiring. Thus, the effect of installing the bypass
capacitor 131 is cancelled out.
[0152] Connecting the bypass capacitor 131 and the semiconductor
element 201 by the three-dimensional wiring comprising the inner
via holes 109 makes it possible to reduce the wiring length and
minimize the noise generated in the semiconductor device.
* * * * *