U.S. patent application number 10/847695 was filed with the patent office on 2004-10-28 for method of etching with nh3 and fluorine chemistries.
Invention is credited to Annapragada, Rao, Sadjadi, Reza.
Application Number | 20040211517 10/847695 |
Document ID | / |
Family ID | 25002834 |
Filed Date | 2004-10-28 |
United States Patent
Application |
20040211517 |
Kind Code |
A1 |
Annapragada, Rao ; et
al. |
October 28, 2004 |
Method of etching with NH3 and fluorine chemistries
Abstract
A method of etching a stack using a fluorine containing gas and
an ammonia containing gas is provided. Generally, the stack is
placed in a plasma processing chamber. A fluorine containing gas is
flowed into the plasma processing chamber. An ammonia containing
gas is flowed into the plasma processing chamber. A plasma is
generated. The stack is then etched. In addition, a device for
etching stacks on a substrate is provided. The device comprises: a
plasma chamber with chamber walls; a plasma confinement device for
reducing plasma contact with the chamber walls; a gas source;
plasma generation and energizing device; and an exhaust system for
pumping plasma away. The gas source comprises a fluorine containing
gas source and an ammonia containing gas source.
Inventors: |
Annapragada, Rao; (Union
City, CA) ; Sadjadi, Reza; (Saratoga, CA) |
Correspondence
Address: |
BEYER WEAVER & THOMAS LLP
P.O. BOX 778
BERKELEY
CA
94704-0778
US
|
Family ID: |
25002834 |
Appl. No.: |
10/847695 |
Filed: |
May 17, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10847695 |
May 17, 2004 |
|
|
|
09746900 |
Dec 22, 2000 |
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Current U.S.
Class: |
156/345.47 ;
257/E21.252; 257/E21.256; 257/E21.579 |
Current CPC
Class: |
H01L 21/31116 20130101;
H01L 21/76807 20130101; C03C 15/00 20130101; H01L 21/31138
20130101 |
Class at
Publication: |
156/345.47 |
International
Class: |
C23F 001/00 |
Claims
1-15. (Canceled)
16. A method of etching a stack, comprising: placing the stack in a
plasma processing chamber; flowing a fluorine containing gas into
the plasma processing chamber; flowing an ammonia containing gas
into the plasma processing chamber; generating a plasma; and
etching the stack.
17. The method, as recited in claim 15, further comprising
confining the plasma to reduce plasma contact with chamber
walls.
18. The method, as recited in claim 15, wherein the stack comprises
a low dielectric constant layer and an etch stop layer over a
substrate.
19. The method, as recited in claim 16, wherein the fluorine
containing gas and the ammonia containing gas are provided in an
alternating manner and wherein a plasma is generated from the
fluorine containing gas and a plasma is generated from the ammonia
containing gas.
20. The method, as recited in claim 16, wherein the confining the
plasma comprises providing a plurality of spaced apart plasma
rings.
21. The method, as recited in claim 20, further comprising
providing a pressure below 300 mTorr during the etching.
22. The method, as recited in claim 15, wherein the stack comprises
a low dielectric constant material layer and an etch stop layer,
wherein the low dielectric constant layer is etched by plasma
generated from the ammonia containing gas and the etch stop layer
is etched plasma generated from the fluorine containing gas.
23. The method, as recited in claim 15, further comprising
stripping a photoresist mask within the plasma processing chamber
wherein the stripping uses a plasma generated from an ammonia
containing stripping gas.
24. A method of etching a stack with at least one organic low
dielectric constant layer, comprising: placing the stack in a
plasma processing chamber comprising a plasma chamber wall, a gas
source, a plasma generation and energizing device, confinement
rings and an exhaust system; flowing an ammonia containing gas into
the plasma processing chamber; generating a plasma from the ammonia
containing gas; performing a first etch from the ammonia containing
gas; flowing a fluorine containing gas into the plasma processing
chamber; generating a plasma from the fluorine containing gas; and
performing a second etch from the fluorine containing gas.
25. The method, as recited in claim 24, wherein the first etch
etches the at least one organic low dielectric constant layer.
26. The method, as recited in claim 25, wherein the stack further
comprises an etch stop layer, wherein the second etch etches the
etch stop layer.
27. The method, as recited in claim 26, further comprising: flowing
an ammonia containing stripping gas into the plasma processing
chamber; generating a plasma from the ammonia containing gas; and
stripping a photoresist mask over the stack.
28. The method, as recited in claim 27, wherein the ammonia
containing stripping gas contains a fluorine containing gas.
29. The method, as recited in claim 28, further comprising
confining the plasma to reduce plasma contact with chamber walls
wherein the confinement rings are used to confine the plasma.
30. The method, as recited in claim 24, further comprising: flowing
an ammonia containing stripping gas into the plasma processing
chamber; generating a plasma from the ammonia containing gas; and
stripping a photoresist mask over the stack.
31. The method, as recited in claim 30, wherein the ammonia
containing stripping gas contains a fluorine containing gas.
32. The method, as recited in claim 24, further comprising
confining the plasma to reduce plasma contact with chamber walls
wherein the confinement rings are used to confine the plasma.
33. A method of etching a stack with at least one organic low
dielectric constant layer, comprising: placing the stack in a
plasma processing chamber comprising a plasma chamber wall, a gas
source, a plasma generation and energizing device, a plurality of
spaced apart confinement rings, and an exhaust system; flowing a
fluorine containing gas into the plasma processing chamber; flowing
an ammonia containing gas into the plasma processing chamber;
generating a plasma; confining the plasma with the confinement
rings; maintaining the pressure below 300 mTorr; and etching the
stack with the generated plasma.
34. The method, as recited in claim 33, wherein a the organic low
dielectric constant material is below a photoresist mask, further
comprising stripping the photoresist mask, wherein the stripping
comprises
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to the fabrication of
semiconductor-based devices. More particularly, the present
invention relates to improved techniques for fabricating
semiconductor-based devices with low dielectric constant
materials.
[0002] In semiconductor-based device (e.g., integrated circuits or
flat panel displays) manufacturing, dual damascene structures may
be used in conjunction with copper conductor material to reduce the
RC delays associated with signal propagation in aluminum based
materials used in previous generation technologies. In dual
damascene, instead of etching the conductor material, vias, and
trenches may be etched into the dielectric material and filled with
copper. The excess copper may be removed by chemical mechanical
polishing (CMP) leaving copper lines connected by vias for signal
transmission. To reduce the RC delays even further, low dielectric
constant materials may be used. Low dielectric constant materials
are here defined as materials with a dielectric constant of less
than about 3.7. These low dielectric constant materials may include
organo-silicate-glass (OSG) materials, such as Coral.TM. and Black
Diamond.TM., or may be purely organic materials, such as SILK.TM.
or Flare.TM.. OSG materials may be silicon dioxide doped with
organic components such as methyl groups. Etching these materials
and stripping the photoresist on these materials may be
significantly different and much more challenging than when
conventional oxide materials are used. Oxygen containing plasmas
may not be suitable for stripping resist on OSG materials, since
oxygen plasmas may oxidize the organic content of low k OSG
materials or may cause bowing during the etch of purely organic low
k materials.
[0003] To facilitate discussion, FIG. 1A is a cross-sectional view
of a stack 100 on a wafer 110 used in the damascene process of the
prior art. A contact 104 may be placed in a dielectric layer 108
over the wafer 110. A barrier layer 112, which may be of silicon
nitride or silicon carbide, may be placed over the contact 104 to
prevent the copper diffusion. A via level low k material layer 116
may be placed over the barrier layer 112 and dielectric layer 108.
A trench stop layer 120 may be placed over the via level low k
layer 116. A trench level low k material layer 124 may be placed
over the trench stop layer 120. A hard mask and/or an
antireflective coating (ARC) layer 128 may be placed over the
trench level low k material layer 124. A patterned resist layer 132
may be placed over the hard mask and/or an antireflective coating
(ARC) layer 128. The via level low k material layer 116 and the
trench level low k material layer 124 may be formed from a low
dielectric constant OSG material or organic material. The trench
etch stop layer 120 may be formed from silicon carbide or silicon
nitride. SiON or organic anti reflective coating (BARC) may be used
to form the ARC layer 128.
[0004] FIG. 1B is a cross-sectional view of the stack 100 after a
via 136 and a trench 140 have been etched. To etch through the hard
mask and/or an antireflective coating (ARC) layer 128, the etch
stop layer 120 and the barrier layer 112 it may be desirable to use
a fluorine containing gas as a gas source for an etching plasma. To
etch through the via level organic low k material layer 116 and the
trench level organic low k material layer 124, it may be desirable
to use an ammonia (NH.sub.3) containing gas as a gas source for an
etching plasma. In addition, for organic low k materials, a
fluorine source may be added to NH.sub.3 to remove any unwanted
polymeric residue from the open areas of the wafer. To etch through
the via level OSG low k material layer 116 and the trench level OSG
low k material layer 124, it may be desirable to use a fluorine
containing gas similar to the gas used to etch the ARC layer 128,
the etch stop layer 120 and barrier layer 112. To strip the photo
resist after via, trench, or barrier etch, it may be desirable to
use NH.sub.3 gas. After the trench and via etches of OSG materials
a polymer crust 144 may be deposited over the patterned resist
layer 132 and side walls of the trench 140 and via 140. To remove a
silicon containing polymer crust 144 it may be desirable to use a
fluorine containing etchant gas in combination with NH3. Although
it is desirable to use an etchant gas with a fluorine containing
gas and an ammonia containing gas either together or in alternating
steps, such attempts in the prior art resulted in the formation of
particles, which may contaminate the plasma processing chamber and
may increase defects in the resulting semiconductor structure. Thus
such processes, which used ammonia and fluorine in the same chamber
were avoided.
[0005] It is desirable to provide an efficient etching with minimal
particle contamination.
SUMMARY OF THE INVENTION
[0006] To achieve the foregoing and other objectives and in
accordance with the purpose of the present invention for etching a
stack, generally, the stack is placed in a plasma processing
chamber. A fluorine containing gas is flowed into the plasma
processing chamber. An ammonia containing gas is flowed into the
plasma processing chamber. A plasma is generated. The stack is then
etched.
[0007] In addition, the present invention provides a device for
etching stacks on a substrate. The device comprises: a plasma
chamber with chamber walls; a plasma confinement device for
reducing plasma contact with the chamber walls; a gas source;
plasma generation and energizing device; and an exhaust system for
pumping plasma away. The gas source comprises a fluorine containing
gas source and an ammonia containing gas source.
[0008] These and other features of the present invention will be
described in more detail below in the detailed description of the
invention and in conjunction with the following figures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The present invention is illustrated by way of example, and
not by way of limitation, in the figures of the accompanying
drawings and in which like reference numerals refer to similar
elements and in which:
[0010] FIGS. 1A-B are cross-sectional views of a stack on a wafer
used in the damascene process of the prior art.
[0011] FIG. 2 is a schematic view of a plasma processing chamber
that may be used in a preferred embodiment of the invention.
[0012] FIG. 3 is a flow chart of a process that uses the plasma
processing chamber.
[0013] FIGS. 4A-B are cross-sectional views of a stack on a wafer
used in the damascene process in a preferred embodiment of the
invention.
[0014] FIG. 5 is a more detailed flow chart for the step of etching
the via.
[0015] FIGS. 6A-C are cross-sectional views of a stack on a wafer
used in the damascene process in a preferred embodiment of the
invention after a via has been etched.
[0016] FIG. 7 is a more detailed flow chart for the step of etching
the trench.
[0017] FIG. 8 is a graph of the number of particles over 0.16
microns versus the number of wafers processed found during a
test.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0018] The present invention will now be described in detail with
reference to a few preferred embodiments thereof as illustrated in
the accompanying drawings. In the following description, numerous
specific details are set forth in order to provide a thorough
understanding of the present invention. It will be apparent,
however, to one skilled in the art, that the present invention may
be practiced without some or all of these specific details. In
other instances, well known process steps and/or structures have
not been described in detail in order to not unnecessarily obscure
the present invention.
[0019] To facilitate discussion, FIG. 2 is a schematic view of a
plasma processing chamber 200 that may be used in a preferred
embodiment of the invention. The plasma processing chamber 200
comprising confinement rings 202, an upper electrode 204, a lower
electrode 208, a gas source 210, and an exhaust pump 220. The gas
source 210 comprises a fluorine containing gas source 212 and an
ammonia containing gas source 216. The gas source 210 may comprise
additional gas sources. Within plasma processing chamber 200, a
substrate 224 is positioned upon the lower electrode 208. The lower
electrode 208 incorporates a suitable substrate chucking mechanism
(e.g., electrostatic, mechanical clamping, or the like) for holding
the substrate 224. The reactor top 228 incorporates the upper
electrode 204 disposed immediately opposite the lower electrode
208. The upper electrode 204, lower electrode 208, and confinement
rings 202 define the confined plasma volume 240. Gas is supplied to
the confined plasma volume 240 by gas source 210 and is exhausted
from the confined plasma volume 240 through the confinement rings
202 and an exhaust port by the exhaust pump 220. A first RF source
244 is electrically connected to the upper electrode 204. A second
RF source 248 is electrically connected to the lower electrode 208.
Different combinations of connecting RF power to the electrode are
possible. In case of Exelan HP both the RF sources are connected to
the lower electrode and the upper electrode is grounded. Chamber
walls 252 surround the confinement rings 202, the upper electrode
204, and the lower electrode 208. Both the first RF source 244 and
the second RF source 248 may comprise a 27 MHz power source and a 2
MHz power source. The upper electrode 204 and the lower electrode
are spaced are preferably spaced apart by a distance of about 1.35
cm but may have a spacing up to 2.0 cm.
[0020] FIG. 3 is a flow chart of a process that uses the plasma
processing chamber 200. A stack 400 is formed on a wafer 224 (step
304), as shown in FIG. 4A. A contact 404 may be placed in a
dielectric layer 408 over a wafer 224. A barrier layer 412, which
may be of silicon nitride or silicon carbide, may be placed over
the contact 404 to prevent a copper or metal diffusion. A via level
low k material layer 416 may be placed over the barrier layer 412.
A trench stop layer 420 may be placed over the via level low k
layer 416. In a preferred embodiment, the trench stop layer 420 may
be made of silicon nitride (SiN). A trench level low k material
layer 424 may be placed over the trench stop layer 420. A hard mask
and/or an antireflective coating (ARC) layer 428 may be placed over
the trench level low k material layer 424. A patterned resist layer
432 patterned for etching a via may be placed over the hard mask
and/or an antireflective coating (ARC) layer 428. The via level low
k material layer 416 and the trench level low k material layer 424
may be formed from a low dielectric constant OSG material or
organic material. The trench etch stop layer 420 may be formed from
silicon carbide, instead of silicon nitride, and the hard mask
layer may be formed from SiN. The ARC layer 428 may be formed from
SiON or organic anti reflective coating. The patterned resist layer
432 may be made of a photo resist layer with the ARC layer 428
acting as an antireflective coating. The stack 400 may be placed
over other layers over the wafer 224.
[0021] The wafer 224 may then be placed in the plasma processing
chamber 200 (step 308). A via is then etched (step 312). Generally,
to provide etching in the plasma processing chamber 200 a gas is
flowed from the gas source 210. Energy is provided by the first RF
source 244 and the second RF source 248, which energizes and
ionizes the gas generating a plasma. The plasma is partially
confined to the confined plasma volume 240, where the plasma is
able to etch the stack 400 on the wafer 224. The plasma is then
vented past the confinement rings 202 to the exhaust pump 220. The
confinement rings 202 reduce plasma interaction with the chamber
walls 252. FIG. 4B is a schematic view of the stack 400 with an
etched via 440. To etch the via 440 the hard mask and or ARC layer
428, the trench level low k material layer 424, the trench stop
layer 420, and the via level low k material layer 416 are
etched.
[0022] FIG. 5 is a more detailed flow chart for the step of etching
the via (step 312) where the trench level low k material 424 and
the via level low k material 416 are organic. First the via is
etched through the hard mask/ARC layer 428 (step 504). One recipe
set of parameters for etching the hard mask/ARC layer 428 is
provided in Table I where sccm stands for Standard Cubic
Centimeters per minute.
1TABLE I MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE
RANGE PRESSURE 0-140 35-105 60-80 (mTorr) Flow rate of Ar 80-320
120-200 150-170 (sccm) Flow rate of C.sub.4F.sub.8 1-9 3-7 5 (sccm)
Flow rate of CF.sub.4 10-80 30-50 35-45 (sccm) Flow rate of O.sub.2
4-26 10-20 13-17 (sccm) Power at 27 MHz 250-750 300-700 450-550
(Watts) Power at 2 MHz 500-1500 750-1250 900-1100 (Watts)
[0023] In a preferred embodiment for etching the hard mask/ARC
layer 428: the flow rate of pressure was approximately 70 mTorr;
approximately 500 Watts was provided at 27 MHz; approximately 1,000
Watts was provided at 2 MHz; the flow rate of Argon (Ar) was
approximately 160 sccm; the flow rate of oxygen (O.sub.2) was
approximately 15 sccm; the flow rate of CF.sub.4 was approximately
40 sccm; the flow rate of C.sub.4F.sub.8 was approximately 5
sccm.
[0024] Next the via level organic low k material layer 424 is
etched (step 508). One recipe set of parameters for etching the
trench level low k material layer 424 is provided in Table II.
2TABLE II MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE
RANGE PRESSURE 0-300 100-200 140-160 (mTorr) Flow rate of NH.sub.3
500-1500 750-1250 900-1100 (sccm) Power at 27 MHz 250-750 300-700
450-550 (Watts) Power at 2 MHz 0-500 0-250 0 (Watts)
[0025] In the preferred embodiment for etching the trench level low
k material layer 424: the flow rate of pressure was approximately
150 mTorr; approximately 500 Watts was provided at 27 MHz;
approximately 0 Watts was provided at 2 MHz; the flow rate of
NH.sub.3 was approximately 1,000 sccm. During the via etch of the
organic low k material using NH.sub.3 plasma, all the resist
material to form the via pattern is removed. After via etch the
stack is repatterned with photo resist trench pattern to form
trench pattern on the wafers.
[0026] Next the trench stop layer 420 is etched (step 512). One
recipe set of parameters for etching an SiN trench stop layer 420
is provided in Table III.
3TABLE III MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE
RANGE PRESSURE 0-180 60-120 80-100 (mTorr) Flow rate of Ar 75-300
100-200 130-170 (sccm) Flow rate of CHF.sub.3 6-18 9-15 11-13
(sccm) Flow rate of CF.sub.4 10-40 15-35 20-30 (sccm) Flow rate of
O.sub.2 5-15 7-13 9-11 (sccm) Flow rate of N.sub.2 15-45 20-40
25-35 (sccm) Power at 27 MHz 300-1200 450-750 550-650 (Watts) Power
at 2 MHz 50-200 75-125 90-110 (Watts)
[0027] In the preferred embodiment for etching the trench stop
layer 420: the flow rate of pressure was approximately 90 mTorr;
approximately 600 Watts was provided at 27 MHz; approximately 100
Watts was provided at 2 MHz; the flow rate of Argon (Ar) was
approximately 150 sccm; the flow rate of oxygen (O.sub.2) was
approximately 10 sccm; the flow rate of CF.sub.4 was approximately
25 sccm; the flow rate of CHF.sub.3 was approximately 12 sccm; the
flow rate of N.sub.2 was approximately 30 sccm.
[0028] Next the trench level low k material layer 424 is etched
(step 516). One recipe set of parameters for etching the trench
level low k material layer 424 is provided in Table IV.
4TABLE IV MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE
RANGE PRESSURE 0-300 100-200 140-160 (mTorr) Flow rate of NH.sub.3
500-1500 750-1250 900-1100 (sccm) Power at 27 MHz 250-750 300-700
450-550 (Watts) Power at 2 MHz 0-500 0-250 0 (Watts)
[0029] In the preferred embodiment for etching the via level low k
material layer 416: the flow rate of pressure was approximately 150
mTorr; approximately 500 Watts was provided at 27 MHz;
approximately 0 Watts was provided at 2 MHz; the flow rate of
NH.sub.3 was approximately 1,000 sccm;.
[0030] While etching via 440 in the OSG low k materials to the
barrier layer 412 the via etching may be stopped. A silicon
containing polymer crust 444 may be deposited over the patterned
resist layer 432 and the sidewalls of the via 440 as a result of
the via etching. The plasma chamber 200 may be used to strip the
polymer crust 444, when etching OSG low k materials, and the
patterned resist layer 432, when etching either OSG low k materials
or organic low k materials (step 316). A recipe for stripping the
polymer crust 444 and patterned resist layer 432 may use NH.sub.3
as a plasma source gas for stripping the photoresist. Once the
polymer crust 444 and patterned resist layer 432 have been
stripped, the wafer 224 may be removed from the plasma chamber 200
to allow the depositing of a new patterned resist layer 504 (step
320), as shown in FIG. 6A.
[0031] The wafer 224 may be placed back in the plasma chamber 200
(step 324). A trench 604 is etched (step 328), as shown in FIG. 6B.
FIG. 7 is a more detailed flow chart for the step of etching the
trench (step 328) when the trench level layer 424 is an organic low
k material. First, the trench is etched through the hard mask/ARC
layer 428 (step 704). One recipe set of parameters for etching the
hard mask/ARC layer 428 is provided in Table I above. In a
preferred embodiment for etching the hard mask/ARC layer 428: the
flow rate of pressure was approximately 70 mTorr; approximately 500
Watts was provided at 27 MHz; approximately 1,000 Watts was
provided at 2 MHz; the flow rate of Argon (Ar) was approximately
160 sccm; the flow rate of oxygen (O.sub.2) was approximately 15
sccm; the flow rate of CF.sub.4 was approximately 40 sccm; the flow
rate of C.sub.4F.sub.8 was approximately 5 sccm.
[0032] Next the trench level organic low k material layer 424 is
etched (step 708). One recipe set of parameters for etching the
trench level organic low k material layer 424 is provided in Table
II. In the preferred embodiment for etching the trench level low k
material layer 424: the flow rate of pressure was approximately 150
mTorr; approximately 500 Watts was provided at 27 MHz;
approximately 0 Watts was provided at 2 MHz; the flow rate of
NH.sub.3 was approximately 1,000 sccm.
[0033] Once the trench 604 has been etched to the trench stop layer
420 the trench etching may be stopped. The barrier layer 412 may
then be etched (step 332). One recipe set of parameters for etching
the barrier layer 412 is provided in Table V.
5TABLE V MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE
RANGE PRESSURE 100-220 130-190 150-170 (mTorr) Flow rate of Ar
100-500 200-400 250-350 (sccm) Flow rate of CHF.sub.3 5-40 10-30
15-25 (sccm) Flow rate of N.sub.2 40-200 60-140 80-120 (sccm) Power
at 27 MHz 300-800 500-600 400 (Watts) Power at 2 MHz 50-400 100-300
200 (Watts)
[0034] In the preferred embodiment for etching the barrier layer
412: the flow rate of pressure was approximately 158 mTorr;
approximately 400 Watts was provided at 27 MHz; approximately 200
Watts was provided at 2 MHz; the flow rate of Argon (Ar) was
approximately 300 sccm; the flow rate of CHF.sub.3 was
approximately 20 sccm; the flow rate of N.sub.2 was approximately
100 sccm.
[0035] A silicon containing polymer crust 608 may be deposited over
the patterned resist layer 432 and the sidewalls of the via 440 and
trench 604 as a result of the trench etching, as shown in FIG. 6B.
The plasma chamber 200 may be used to strip the polymer crust 608
and patterned resist layer 504 (step 336). A recipe for stripping
the polymer crust 608 and patterned resist layer 504 may use
NH.sub.3 as a plasma source gas for stripping the photoresist. Once
the polymer crust 608 and patterned resist layer 504 have been
stripped, the wafer 224, as shown in FIG. 6C, may be removed from
the plasma chamber 200 (step 340).
[0036] In an Exelan HP, made by LAM Research Corporation.TM. of
Fremont, Calif., a test was performed using the above recipes for
500 wafers. An O.sub.2 clean was done every 60 seconds. Particles
were collected periodically in 25 or 50 wafer intervals. A particle
count was taken using an NH.sub.3 recipe as described above for 10
seconds, where the particle size monitored was 0.16 to 9,000
microns with 6 mm edge exclusion. The test temperature was about
0.degree. C. FIG. 8 is a graph of the number of particles over 0.16
microns (Particle count) versus the number of wafers processed
(0-500) found during the test. It can be seen that the level of
particle generation is below 30, which is normal for the chamber,
indicating that the confinement rings 202, small plasma volume 240,
and exhaust pump 220 speed help to minimize plasma contact with the
walls of the chamber so that formed ammonium fluoride does not have
a chance to condense onto the walls of the chamber to form a higher
number of particles.
[0037] In another embodiment of the invention, where the trench
level low k material layer 424 and the via level low k material 416
are made of an OSG material the trench level low k material 424,
the via level low k material 416, the ARC layer 428, barrier layer
412, and the trench stop layer 420 may be all etched with fluorine
containing etchant gases. For stripping the patterned resist layer
432 an NH.sub.3 stripping gas may be used. More preferably an
NH.sub.3 gas combined with a CF.sub.4 gas may be used to strip the
patterned resist layer. In such an embodiment an ammonia containing
gas and a fluorine containing gas are used at the same time within
the same plasma chamber and at alternating times.
[0038] In other embodiments other types of plasma confinement
devices, which keep plasma from the chamber walls may be used in
place of the confinement rings. Other types of plasma generation
and energizing systems may be used in place of the upper and lower
electrodes 204, 208 and the first and second RF sources 244, 248,
which may generate and energize a plasma in a small plasma
volume.
[0039] Another embodiment of the invention may use a combined
resist strip and barrier etch step to reduced etching damage as
described in U.S. patent application Ser. No. ______ (Attorney
Docket Number LAM1P158) entitled "A Combined Resist Strip And
Barrier Etch Process For Dual Damascene Structures" by Rao
Annapragada and Reza Sadjadi, with the same filing date, and which
is incorporated by reference.
[0040] Sidewalls formed by the crust may be removed during the
stripping of the resist or may be removed using a separate wet
stripping as described in U.S. patent application Ser. No. ______
(Attorney Docket Number LAM1P156) entitled "Method of Preventing
Damage To Organo-Silicate-Glass Materials During Resist Stripping"
by Rao Anapragada, with the same filing date, and which is
incorporated by reference.
[0041] While this invention has been described in terms of several
preferred embodiments, there are alterations, permutations, and
substitute equivalents, which fall within the scope of this
invention. It should also be noted that there are many alternative
ways of implementing the methods and apparatuses of the present
invention. It is therefore intended that the following appended
claims be interpreted as including all such alterations,
permutations, and substitute equivalents as fall within the true
spirit and scope of the present invention.
* * * * *