U.S. patent application number 10/803363 was filed with the patent office on 2004-10-07 for adhesion layer for pt on sio2.
This patent application is currently assigned to Infineon Technologies North America Corp.. Invention is credited to Lian, Jingyu, Limb, Young, Nagel, Nicolas, Wise, Michael, Wong, Kwong Hon.
Application Number | 20040197984 10/803363 |
Document ID | / |
Family ID | 33097741 |
Filed Date | 2004-10-07 |
United States Patent
Application |
20040197984 |
Kind Code |
A1 |
Lian, Jingyu ; et
al. |
October 7, 2004 |
Adhesion layer for Pt on SiO2
Abstract
Si, Al, Al plus TiN, and Ir02 are used as adhesion layers to
prevent peeling of noble metal electrodes, such as Pt, from a
silicon dioxide (5i0.sub.2) substrate in capacitor structures of
memory devices.
Inventors: |
Lian, Jingyu; (Tokyo,
JP) ; Wong, Kwong Hon; (Wappingers Falls, NY)
; Wise, Michael; (Larangeville, NY) ; Limb,
Young; (Poughkeepsie, NY) ; Nagel, Nicolas;
(Munich, DE) |
Correspondence
Address: |
LERNER, DAVID, LITTENBERG,
KRUMHOLZ & MENTLIK
600 SOUTH AVENUE WEST
WESTFIELD
NJ
07090
US
|
Assignee: |
Infineon Technologies North America
Corp.
San Jose
CA
International Business Machines Corp.
Armonk
NY
|
Family ID: |
33097741 |
Appl. No.: |
10/803363 |
Filed: |
March 17, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10803363 |
Mar 17, 2004 |
|
|
|
10408339 |
Apr 7, 2003 |
|
|
|
Current U.S.
Class: |
438/240 |
Current CPC
Class: |
H01L 28/65 20130101;
Y10T 428/12875 20150115; Y10T 428/12597 20150115 |
Class at
Publication: |
438/240 |
International
Class: |
H01L 021/8242 |
Claims
1. A method of fabricating a high dielectric constant (high-k)
capacitor structure, said method comprising: depositing an adhesion
layer on a SiO.sub.2 substrate, said adhesion layer being selected
from the group consisting of Si, Al, Al plus TiN, and SiO.sub.2;
and depositing a noble metal bottom electrode on said adhesion
layer.
2. The method of claim 1 further comprising: depositing a high-k
dielectric material on said bottom electrode; depositing a top
electrode on said high-k dielectric layer; patterning said top
electrode and said high-k dielectric layer; depositing an
insulation layer thereon; opening vias to said top electrode in the
insulation layer; depositing a metal pad layer in said vias and
atop said insulation layer; and patterning the metal pad layer.
3. The method recited in claim 1 wherein said bottom electrode is
Pt
4. The method recited in claim 2 wherein said top electrode is
Pt.
5. The method recited in claim 2 wherein said insulation layer is
SiO.sub.2.
6. The method recited in claim 2 wherein said metal pad layer is Al
or W.
7. A method of fabricating a three-dimensional capacitor structure,
comprising the steps of: depositing a Si0.sub.2 layer on a
substrate; opening vias in said SiO.sub.2 layer; depositing
polycrystalline Si into said vias; planarizing and recessing back
said polycrystalline Si to form poly plugs in said vias; depositing
a barrier layer in said vias atop said poly plugs; planarizing said
barrier layer; depositing an adhesion layer atop said barrier layer
and said SiO.sub.2 layers, said adhesive layer being selected from
the group consisting of Si, Al, Al plus TiN, and IrO.sub.2; and
depositing a noble metal bottom electrode on said adhesive
layer.
8. The method recited in claim 7 wherein said adhesion layer is
conductive.
9. The method recited in claim 8 wherein said adhesion layer is
Ir0.sub.2.
10. The method recited in claim 7 wherein said adhesion layer is a
non-conductive layer, and said method further comprises: removing a
portion of said adhesion layer that is above said barrier layer
before depositing said bottom electrode.
11. The method recited in claim 7 wherein said bottom electrode is
Pt.
12. The method recited in claim 7 further comprising: patterning
said bottom electrode to form a three-dimensional structure;
depositing a high-k dielectric layer thereon; and depositing a top
electrode on said high-k dielectric layer.
13. The method recited in claim 12 further comprising: depositing
and patterning a Si0.sub.2 layer to form a three-dimensional
structure prior to depositing said adhesion layer.
14. The method recited in claim 13 further comprising: removing a
top planar part of said bottom electrode; depositing a high-k
dielectric layer; and depositing a top electrode
15. The method recited in claim 14 wherein said bottom and top
electrodes are Pt.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. application Ser.
No. 10/408,339, filed Apr. 7, 2003, the disclosure of which is
incorporated herein.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to integrated circuit (IC)
memory devices and, more particularly, to the inclusion of one or
more thin layers, such as Si, Al, Ir0.sub.2, or Al plus TiN, as an
adhesion layer between a noble metal layer, such as Pt, and a
silicon dioxide (Si0.sub.2)layer to form the electrode for high-k
dielectric Dynamic Random Access Memory (DRAM) and Ferroelectric
Random Access Memory (FRAM) applications.
[0003] Capacitors with high dielectric constant (high-k) materials
as the dielectric are increasingly used in high density devices.
The high-k dielectrics used in DRAM devices are generally formed at
a high temperature oxidation ambient, as are ferroelectric
materials used in FRAM devices. To avoid oxidation of the
electrodes at these high temperatures, noble metal electrodes are
used with the dielectric. Platinum (Pt) electrodes are typically
used for the high-k dielectric capacitors in DRAM devices and for
FRAM devices because of its excellent oxidation resistance and high
work function. However, Pt poorly adheres to silicon dioxide and
results in peeling of the Pt at various process steps, such as
during the formation of the capacitor and during the following Back
End of Line (BEOL) processes. To prevent peeling, an intermediate
adhesion layer may be added between the Pt and SiO.sub.2 layers.
Currently, the adhesion layers used include Ti, TaSiN or TiN.
[0004] Though these materials can improve the adhesion between the
Pt and SiO.sub.2 layers in the "as-deposited" state, roughening of
the Pt surface or a local peeling has been observed after the
subsequent annealing step which is typically at a temperature of
500 to 580.degree. C. in an oxygen ambient. Further, when high-k
dielectric and ferroelectric layers are deposited at temperatures
below 500.degree. C., the layers have degraded film quality with
decreased capacitance, which degrades the performance of the
device.
[0005] It is therefore desirable to provide an improved adhesion
layer between the noble metal electrodes and the SiO.sub.2 layers.
It is also desirable to provide an adhesion layer that prevents the
peeling of the noble metal electrodes of the capacitor
structures.
SUMMARY OF THE INVENTION
[0006] The present invention provides one or more adhesion layers
which prevent the Pt electrode from peeling from the SiO.sub.2.
Such layers include IrO.sub.2, Si, Al, or Al plus TiN as the
adhesion layer.
[0007] According to an aspect of the invention, in a semiconductor
capacitor structure formed on a silicon dioxide (SiO.sub.2)
substrate and having a noble metal electrode, an adhesion layer is
disposed between the electrode and the SiO.sub.2 substrate. The
adhesion layer is selected from a group consisting of silicon (Si),
aluminum (Al), aluminum (Al) plus titanium nitride (TiN) and
iridium oxide (IrO.sub.2).
[0008] According to a further aspect of the invention, an adhesion
layer is selected from a group consisting of Si, Al, Al plus TiN,
and IrO.sub.2 and is disposed between a noble metal layer and a
silicon dioxide layer.
[0009] According to another aspect of the invention, a high
dielectric constant (high-k) capacitor structure is fabricated. An
adhesion layer is deposited on a SiO.sub.2 substrate. The adhesion
layer is selected from a group consisting of Si, Al, Al plus TiN,
and IrO.sub.2. A noble metal bottom electrode is deposited on the
adhesion layer.
[0010] In accordance with this aspect of the invention, a high-k
dielectric material is deposited on the bottom electrode. A top
electrode is deposited on the high-k dielectric layer, and the top
electrode and the high-k dielectric are patterned. An insulation
layer is deposited thereon, and vias are opened in the insulation
layer. A metal pad layer is deposited in the vias and atop the
insulation layer, and the metal pad layer is patterned.
[0011] According to a still further aspect of the invention, a
3-dimensional capacitor structure is fabricated. A silicon dioxide
layer is deposited on a substrate, and vias are opened in the
silicon dioxide layer. Polycrystalline silicon is deposited into
the vias, and the polycrystalline silicon is planarized and
recessed back to form poly plugs in the vias. A barrier layer is
deposited in the vias, and the barrier layer is planarized. An
adhesion layer is deposited atop the barrier layer and the
SiO.sub.2 layer. The adhesion layer is selected from a group
consisting of Si, Al, Al plus TiN, and IrO.sub.2. A noble metal
bottom electrode is deposited on the adhesion layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The foregoing and other objects, aspects and advantages will
be better understood from the following detailed description of the
invention with reference to the drawings in which:
[0013] FIG. 1 is a graph illustrating x-ray diffraction analysis
data and showing the stability of IrO.sub.2 at temperatures of up
to 750.degree. C.
[0014] FIG. 2 is a cross-sectional view showing a planar capacitor
structure of a device according to an embodiment of the
invention.
[0015] FIG. 3 is a cross-sectional view showing a first
three-dimensional capacitor structure of a device according to
another embodiment of the invention.
[0016] FIG. 4 is a cross-sectional view showing a second
three-dimensional capacitor structure of a device according to a
further embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0017] The invention is directed to the use of one or more layers,
such as IrO.sub.2, Si and Al plus TiN, that improve adhesion
between an electrode layer and a SiO.sub.2 layer.
[0018] IrO.sub.2, as an example, has a good adhesion to silicon
oxide as can be predicted by its oxygen bonding nature. IrO.sub.2
remains stable up to 750.degree. C. when exposed to an oxygen
ambient, as shown in FIG. 1. Further, polycrystalline IrO.sub.2 is
conductive and can serve as a part of the electrode.
[0019] Alternatively, thin Si or Al layers can form a uniform thin
silicon oxide or aluminum oxide layer underneath a Pt electrode to
improve the adhesion of Pt on SiO.sub.2 layer without decreasing
dielectric film quality on the Pt.
1TABLE 1 Adhesion Test Results Adhesion Layer and Thickness Pt
Thickness Adhesion (Mpam1/2) None 1000 .ANG. Failed TiN, CVD, 50
.ANG. 1000 .ANG. <0.16 TaSiN, 250 .ANG. 2500 .ANG. 0.24 Ti, PVD,
50 .ANG. 1000 .ANG. 0.26 Al, 100 .ANG. 1000 .ANG. 0.23 Al, 100
.ANG., +Ti, 200 .ANG. 1000 .ANG. 0.32 Poly Si, 50 .ANG. 1000 .ANG.
0.30
[0020] Table 1 shows the adhesion properties of various materials
after exposure in an oxygen ambient at 640.degree. C. for five
minutes. Samples with a known chemical vapor deposited (CVD) TiN
adhesion layer could not be tested since its adhesion was less than
0.16. Samples with known Ti or TaSiN adhesion layers had improved
adhesion over the CVD physical vapor deposition (PVD) but were not
suitable because of dielectric layer degradation on a Pt/Ti or
TaSiN/SiO.sub.2 structure. Better or at least comparable adhesion
was obtained for samples with a polycrystalline Si, Al, or Al plus
Ti adhesion layers of the invention.
[0021] To test the adhesion, a planar capacitor structure, such as
is shown in FIG. 2, was prepared by first depositing an adhesion
layer 21 on a SiO.sub.2 layer atop a substrate (not shown). The
adhesion layer is preferably Si, Al, Al plus Ti or IrO.sub.2. A Pt
bottom electrode 23 is then deposited atop the adhesion layer 21. A
high-k dielectric 24 is then deposited atop the adhesion layer, and
a top electrode 25 (Pt) is deposited thereon. The high-k dielectric
may be a (Ba,Sr)TiO.sub.3 (BST) material. The top electrode 25 and
the high-k dielectric 24 are then patterned and an insulation
(SiO.sub.2) layer 26 is thereafter deposited atop this structure.
Vias are then opened in the SiO.sub.2, and a Al or W a metal pad
layer 27 is deposited in and on top of the vias and is then
patterned.
[0022] Electrical testing results using the planar capacitor
structure shown in FIG. 2 show essentially no change in the
capacitance of the dielectric layer when using a poly Si adhesion
layer, as Table 2 shows.
2TABLE 2 Electrical Test Results Adhesion Layer Capacitance (pF)
None 350-400 Poly Si, 50 .ANG. 350-400
[0023] The adhesion layers of the invention may be used in any
integration scheme where adhesion of the electrode to the SiO.sub.2
layer is of importance. Without limiting the scope of the
invention, two examples using three-dimensional capacitor
structures on devices for a DRAM application are now described.
[0024] Referring to FIG. 3, a SiO.sub.2 layer 31 is formed on a
device substrate (not shown). Vias are opened in the SiO.sub.2
layer 31, and a polycrystalline Si layer 32 is deposited on top of
the SiO.sub.2 and into the vias. The polycrystalline Si is
planarized to remove any material atop the SiO.sub.2 layer, using a
chemical mechanical polish (CMP) process, and the polysilicon is
then recessed back, leaving poly plugs in the vias between the
surface of the SiO.sub.2 layer. Next, a barrier layer 33 is
deposited atop the SiO.sub.2 layer and the poly plugs, and the
barrier layer is likewise subjected to a CMP process. An adhesion
layer 34 is then deposited, and a Pt bottom electrode 35 is
deposited atop the adhesion layer. If a conductive adhesion layer
is used, such as IrO.sub.2 the bottom electrode is deposited
directly onto the adhesion layer. Alternatively, if a
non-conductive adhesion layer is used, the part of the adhesion
layer that is over the barrier layer is removed, and then the
bottom electrode 35 is then deposited. Thereafter, the bottom
electrode layer is patterned to form a three-dimensional structure
(not shown). A high-k dielectric, such as BST, is then deposited
and is covered with Pt top electrode layer to form the capacitor
structure.
[0025] An alternative three-dimensional structure is shown in FIG.
4. First, a SiO.sub.2 layer 41 is deposited on a device substrate
(not shown). Vias are then opened in the SiO.sub.2 layer, and a
polycrystalline Si layer 42 is formed in the vias and atop the
SiO.sub.2. The polycrystalline Si is then planarized using a CMP
process and recessed back, thereby leaving poly plugs in the vias.
Next, a barrier layer 43 is deposited and subjected to a CMP
process. A SiO.sub.2 layer 44 is deposited and then patterned to
form a three-dimensional structure, and an adhesion layer 45 is
deposited thereon. A bottom (Pt) electrode 46 is deposited directly
on the adhesion layer when the adhesion layer is conductive, such
as when IrO.sub.2 is used. Alternatively, the adhesion layer is
removed in the regions above the barrier layer 43 and the bottom
electrode is thereafter deposited. The top planar part of the
bottom electrode 46 is then removed (not shown), and a high-k
dielectric, such as BST, is deposited and covered with a Pt layer
to form capacitors.
[0026] While the invention has been described in terms of preferred
embodiments, those skilled in the art will recognize that the
invention can be practiced with modification within the spirit and
scope of the appended claims.
* * * * *