U.S. patent application number 10/705185 was filed with the patent office on 2004-08-19 for buried conductors.
This patent application is currently assigned to Micron Technology , Inc.. Invention is credited to Farrar, Paul A., Noble, Wendell P..
Application Number | 20040159950 10/705185 |
Document ID | / |
Family ID | 22088234 |
Filed Date | 2004-08-19 |
United States Patent
Application |
20040159950 |
Kind Code |
A1 |
Farrar, Paul A. ; et
al. |
August 19, 2004 |
Buried conductors
Abstract
Buried conductors within semiconductor devices and structures,
and methods for forming such conductors, are disclosed. In one
embodiment of the invention, a semiconductor structure includes a
substrate and a plurality of conductive elements buried within the
substrate. The conductive elements may be metal, such as tungsten
or a tungsten alloy. The invention described in the disclosure
provides for advantages including formation of three-dimensional
structures without resort to external wiring.
Inventors: |
Farrar, Paul A.; (So.
Burlington, VT) ; Noble, Wendell P.; (Milton,
VT) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG, WOESSNER & KLUTH, P.A.
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Micron Technology , Inc.
|
Family ID: |
22088234 |
Appl. No.: |
10/705185 |
Filed: |
November 11, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10705185 |
Nov 11, 2003 |
|
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|
09069326 |
Apr 29, 1998 |
|
|
|
6696746 |
|
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Current U.S.
Class: |
257/758 ;
257/E21.597; 257/E23.168 |
Current CPC
Class: |
H01L 2223/54453
20130101; H01L 2924/0002 20130101; H01L 21/76898 20130101; H01L
2924/0002 20130101; H01L 21/743 20130101; H01L 2924/00 20130101;
H01L 23/535 20130101 |
Class at
Publication: |
257/758 |
International
Class: |
H01L 029/00 |
Claims
We claim:
1. A semiconductor device comprising: a substrate having an active
semiconductor layer formed thereon; a plurality of substantially
parallel buried conductive elements separated from the active
semiconductor layer by and surrounded by an insulating material;
and a deep trench capacitor formed through the active semiconductor
layer, the insulative material, and between the conductive
elements, the deep trench capacitor surrounded by a dielectric
material.
2. The semiconductor device of claim 1, wherein the conductive
elements include a material with a high melting point that prevents
unwanted metallurgical changes.
3. The semiconductor device of claim 1, wherein the conductive
elements are formed from a metal.
4. The semiconductor device of claim 3, wherein the metal comprises
one of tungsten and a tungsten alloy.
5. The semiconductor device of claim 1, wherein the substrate
comprises doped silicon.
6. The semiconductor device of claim 1, wherein the insulating
material is formed from the group consisting of: oxide,
oxy-nitride, and nitride.
7. The semiconductor device of claim 1, wherein the deep trench
capacitor includes P+ silicon.
8. A semiconductor device comprising: a substrate having an active
semiconductor layer formed thereon; a first buried layer buried at
a first depth within the substrate and including a plurality of
substantially parallel first conductive elements oriented in a
first direction; a second buried layer buried at a second depth
within the substrate and including a plurality of substantially
parallel second conductive elements oriented in a second direction,
wherein the second depth is greater than the first depth; an
insulating material arranged to separate the first and second
buried layer and to separate the first and second conductive
elements, and a deep trench capacitor formed through the active
semiconductor layer, the insulative material, and between the
plurality of substantially parallel first conductive elements.
9. The semiconductor device of claim 8, wherein the first buried
layer and the second buried layer are substantially parallel to the
active semiconductor layer;
10. The semiconductor device of claim 8, wherein the insulating
material separates the first buried layer from the active
semiconductor layer.
11. The semiconductor device of claim 8, wherein the first buried
layer and the second buried layer include a material with a high
melting point that prevents unwanted metallurgical changes when
processing the active semiconductor layer.
12. The semiconductor device of claim 8, wherein the plurality of
substantially parallel second conductive elements are connected to
conductive parts that extend upwardly on opposite sides of the
first buried layer beyond the first depth adjacent outer ones of
the plurality of substantially parallel first conductive
elements.
13. The semiconductor device of claim 8, wherein the deep trench
capacitor includes a charge storage material and a dielectric
material separating the charge storage material from the
substrate.
14. The semiconductor device of claim 8, wherein the charge storage
material includes P+ silicon.
15. A semiconductor device comprising: a substrate having an active
semiconductor layer formed thereon; a first buried layer buried at
a first depth within the substrate and including a plurality of
substantially parallel first conductive elements oriented in a
first direction; a second buried layer buried at a second depth
within the substrate and including a plurality of substantially
parallel second conductive elements oriented in a second direction,
wherein the second depth is greater than the first depth; an
insulating material arranged to separate the first and second
buried layer and to separate the first and second conductive
elements; a deep trench capacitor formed through the active
semiconductor layer, the insulative material, and between the
plurality of substantially parallel first conductive elements; and
wherein the plurality of substantially parallel second conductive
elements are located either in front of or behind the deep trench
capacitor.
16. The semiconductor device of claim 15, wherein the active device
layer includes integrated circuits adapted for use with at least
one of the group consisting of: dynamic random-access memory
(DRAM), static random-access-memory (SRAM), flash memory,
synchronous dynamic random-access-memory (SDRAM), extended-data-out
random-access-memory (EDO RAM), and burst-extended-data-out
random-access-memory (BEDO RAM).
17. The semiconductor device of claim 15, wherein at least one of
the first conductive elements and the second conductive elements is
metal.
18. The semiconductor device of claim 17, wherein the metal
comprises one of tungsten and a tungsten alloy.
19. The semiconductor device of claim 17, wherein the metal
comprises one of a non-radioactive element selected from groups
IVB, VB, VIB, VIIB, and VIIIB of the periodic table, and an alloy
of the non-radioactive element.
20. The semiconductor device of claim 15, wherein the plurality of
substantially parallel second conductive elements are connected to
conductive parts that extend upwardly on opposite sides of the
first buried layer beyond the first depth adjacent outer ones of
the plurality of substantially parallel first conductive
elements.
21. The semiconductor device of claim 15, wherein the second
direction is orthogonal to the first direction.
Description
RELATED APPLICATION
[0001] This application is a divisional of U.S. application Ser.
No. 09/069,326 filed on Apr. 29, 1998 which is incorporated herein
by reference.
[0002] This application is related to cofiled, copending and
coassigned application entitled "Hi Q Inductive Elements" Attorney
docket #303.381US1, U.S. application Ser. No. 09/069,346, now
issued as U.S. Pat. No. 6,025,261.
FIELD OF THE INVENTION
[0003] This invention relates generally to semiconductor
technology, and more particularly to buried conductors within
semiconductor devices and structures, and methods for forming such
conductors.
BACKGROUND OF THE INVENTION
[0004] Semiconductor technology pervades most electronic devices
today. Computers, televisions, videocassette recorders, cameras,
etc., all use semiconductor integrated circuits to varying degrees.
For example, the typical computer includes microprocessors and
dedicated controller integrated circuits (i.e., video controllers,
audio controllers, etc.), as well as memory, such as dynamic
random-access memory.
[0005] Traditionally, the semiconductor industry has used a process
that requires first building a device or series of devices, and
then connecting the devices together with a wiring level or levels
above the active-device surfaces. As integrated circuit designs
have become more complex, several external wiring planes have been
used to connect adjacent devices. As the number of wiring levels
grew, the requirement of the vertical connections has significantly
reduced the usefulness of the lower levels.
[0006] A limited prior art solution is to use a single buried
wiring level in the initial phases of semiconductor fabrication. A
single buried wiring level overcomes the limitations of using
external wiring planes, but is not entirely applicable to current
semiconductor technology. For example, stacked chip arrays require
more than one wiring level. Therefore, even if a single buried
wiring level is used, external wiring planes are still nevertheless
required.
[0007] For these and other reasons, there is a need for multiple
buried wiring levels within a single semiconductor device or
structure.
SUMMARY OF THE INVENTION
[0008] The above-identified disadvantages, shortcomings and
problems are overcome by the present invention, which will be
understood by reading and studying the following specification. In
one embodiment of the invention, a semiconductor structure includes
a substrate and a plurality of conductive elements buried within
the substrate. The conductive elements may be metal, such as
tungsten or a tungsten alloy.
[0009] The use of a plurality of conductive elements buried within
the substrate of a semiconductor structure overcomes limitations
found in the prior art. For example, where each conductive element
is a separate buried plane, there may be two or more such planes,
such that a three-dimensional semiconductor structure may be
formed. Three-dimensional structures, as those of ordinary skill
within the art can appreciate, have the ability to significantly
reduce the average distance from one segment of a large computer
processor and associated memory to another, allowing for
higher-density semiconductor storage devices and faster
processors.
[0010] The invention includes semiconductor structures, devices,
and methods to form such structures and devices, of varying scope.
In addition to the aspects and advantages of the present invention
described in this summary, further aspects and advantages of the
invention will become apparent by reference to the drawings and by
reading the detailed description that follows.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIGS. 1(a), 1(b) and 1(c) show exemplary semiconductor
structures according to varying embodiments of the invention;
[0012] FIGS. 2(a), 2(b), 2(c), 2(d) and 2(e) show an exemplary
semiconductor structure according to an embodiment of the
invention;
[0013] FIGS. 2(f) and 2(g) show cross-sectional views respectively
taken generally along lines 2(f)-2(f) and 2(g)-2(g) of FIG.
2(a);
[0014] FIGS. 3(a), 3(b), 3(c), 3(d) and 3(e) show a process to form
buried conductors according to an embodiment of the invention;
and,
[0015] FIG. 4 shows a representative semiconductor memory device in
conjunction with which embodiments of the invention may be
practiced.
DETAILED DESCRIPTION OF THE INVENTION
[0016] In the following detailed description of exemplary
embodiments of the invention, reference is made to the accompanying
drawings which form a part hereof, and in which is shown by way of
illustration specific exemplary embodiments in which the invention
may be practiced. These embodiments are described in sufficient
detail to enable those skilled in the art to practice the
invention, and it is to be understood that other embodiments may be
utilized and that logical, mechanical, electrical and other changes
may be made without departing from the spirit or scope of the
present invention. The following detailed description is,
therefore, not to be taken in a limiting sense, and the scope of
the present invention is defined only by the appended claims.
[0017] The detailed description is divided into five sections. In
the first section, exemplary structures having buried conductors
are described. In the second section, a method by which buried
conductors may be formed according to one embodiment of the
invention is provided. In the third section, processes to form the
exemplary structures of the first section are given. In the fourth
section, a representative memory device in conjunction with which
embodiments of the invention may be practiced is presented.
Finally, in the fifth section, a conclusion is provided.
Exemplary Structures
[0018] In this section of the detailed description, exemplary
structures according to varying embodiments of the invention are
presented. Those of ordinary skill within the art will appreciate
that the structures described in this section are merely exemplary,
and the invention is not limited to these particular structures.
Rather, a description of the exemplary structures is provided to
inform those of ordinary skill within the art the types of
structures covered by the invention. The structures may thus be
utilized in the formation of a semiconductor device incorporating
the structures.
[0019] Referring first to FIG. 1(a), one such exemplary structure
is shown. Within N+ substrate 100 (i.e., doped silicon) are two
buried conductive layers, layer 102 and layer 104. Layer 102
includes a series of conductive lines separated by an insulative
material, where the conductive lines are parallel to the view shown
in FIG. 1(a), such that only one such line is seen. Layer 104
includes a series of conductive lines also separated by an
insulative material, but where the conductive lines are
perpendicular to the view shown in FIG. 1(a), such that two such
lines are seen. Layer 102 may thus be described as oriented in an x
plane, and layer 104 oriented in a y plane. A conductive element
may refer to either a layer within a semiconductor structure, or a
conductive line within such a layer.
[0020] The invention is not particularly limited to the type of
material utilized to form the buried conductive layers or elements.
A metal, such as tungsten or a tungsten alloy, is desirably used.
Other metals include the non-radioactive elements selected from
groups IVB, VB, VIB, VIIB, and VIIIB of the periodic table, and
alloys of such elements. Each conductive element, be it a separate
layer or a line within a layer, may be of the same material, or a
different material, as the other conductive elements.
[0021] Insulative material 106 surrounds conductive layers 102 and
104, to prevent short circuiting. The invention is also not
particularly limited to the type of insulative material used. In
one embodiment of the invention, silicon dioxide, also known as
oxide, is utilized. Other insulative materials amenable to the
invention include nitride, and oxy-nitride.
[0022] Over the layer formed by insulative material 106, as shown
in FIG. 1(a) is active semiconductor layer 108 (e.g., a P-
epitaxial layer). The active circuitry of the semiconductor
structure are formed within this layer. Because layer 108 rests on
an insulator layer (material 106), such active circuitry includes
silicon-on-insulator (SOI), as known within the art.
[0023] Optionally, a connection between layers 102 and 104 may also
be made, or between either layer and active semiconductor layer
108, using ion-implanted nickel, as described in the coassigned and
copending application entitled "Implanted Conductor and Method of
Making," filed Mar. 14, 1997, Ser. No. 08/818,230, which is hereby
incorporated by reference, or using a conventional fill strategy as
known within the art.
[0024] Those of ordinary skill within the art can also appreciate
that additional conductive layers may also be formed. Thus, third,
fourth, fifth, et seq., layers may be formed within the structure
as necessary. These other layers may be positioned above or below
the other layers, and may have lines oriented in a direction
parallel to or orthogonal to the directions in which the lines of
the other layers are oriented. All the conductive layers provide
for internal wiring within the semiconductor structure, to allow
three-dimensional structures to be formed.
[0025] Referring next to FIG. 1(b), another exemplary structure
according to an embodiment of the invention is shown. Within N+
substrate 110 are two buried conductive elements, lines 114.
Insulative material 116 surrounds each line, and also separates
lines 114 from active semiconductor layer 118. In addition, deep
trench capacitor 120 cuts through active layer 118, insulative
material 116, and within substrate 110 between lines 114. The deep
trench capacitor trench is filled with P+ silicon, and is
surrounded by dielectric material 117. An alternative embodiment to
that of FIG. 1(b) might have an additional level of buried
elements, where the elements are located either in front of and/or
behind the plane of the trench capacitor.
[0026] Referring now to FIG. 1(c), still another exemplary
structure according to an embodiment of the invention is shown.
Within N+ substrate 122 are two buried conductive layers, layer 124
and 126. Each layer includes a series of conductive lines. Layer
124 is oriented in an x plane (parallel to the view shown in FIG.
1(c)), and layer 126 is oriented in a y plane (perpendicular to the
view shown in FIG. 1(c)). Insulative material 128 surrounds
conductive layers 124 and 126. Active semiconductor layer 130 lies
above the layer formed by insulative material 128.
[0027] Conductive connection 132 is formed prior to the buried
wiring, as those of ordinary skill within the art can appreciate.
Conductive connection 132 thus provides an external connection to
layer 124; connection 132 cuts through substrate 122 at the back
(bottom) of the structure of FIG. 1(c). Connection 132 may then
allow the die of which the structure is a part to be attached
electrically to another structure of another die, as described in
U.S. Pat. Nos. 5,270,261 and 5,202,754, which are hereby
incorporated by reference.
[0028] Connection 132 is desirably formed by first etching a hole
within substrate 122, and then oxidizing the surface to provide for
insulative material 128 around the hole. A conductive plug may then
be deposited to form connection 132. A metal, such as tungsten or a
tungsten alloy, may be the material utilized to form the
connection. The invention is not so particularly limited,
however.
[0029] Another exemplary structure according to an embodiment of
the invention is shown by reference to FIGS. 2(a)-2(e). Referring
first to FIG. 2(a), within N+ substrate 200 are two buried
conductive layers, layer 204 and 206, each having a plurality of
lines. Each layer is oriented in both the x and y planes; that is,
each has a plurality of lines oriented in both the x and y planes.
Insulative material 208 surrounds conductive layers 204 and 206.
Active semiconductor layer 210 lies above the layer formed by
insulative material 208. As shown in FIG. 2(a), the parts of each
layer 204 and 206 oriented in the x plane, parallel to the view
shown in FIG. 2(a), are accessible from the top of the structure.
That is, a conductive connection to each of these parts of layers
204 and 206 cuts through active layer 210 and the layer formed by
insulative material 208.
[0030] Referring next to FIG. 2(b), a first mask pattern used to
produce the trenches for (first, lower) layer 206 of the structure
is shown. Lines 212 correspond to the lines of conductive layer 206
that are oriented in the y plane, and lines 214 correspond to the
lines of conductive layer 206 that are oriented in the x plane.
Exposure of the substrate layer using this first mask pattern, and
subsequent etching, thus results in the formation of trenches
which, when deposited with conductive material, make for the lines
of layer 206, as those of ordinary skill within the art can
appreciate.
[0031] Similarly, referring to FIG. 2(c), a second mask pattern
used to produce the trenches for (second, higher) layer 204 of the
structure is shown. Lines 216 correspond to the lines of conductive
layer 204 that are oriented in the y plane, and lines 218
correspond to the lines of conductive layer 204 that are oriented
in the x plane. Exposure of the substrate layer, after formation of
layer 204, using this second mask pattern, and subsequent etching,
thus results in the formation of trenches which, when deposited
with conductive material, make for the lines of layer 204.
[0032] Finally, FIG. 2(d) shows a portion of the silicon island
structure that may be used as the seed points for the epitaxial
growth of the N+ substrate level, while FIG. 2(e) shows a schematic
layout of possible contacts to the buried wiring lines (both within
layer 204 and layer 206). The structure of FIGS. 2(a)-2(e) thus is
a three-dimensional semiconductor structure, having two levels of
buried wiring lines; each level of buried wiring lines includes
lines oriented in the x and the y planes. Such buried wiring lines
may render it unnecessary to use external wiring for connections of
the structure.
Exemplary Method to Form Buried Conductors
[0033] In this section of the detailed description, an exemplary
method to form buried conductors, according to one embodiment of
the invention, is described. Utilizing this method, those of
ordinary skill within the art will then be able to form the
exemplary structures of the previous section.
[0034] Referring first to FIG. 3(a), within silicon substrate 300,
trench 302, of the desired width and depth is cut. Trench 302 has a
bottom, and at least two sidewalls. Substrate 300 is part of a
wafer having a front side (top) and a back side (bottom). Referring
next to FIG. 3(b), oxidation is performed to produce oxide layer
304 of sufficient thickness to provide electrical insulation for
the subsequently formed wire. Oxide layer 304 is present on the
bottom and the walls of trench 302. Seed layer 306 is then
deposited, desirably using a line of sight deposition process such
as collimated sputtering. In one embodiment, seed layer 306 is
titanium, although the invention itself is not so limited to this
material. The seed material may be an element selected from groups
IVB, VB, or VIB, of the periodic table, for example.
[0035] Referring next to FIG. 3(c), the seed layer and the oxide on
the top surface of the wafer (i.e., not at the bottom of trench
302) is removed, desirably by chemical mechanical polishing (CMP),
or another selective removal process. The conductive material to be
used to form the buried wiring level is then deposited within the
trench, such as tungsten 308, substantially at the bottom of the
trench (i.e., over the seed layer). This is desirably accomplished
by a selective metal deposition process, such as plating or
chemical vapor deposition. (However, a line of sight process--such
as columnated sputtering or long through evaporation--may also be
used, in which case a seed layer deposition prior to conductive
material deposition is unnecessary.) Any incidental deposition on
the surface of the wafer may be removed by CMP. Insulative material
310 is then deposited to sufficiently fill the trench. Material 310
may be oxide (silicon dioxide), or any other suitable
insulator.
[0036] Referring next to FIG. 3(d), the top wafer surface is again
polished by CMP or another suitable process to expose substrate
300, but not far enough to expose tungsten 308. The exposed
substrate 300 may then be used as seed points for epitaxial silicon
growth. It is noted that the width of tungsten 308 within trench
302 is less than the photo image that was used to etch trench 302;
thus, it is possible to produce line widths that are less than the
minimum photo-definable image.
[0037] Referring finally to FIG. 3(e), the process of FIGS. 3(a)
through 3(e) may be repeated to produce another level of buried
wiring. Thus, as shown in FIG. 3(e), two buried conductors are
present: a deeper conductor at the bottom of trench 302, and a
shallower conductor at the bottom of trench 312. Greater-depth
conductors are formed first, and then lesser-depth conductors are
formed. Utilizing the described process, any number of buried
wiring levels may be produced. Furthermore, while as described only
one trench for each layer has been formed, those of ordinary skill
within the art can appreciate that any number of trenches for each
layer may be formed.
[0038] Other steps may also be added to the described process. For
example, the back side of the wafer may be thinned to expose parts
of at least the bottom-most conductive layer. For further example,
the first layer may be connected to the second layer, using
ion-implanted nitrogen, as described in the coassigned and
copending application entitled "Implanted Conductor and Method of
Making," filed Mar. 14, 1997, Ser. No. 08/818,230, or using a
conventional fill strategy as known within the art.
Specific Processes
[0039] Utilizing the exemplary method described in the previous
section of the detailed description, those of ordinary skill in the
art are thus enabled to form the exemplary structures described in
the first section of the detailed description. However, specific
processes to form the exemplary structures of the first section of
the detailed description are provided in this section of the
detailed description. These processes correspond to the exemplary
method described in the previous section, except that more specific
detail is provided.
[0040] A specific process that can be used to produce the
structures of FIG. 1(a) and FIG. 1(c) (except for the tungsten
connection of FIG. 1(c), a process to form such a connection having
already been described) is first provided. Starting with an N+
wafer, 0.3 micron width trenches 1.2 microns deep are etched in the
silicon to form the spaces for the first (deepest) level of wiring.
850 angstrom of thermal oxide are then grown, thus reducing the
trench width to 0.225 micron. Alternatively, instead of growing
thermal oxide, 500 angstroms of CVD oxide may be deposited. The use
of a CVD layer is particularly advantageous when several layers of
buried wiring are to be used. 75 angstrom of titanium is then
deposited using collimated sputtering. Chemical mechanical
polishing is performed to remove titanium and oxide from the wafer
surface, exposing the N+ silicon underneath. Next, 0.4 micron of
tungsten is selectively deposited over the titanium, using
low-temperature hydrogen reduction of tungsten fluoride, where the
titanium serves as the seed layer. 1450 angstrom of silicon dioxide
is deposited, and chemical mechanical polishing is used to remove
the oxide from the wafer surface, but leaving oxide over the
tungsten-filled trenches. Thus, the first wiring level is
constructed.
[0041] A second wiring level is constructed by first etching 0.3
micron width trenches 0.6 micron deep in the silicon and the oxide
where the trench crosses the oxide-covered tungsten of the first
wiring level. 850 angstrom silicon oxide is deposited, and 75
angstrom of titanium is deposited. The titanium and oxide on the
wafer surface is removed via chemical mechanical polishing. If
connections are desired between the two levels of conductors, they
can be made through the insulator separating the layers (or the
conducting layer and an active device) using ion-implanted nickel,
as described in the coassigned and copending application entitled
"Implanted Conductor and Method of Making," filed Mar. 14, 1997,
Ser. No. 08/818,230, or using a conventional fill strategy as known
within the art. 0.4 micron of tungsten is selectively deposited
over the titanium, and chemical mechanical polishing or another
suitable technique is used to remove any tungsten inadvertently
deposited on the wafer surface. 5200 angstrom of oxide is deposited
via chemical vapor deposition to fill the trenches and cap the
conductors.
[0042] Finally, chemical mechanical polishing is used to remove the
oxide and expose the silicon surface. The open windows of the
exposed N+ silicon are used as nucleation points to grow P- silicon
epitaxially. A desired photo mask is used to define the areas of
P-/N+contact and to selectively remove the P- silicon. 1000
angstrom of oxide is deposited, and chemical mechanical polishing
is used to expose the P- silicon. Finally, the P- areas that are
exposed are used as nucleating sites to grow a P- epitaxial layer
to cover the wafer surface. A specific process that can be used to
form the structure of FIG. 1(b) is now described. On an N+ wafer,
0.3 micron width trenches, 0.6 microns deep, are etched to form the
spaces for the buried level of wiring. 850 angstrom of thermal
oxide is grown. 75 angstrom of titanium is deposited using
collimated sputtering, to provide a seed layer for the conductive
material. Chemical mechanical polishing, or another suitable
technique, is used to remove titanium and oxide from the wafer
surface. 0.4 micron of tungsten is selectively deposited at the
bottom of the trench, using low temperature hydrogen reduction of
tungsten fluoride, where the titanium serves as the seed layer.
1075 angstrom of oxide is deposited, and chemical mechanical
polishing is used to remove the oxide from the wafer surface. The
resulting open windows to the N+ silicon are used as nucleation
points to grow a P- silicon epitaxial layer.
[0043] Next, an appropriate photomask is used to define the areas
of P-/N+ contact, and the deep trench capacitor is etched. A
desired oxygen-nitrogen-oxygen (ONO) structure, or other
dielectric, is grown to provide the capacitor dielectric. The
capacitor trench is then filled with P+ polysilicon, and chemical
mechanical polishing is used to expose the P- silicon surface.
Conventional processing may then be used to form devices and memory
cells within the active layer.
[0044] Finally, a specific process that can be used to produce the
structure of FIGS. 2(a)-2(e) is described. On an N-type wafer, 0.3
micron width trenches, 1.2 microns deep, are etched to form the
spaces for the first (deepest) level of wiring. 850 angstrom of
thermal oxide is grown, and 75 angstrom of titanium is deposited
using collimated sputtering. Chemical mechanical polishing is used
to remove titanium and oxide from the wafer surface. 0.4 micron of
tungsten is selectively deposited over the titanium at the bottom
of the trench using low temperature hydrogen reduction of tungsten
fluoride, the titanium serving as the seed layer. 1450 angstrom of
oxide is deposited, and chemical mechanical polishing is used to
remove the oxide from the wafer surface.
[0045] Next, 0.3 micron width troughs, 0.6 microns deep, are etched
in the silicon and the oxide in the pattern of the upper (second)
level of metal. 850 angstrom of thermal oxide is CVD deposited and
75 angstrom of titanium is deposited. Titanium and oxide from the
wafer surface is removed via chemical mechanical polishing. If
connections are desired between the two levels of conductors, they
can be made through the insulator separating the layers (or the
conducting layer and an active device) using ion-implanted nickel,
as described in the coassigned and copending application entitled
"Implanted Conductor and Method of Making," filed Mar. 14, 1997,
Ser. No. 08/818,230, or using a conventional fill strategy as known
within the art. 0.4 microns of tungsten are selectively deposited
over the titanium. If necessary, any tungsten inadvertently
deposited on the wafer surface is removed using chemical mechanical
polishing or other suitable techniques. 5200 angstrom of oxide is
deposited via chemical vapor deposition, and chemical mechanical
polishing is used to remove the oxide sufficiently to expose the N+
silicon surface.
[0046] Next, using the open windows to the N+ silicon as nucleation
points, P- silicon is grown epitaxially. If contacts from the
buried wiring levels to structures on or above the P- epitaxial
surface are desired, windows are etched in the epitaxial layer
using a mask (such as that which has been shown in FIG. 2(d)). An
oxide layer equal in thickness to the P- silicon layer is then
deposited, and the surface of the wafer is polished (via chemical
mechanical polishing) to expose the P- silicon; contact is then
made to the wiring levels using ion-implanted nickel as described
in the coassigned and copending application entitled "Implanted
Conductor and Method of Making," filed Mar. 14, 1997, Ser. No.
08/818,230, or using a conventional fill strategy as known within
the art.
[0047] Those of ordinary skill within the art can appreciate that
the order of the processes described may be modified without
affecting materially the final structure produced. For example, in
the process just described, the oxide could be removed from the
wafer surface prior to titanium deposition, with the titanium on
the surface being removed in a subsequent polishing process. The
seed layer used could be other materials besides titanium, such as
zirconium. Similarly, while the material used for the wiring
structure was described as tungsten, other metals and alloys
thereof are suitable. Desirably, a material of sufficiently low
resistance to provide a good electrical conductor is used.
Sufficient electromigration resistance to enable the required
current to be carried without failure during the devices' expected
lifetime is desirable.
[0048] Furthermore, the diffusion rate of the element or elements
used as conductors through the oxide or other insulator should
desirably be low enough so that the amount diffusing through the
insulating film and into the silicon is insufficient to degrade the
properties of the device or devices formed in the various silicon
layers. The melting point of the metal or alloy used should
desirably be sufficiently high to prevent its melting or other
unwanted metallurgical changes during further processing of the
silicon. For example, aluminum and aluminum alloys that have been
used in traditional wiring applications may have melting points
that are low enough to cause concern; however, future changes in
processing technology that may lower the temperature requirements
of device operation may mute this concern.
[0049] In addition, copper, which has a high diffusion rate in
silicon dioxide and is a junction "poison," as known within the
art, is another metal which at the time of filing of this patent
application may not be able to be considered for use unless a
suitable barrier layer surrounds it. The requirements for the
buried wiring levels may be fulfilled with more or less ease by a
number of materials, including the non-radioactive elements of
groups IVB, VB, VIB, VIIB, and VIIIB of the periodic table. Of
these elements, those in groups VB, VIB and VIIIB may be most
desirable because of their lower resistance. A material such as
tungsten may be desired because of its reasonably low resistance
and because its deposition is relatively well understood by those
of ordinary skill within the art.
[0050] Furthermore, although selective chemical vapor deposition
has been specifically referenced to deposit the conductive material
after the seed layer has been deposited, the invention is not so
limited to such deposition. For example, electroless plating may be
substituted for selective chemical vapor deposition. Also, instead
of chemical vapor deposition oxide for the final trench fill after
the last metal deposition, an alternative material such as
polyimide may also be used.
Representative Memory Device
[0051] In this section, a typical memory device in conjunction with
which an embodiment of the invention may be implemented is
described. Referring to FIG. 4, memory device 10 includes memory
array 12, control circuit 14, input/output buffers 16, and address
decoder 18. Memory array 12 includes a plurality of memory cells
organized into rows and columns. The memory cells are accessed in
response to an address signal provided on the address lines A0 . .
. AN running to address decoder 18, which includes both row and
column decoder circuitry. Input/output buffers 16 are provided for
bi-directional communication via the data communications lines DQ1
. . . DQN running out of buffers 16. Control circuit 14 regulates
the memory device operations in response to control signals
including, but not limited to, a Clock (CLK), a Row Access Strobe
(RAS*), a Column Access Strobe (CAS*), a Write Enable (WE*), and a
Clock Enable (CKE).
[0052] As will be appreciated by those skilled in the art, the
present invention is not limited to any particular type of memory
device or repair memory device. In one embodiment, the devices are
dynamic random-access-memories (DRAMs), including those available
from Micron Technology, Inc., of Boise, Id. In other embodiments,
the devices are static random-access-memories (SRAMs), flash
memories, synchronous dynamic random-access-memories (SDRAMs),
extended-data-out random-access-memories (EDO RAMs), and
burst-extended-data-out random-access-memories (BEDO RAMs), as
those skilled in the art will appreciate.
CONCLUSION
[0053] Buried conductors have been described. The utilization of
such conductors provides for internal wiring levels within
semiconductor structures and devices, making external wiring levels
unnecessary. Thus, three-dimensional structures, such as
stacked-chip arrays, may be constructed without resorting to such
external wiring levels. This renders these structures faster, and
more densely integrated, than would otherwise be possible. Those of
ordinary skill within the art can, however, appreciate that other
advantages may and can be provided by the invention.
[0054] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement which is calculated to achieve the
same purpose may be substituted for the specific embodiments shown.
This application is intended to cover any adaptations or variations
of the present invention. Therefore, it is manifestly intended that
this invention be limited only by the following claims and
equivalents thereof.
* * * * *