Noble; Wendell P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Noble; Wendell P..The latest application filed is for "trench dram cell with vertical device and buried word lines".

Company Profile

0.122.77

Noble; Wendell P. - Milton VT
NOBLE, WENDELL P - MILTON VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Trench DRAM cell with vertical device and buried word lines Grant 7,883,962 - Noble February 8, 2	2011-02-08
Trench DRAM Cell with Vertical Device and Buried Word Lines App 20100297819 - Noble; Wendell P.	2010-11-25
Trench DRAM cell with vertical device and buried word lines Grant 7,785,961 - Noble August 31, 2	2010-08-31
Trench DRAM Cell with Vertical Device and Buried Word Lines App 20090130807 - Noble; Wendell P.	2009-05-21
Trench DRAM cell with vertical device and buried word lines Grant 7,488,641 - Noble February 10, 2	2009-02-10
Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Grant 7,282,400 - Noble , et al. October 16, 2	2007-10-16
Multiple oxide thicknesses for merged memory and logic applications Grant 7,271,467 - Noble , et al. September 18, 2	2007-09-18
Methods of forming interconnect lines Grant 7,232,713 - Noble June 19, 2	2007-06-19
Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor Grant 7,223,678 - Noble , et al. May 29, 2	2007-05-29
Method of forming vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, soi and thin film structures Grant 7,217,606 - Forbes , et al. May 15, 2	2007-05-15
Ultra high density flash memory App 20070069281 - Noble; Wendell P. ; et al.	2007-03-29
Methods of forming electrical connections Grant 7,176,087 - Noble February 13, 2	2007-02-13
Ultra high density flash memory App 20060255397 - Noble; Wendell P. ; et al.	2006-11-16
Ultra high density flash memory App 20060258096 - Noble; Wendell P. ; et al.	2006-11-16
Multiple Oxide Thicknesses For Merged Memory And Logic Applications App 20060244057 - Noble; Wendell P. ; et al.	2006-11-02
Method of forming at least one interconnection to a source/drain region in silicon-on-insulator integrated circuitry Grant 7,105,388 - Noble September 12, 2	2006-09-12
Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction App 20060141697 - Noble; Wendell P. ; et al.	2006-06-29
DRAM technology compatible processor/memory chips App 20060124981 - Forbes; Leonard ; et al.	2006-06-15
Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor Grant 7,057,223 - Noble , et al. June 6, 2	2006-06-06
Vertical gain cell and array for a dynamic random access memory and method for forming the same Grant 7,049,196 - Noble May 23, 2	2006-05-23
Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Grant 7,045,880 - Noble , et al. May 16, 2	2006-05-16
DRAM technology compatible processor/memory chips Grant 7,023,040 - Forbes , et al. April 4, 2	2006-04-04
Buried conductors App 20060033181 - Farrar; Paul A. ; et al.	2006-02-16
Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor App 20060003525 - Noble; Wendell P. ; et al.	2006-01-05
Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Grant 6,960,821 - Noble , et al. November 1, 2	2005-11-01
Method of forming buried conductors Grant 6,946,389 - Farrar , et al. September 20, 2	2005-09-20
Trench DRAM cell with vertical device and buried word lines Grant 6,946,700 - Noble September 20, 2	2005-09-20
DRAM technology compatible processor/memory chips Grant 6,924,194 - Forbes , et al. August 2, 2	2005-08-02
Programmable memory cell using charge trapping in a gate oxide Grant 6,909,635 - Forbes , et al. June 21, 2	2005-06-21
Base current reversal SRAM memory cell and method Grant 6,891,213 - Noble May 10, 2	2005-05-10
Multiple oxide thicknesses for merged memory and logic applications Grant 6,887,749 - Noble , et al. May 3, 2	2005-05-03
Semiconductor Processing Methods Of Forming Integrated Circuitry, Forming Conductive Lines, Forming A Conductive Grid, Forming A Conductive Network, Forming An Electrical Interconnection To A Node Location, Forming An Electrical Interconnection With A Transistor Source/drain Region, And Integrated C Grant 6,884,687 - Noble April 26, 2	2005-04-26
Trench DRAM cell with vertical device and buried word lines App 20050048714 - Noble, Wendell P.	2005-03-03
Semiconductor Processing Methods Of Forming Integrated Circuitry, Forming Conductive Lines, Forming A Conductive Grid, Forming A Conductive Network, Forming An Electrical Interconnection To A Node Location, Forming An Electrical Interconnection With A Transistor Source/drain Region, And Integrated C Grant 6,861,311 - Noble March 1, 2	2005-03-01
Method for forming gate segments for an integrated circuit Grant 6,858,504 - Noble February 22, 2	2005-02-22
Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction App 20050026369 - Noble, Wendell P. ; et al.	2005-02-03
Multiple oxide thicknesses for merged memory and logic applications App 20050023593 - Noble, Wendell P. ; et al.	2005-02-03
Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor App 20040235243 - Noble, Wendell P. ; et al.	2004-11-25
Memory cell having a vertical transistor with buried source/drain and dual gates Grant 6,818,937 - Noble , et al. November 16, 2	2004-11-16
Field programmable logic arrays with vertical transistors Grant 6,812,516 - Noble , et al. November 2, 2	2004-11-02
DRAM technology compatible processor/memory chips Grant 6,809,985 - Forbes , et al. October 26, 2	2004-10-26
Multiple oxide thicknesses for merged memory and logic applications Grant 6,800,927 - Noble , et al. October 5, 2	2004-10-05
Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor Grant 6,798,009 - Forbes , et al. September 28, 2	2004-09-28
Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk. SOI and thin film structures and method of forming same App 20040161886 - Forbes, Leonard ; et al.	2004-08-19
Buried conductors App 20040159950 - Farrar, Paul A. ; et al.	2004-08-19
Circuits and methods using vertical, complementary transistors Grant 6,777,744 - Noble August 17, 2	2004-08-17
Programmable memory cell using charge trapping in a gate oxide App 20040151029 - Forbes, Leonard ; et al.	2004-08-05
Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor Grant 6,764,901 - Noble , et al. July 20, 2	2004-07-20
Vertical gain cell and array for a dynamic random access memory and method for forming the same App 20040132232 - Noble, Wendell P.	2004-07-08
Vertical gain cell and array for a dynamic random access memory and method for forming the same Grant 6,756,622 - Noble June 29, 2	2004-06-29
Memory address decode array with vertical transistors Grant 6,747,305 - Forbes , et al. June 8, 2	2004-06-08
DRAM technology compatible processor/memory chips Grant 6,741,519 - Forbes , et al. May 25, 2	2004-05-25
Method for forming gate segments for an integrated circuit App 20040063265 - Noble, Wendell P.	2004-04-01
Trench DRAM cell with vertical device and buried word lines App 20040046201 - Noble, Wendell P.	2004-03-11
Programmable mosfet technology and programmable address decode and correction Grant 6,700,821 - Forbes , et al. March 2, 2	2004-03-02
Base current reversal SRAM memory cell and method Grant 6,699,742 - Noble March 2, 2	2004-03-02
Methods, structures, and circuits for transistors with gate-to-body capacitive coupling Grant 6,696,330 - Forbes , et al. February 24, 2	2004-02-24
Buried conductors Grant 6,696,746 - Farrar , et al. February 24, 2	2004-02-24
4 F2 folded bit line DRAM cell structure having buried bit and word lines Grant 6,689,660 - Noble , et al. February 10, 2	2004-02-10
Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/drain region, and integrated c App 20040018671 - Noble, Wendell P.	2004-01-29
Method for reading a vertical gain cell and array for a dynamic random access memory Grant 6,680,864 - Noble January 20, 2	2004-01-20
Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction App 20030209782 - Noble, Wendell P. ; et al.	2003-11-13
Technique for gated lateral bipolar transistors Grant 6,638,807 - Forbes , et al. October 28, 2	2003-10-28
Compact SOI body contact link Grant 6,633,067 - Noble October 14, 2	2003-10-14
Trench DRAM cell with vertical device and buried word lines Grant 6,624,033 - Noble September 23, 2	2003-09-23
Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor Grant 6,610,566 - Forbes , et al. August 26, 2	2003-08-26
Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor App 20030142564 - Forbes, Leonard ; et al.	2003-07-31
Programmable memory address decode array with vertical transistors Grant 6,597,037 - Forbes , et al. July 22, 2	2003-07-22
Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Grant 6,580,154 - Noble , et al. June 17, 2	2003-06-17
Highly conductive composite polysilicon gate for CMOS integrated circuits Grant 6,573,169 - Noble , et al. June 3, 2	2003-06-03
Memory address decode array with vertical transistors App 20030087495 - Forbes, Leonard ; et al.	2003-05-08
A Method Of Forming At Least One Interconnection To A Source/Drain Region In Silicon-On-Insulator Integrated Circuitry App 20030073296 - Noble, Wendell P.	2003-04-17
Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/drain region, and integrated c App 20030073268 - Noble, Wendell P.	2003-04-17
Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/drain region, and integrated c App 20030073306 - Noble, Wendell P.	2003-04-17
Base current reversal sram memory cell and method App 20030063486 - Noble, Wendell P.	2003-04-03
Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor Grant 6,537,871 - Forbes , et al. March 25, 2	2003-03-25
Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor Grant 6,528,837 - Forbes , et al. March 4, 2	2003-03-04
MOSFET technology for programmable address decode and correction Grant 6,521,958 - Forbes , et al. February 18, 2	2003-02-18
Methods of forming transistors and connections thereto Grant 6,509,213 - Noble January 21, 2	2003-01-21
Memory cell having a vertical transistor with buried source/drain and dual gates Grant 6,504,201 - Noble , et al. January 7, 2	2003-01-07
Methods, structures, and circuits for transistors with gate-to-body capacitive coupling App 20030001208 - Forbes, Leonard ; et al.	2003-01-02
Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/drain region, and integrated c App 20020197848 - Noble, Wendell P.	2002-12-26
Field programmable logic arrays with vertical transistors App 20020195649 - Noble, Wendell P. ; et al.	2002-12-26
Applications for non-volatile memory cells Grant 6,498,739 - Cloud , et al. December 24, 2	2002-12-24
Memory address decode array with vertical transistors Grant 6,498,065 - Forbes , et al. December 24, 2	2002-12-24
Highly conductive composite polysilicon gate for CMOS integrated circuits Grant 6,492,694 - Noble , et al. December 10, 2	2002-12-10
Memory cell with vertical transistor and buried word and body lines Grant 6,492,233 - Forbes , et al. December 10, 2	2002-12-10
Dram technology compatible processor/memory chips App 20020176313 - Forbes, Leonard ; et al.	2002-11-28
DRAM technology compatible processor/memory chips App 20020176293 - Forbes, Leonard ; et al.	2002-11-28
Dram technology compatible processor/memory chips App 20020176314 - Forbes, Leonard ; et al.	2002-11-28
Field programmable logic arrays with vertical transistors Grant 6,486,027 - Noble , et al. November 26, 2	2002-11-26
Programmable logic array with vertical transistors Grant 6,486,703 - Noble , et al. November 26, 2	2002-11-26
Dram technology compatible processor/memory chips App 20020172089 - Forbes, Leonard ; et al.	2002-11-21
Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same Grant 6,483,171 - Forbes , et al. November 19, 2	2002-11-19
Circuits and methods for a static random access memory using vertical transistors Grant 6,477,080 - Noble November 5, 2	2002-11-05
Memory cell having a vertical transistor with buried source/drain and dual gates App 20020149048 - Noble, Wendell P. ; et al.	2002-10-17
DRAM technology compatible processor/memory chips Grant 6,452,856 - Forbes , et al. September 17, 2	2002-09-17
Multiple oxide thicknesses for merged memory and logic applications App 20020127797 - Noble, Wendell P. ; et al.	2002-09-12
Multiple oxide thicknesses for merged memory and logic applications App 20020127884 - Noble, Wendell P. ; et al.	2002-09-12
Trench DRAM cell with vertical device and buried word lines App 20020127811 - Noble, Wendell P.	2002-09-12
Methods, structures, and circuits for transistors with gate-to-body capacitive coupling Grant 6,448,615 - Forbes , et al. September 10, 2	2002-09-10
Method for fabricating CMOS transistors having matching characteristics and apparatus formed thereby Grant 6,436,748 - Forbes , et al. August 20, 2	2002-08-20
Technique for gated lateral bipolar transistors App 20020102803 - Forbes, Leonard ; et al.	2002-08-01
Integrated circuit with conductive lines disposed within isolation regions App 20020086466 - Noble, Wendell P.	2002-07-04
Circuits and methods for dual-gated transistors Grant 6,414,356 - Forbes , et al. July 2, 2	2002-07-02
Semiconductor Processing Methods Of Forming Integrated Circuitry, Forming Conductive Lines, Forming A Conductive Grid, Forming A Conductive Network, Forming An Electrical Interconnection To A Node Location, Forming An Electrical Interconnection With A Transistor Source/drain Region, And Integrated C Grant 6,403,429 - Noble June 11, 2	2002-06-11
Memory cell having a vertical transistor with buried source/drain and dual gates Grant 6,399,979 - Noble , et al. June 4, 2	2002-06-04
Trench DRAM cell with vertical device and buried word lines Grant 6,395,597 - Noble May 28, 2	2002-05-28
Circuit And Method For An Open Bit Line Memory Cell With A Vertical Transistor And Trench Plate Trench Capacitor App 20020053689 - FORBES, LEONARD ; et al.	2002-05-09
Method of forming multiple oxide thicknesses for merged memory and logic applications Grant 6,383,871 - Noble , et al. May 7, 2	2002-05-07
DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors Grant 6,380,581 - Noble , et al. April 30, 2	2002-04-30
Methods of forming electrical connections App 20020048921 - Noble, Wendell P.	2002-04-25
Methods for dual-gated transistors Grant 6,376,317 - Forbes , et al. April 23, 2	2002-04-23
MOSFET technology for programmable address decode and correction App 20020027264 - Forbes, Leonard ; et al.	2002-03-07
Circuits and methods for a static random access memory using vertical transistors App 20020027802 - Noble, Wendell P.	2002-03-07
Dram Technology Compatible Processor/memory Chips App 20020027825 - FORBES, LEONARD ; et al.	2002-03-07
Dram Technology Compatible Non Volatile Memory Cells App 20020024083 - NOBLE, WENDELL P. ; et al.	2002-02-28
Highly Conductive Composite Polysilicon Gate For Cmos Integrated Circuits App 20020014660 - NOBLE, WENDELL P. ; et al.	2002-02-07
Applications for non-volatile memory cells App 20020015322 - Cloud, Eugene H. ; et al.	2002-02-07
Highly conductive composite polysilicon gate for CMOS integrated circuits App 20020014672 - Noble, Wendell P. ; et al.	2002-02-07
Buried conductors App 20020009874 - Farrar, Paul A. ; et al.	2002-01-24
Method of fabricating body contacted and backgated transistors Grant 6,340,612 - Noble , et al. January 22, 2	2002-01-22
Circuit and method for a memory cell using reverse base current effect App 20020006698 - Noble, Wendell P.	2002-01-17
Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor App 20020006699 - Noble, Wendell P. ; et al.	2002-01-17
Discrete devices including EAPROM transistor and NVRAM memory cell with edge defined ferroelectric capacitance, methods for operating same, and apparatuses including same Grant 6,337,805 - Forbes , et al. January 8, 2	2002-01-08
Discrete Devices Including Eaprom Transistor And Nvram Memory Cell With Edge Defined Ferroelectric Capacitance, Methods For Operating Same, And Apparatus Including Same App 20020001219 - FORBES, LEONARD ; et al.	2002-01-03
Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, Forming an electrical interconnection with a transistor source/drain region, and integrated c App 20020001885 - Noble, Wendell P.	2002-01-03
Method for forming gate segments for an integrated circuit App 20010055221 - Noble, Wendell P.	2001-12-27
Trench Dram Cell With Vertical Device And Buried Word Lines App 20010053575 - NOBLE, WENDELL P.	2001-12-20
Circuits and methods for a static random access memory using vertical transistors App 20010053089 - Noble, Wendell P.	2001-12-20
Method Of Forming Conductive Lines App 20010046728 - NOBLE, WENDELL P.	2001-11-29
Silicon-on-insulator Islands App 20010042871 - NOBLE, WENDELL P	2001-11-22
Structure and method for reducing threshold voltage variations due to dopant fluctuations Grant 6,320,222 - Forbes , et al. November 20, 2	2001-11-20
Construction and application for non-volatile, reprogrammable switches Grant 6,319,773 - Noble , et al. November 20, 2	2001-11-20
Silicon-on-insulator islands Grant 6,319,333 - Noble November 20, 2	2001-11-20
Another technique for gated lateral bipolar transistors Grant 6,307,235 - Forbes , et al. October 23, 2	2001-10-23
Vertical gain cell and array for a dynamic random access memory and method for forming the same App 20010030338 - Noble, Wendell P.	2001-10-18
Circuits and methods for a static random access memory using vertical transistors Grant 6,304,483 - Noble October 16, 2	2001-10-16
Ultra high density flash memory App 20010029077 - Noble, Wendell P. ; et al.	2001-10-11
Vertical gain cell and array for a dynamic random access memory and method for forming the same App 20010028078 - Noble, Wendell P.	2001-10-11
Circuits and methods using vertical, complementary transistors App 20010025985 - Noble, Wendell P.	2001-10-04
Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction App 20010026006 - Noble, Wendell P. ; et al.	2001-10-04
Applications for non-volatile memory cells Grant 6,297,989 - Cloud , et al. October 2, 2	2001-10-02
Circuits and methods using vertical complementary transistors Grant 6,294,418 - Noble September 25, 2	2001-09-25
Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location forming an electrical interconnection with a transistor source/drain region, and integrated ci App 20010019870 - Noble, Wendell P.	2001-09-06
Negative resistance memory cell and method App 20010015907 - Noble, Wendell P.	2001-08-23
Base current reversal SRAM memory cell and method App 20010010376 - Noble, Wendell P.	2001-08-02
Memory cell with vertical transistor and buried word and body lines App 20010010957 - Forbes, Leonard ; et al.	2001-08-02
Method for coupling to semiconductor device in an integrated circuit having edge-defined, sub-lithographic conductors App 20010008784 - Noble, Wendell P.	2001-07-19
Construction and application for non-volatile reprogrammable switches Grant 6,256,225 - Noble , et al. July 3, 2	2001-07-03
Vertical gain cell and array for a dynamic random access memory Grant 6,246,083 - Noble June 12, 2	2001-06-12
Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Grant 6,245,615 - Noble , et al. June 12, 2	2001-06-12
Programmable logic array with vertical transistors App 20010002109 - Noble, Wendell P. ; et al.	2001-05-31
Programmable logic array with vertical transistors App 20010002108 - Noble, Wendell P. ; et al.	2001-05-31
Method for forming high density flash memory Grant 6,238,976 - Noble , et al. May 29, 2	2001-05-29
Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor App 20010001722 - Forbes, Leonard ; et al.	2001-05-24
Circuit and method for low voltage, voltage sense amplifier Grant 6,235,569 - Noble , et al. May 22, 2	2001-05-22
Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor App 20010000918 - Forbes, Leonard ; et al.	2001-05-10
Circuits and method for body contacted and backgated transistors Grant 6,229,342 - Noble , et al. May 8, 2	2001-05-08
Compact SOI body contact link App 20010000628 - Noble, Wendell P.	2001-05-03
Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/ drain region, and integrated App 20010000757 - Noble, Wendell P.	2001-05-03
Methods of forming ICS conductive lines, a conductive grid, a conductive network, an electrical interconnection to a node location, an electrical interconnection with a transistor source/drain region and ICS Grant 6,225,147 - Noble May 1, 2	2001-05-01
Structure and method for gated lateral bipolar transistors App 20010000245 - Forbes, Leonard ; et al.	2001-04-12
Dense SOI flash memory array structure Grant 6,215,145 - Noble April 10, 2	2001-04-10
Silicon-on-insulator islands and method for their formation Grant 6,211,039 - Noble April 3, 2	2001-04-03
Ultra high density flash memory having vertically stacked devices Grant 6,211,015 - Noble April 3, 2	2001-04-03
Negative resistance memory cell and method Grant 6,208,555 - Noble March 27, 2	2001-03-27
Programmable logic array with vertical transistors Grant 6,208,164 - Noble , et al. March 27, 2	2001-03-27
Silicon-on-insulator islands and method for their formation Grant 6,204,145 - Noble March 20, 2	2001-03-20
Method for coupling to semiconductor device in an integrated circuit having edge-defined, sub-lithographic conductors Grant 6,194,262 - Noble February 27, 2	2001-02-27
Dense SOI programmable logic array structure Grant 6,190,950 - Noble February 20, 2	2001-02-20
Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor Grant 6,165,836 - Forbes , et al. December 26, 2	2000-12-26
Method for a folded bit line memory using trench plate capacitor cells with body bias contacts Grant 6,156,607 - Noble , et al. December 5, 2	2000-12-05
Compact SOI body contact link Grant 6,156,589 - Noble December 5, 2	2000-12-05
Method for making an open bit line memory cell with a vertical transistor and trench plate trench capacitor Grant 6,156,604 - Forbes , et al. December 5, 2	2000-12-05
Method of forming a logic array for a decoder Grant 6,153,468 - Forbes , et al. November 28, 2	2000-11-28
High density flash memory Grant 6,143,636 - Forbes , et al. November 7, 2	2000-11-07
Memory address decode array with vertical transistors Grant 6,134,175 - Forbes , et al. October 17, 2	2000-10-17
Field programmable logic arrays with vertical transistors Grant 6,124,729 - Noble , et al. September 26, 2	2000-09-26
Circuit and method for low voltage, voltage sense amplifier Grant 6,104,066 - Noble , et al. August 15, 2	2000-08-15
Memory cell with vertical transistor and buried word and body lines Grant 6,104,061 - Forbes , et al. August 15, 2	2000-08-15
Circuits and methods for dual-gated transistors Grant 6,097,065 - Forbes , et al. August 1, 2	2000-08-01
Structure for gated lateral bipolar transistors Grant 6,075,272 - Forbes , et al. June 13, 2	2000-06-13
Four F.sup.2 folded bit line DRAM cell structure having buried bit and word lines Grant 6,072,209 - Noble , et al. June 6, 2	2000-06-06
Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor Grant 6,066,869 - Noble , et al. May 23, 2	2000-05-23
Circuit and method for low voltage, current sense amplifier Grant 6,049,496 - Forbes , et al. April 11, 2	2000-04-11
Dense SOI programmable logic array structure Grant 6,046,477 - Noble April 4, 2	2000-04-04
Programmable memory address decode array with vertical transistors Grant 5,991,225 - Forbes , et al. November 23, 1	1999-11-23
Semiconductor structure having an optical signal path in a substrate and method for forming the same Grant 5,987,196 - Noble November 16, 1	1999-11-16
Trench dram cell with vertical device and buried word lines Grant 5,977,579 - Noble November 2, 1	1999-11-02
Method for forming gate segments for an integrated circuit Grant 5,976,930 - Noble November 2, 1	1999-11-02
Ultra high density flash memory Grant 5,973,356 - Noble , et al. October 26, 1	1999-10-26
Ultra high density flash memory having vertically stacked devices Grant 5,973,352 - Noble October 26, 1	1999-10-26
High density flash memory Grant 5,936,274 - Forbes , et al. August 10, 1	1999-08-10
Circuit and method for a folded bit line memory using trench plate capacitor cells with body bias contacts Grant 5,914,511 - Noble , et al. June 22, 1	1999-06-22
Method of making memory cell with vertical transistor and buried word and body lines Grant 5,909,618 - Forbes , et al. June 1, 1	1999-06-01
Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor Grant 5,907,170 - Forbes , et al. May 25, 1	1999-05-25
On-chip thermometry for control of chip operating temperature Grant 5,873,053 - Pricer , et al. February 16, 1	1999-02-16
Trench EPROM Grant 5,598,367 - Noble January 28, 1	1997-01-28