U.S. patent application number 09/405091 was filed with the patent office on 2001-12-20 for trench dram cell with vertical device and buried word lines.
Invention is credited to NOBLE, WENDELL P..
Application Number | 20010053575 09/405091 |
Document ID | / |
Family ID | 22756512 |
Filed Date | 2001-12-20 |
United States Patent
Application |
20010053575 |
Kind Code |
A1 |
NOBLE, WENDELL P. |
December 20, 2001 |
TRENCH DRAM CELL WITH VERTICAL DEVICE AND BURIED WORD LINES
Abstract
A DRAM array having trench capacitor cells of potentially
4F.sup.2 surface area (F being the photolithographic minimum
feature width), and a process for fabricating such an array. The
array has a cross-point cell layout in which a memory cell is
located at the intersection of each bit line and each word line.
Each cell in the array has a vertical device such as a transistor,
with the source, drain, and channel regions of the transistor being
formed from epitaxially grown single crystal silicon. The vertical
transistor is formed above the trench capacitor.
Inventors: |
NOBLE, WENDELL P.; (MILTON,
VT) |
Correspondence
Address: |
DICKSTEIN SHAPIRO MORIN & OSHINSKY LLP
SUITE 400
2101 L STREET N W
WASHINGTON
DC
20037
|
Family ID: |
22756512 |
Appl. No.: |
09/405091 |
Filed: |
September 27, 1999 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09405091 |
Sep 27, 1999 |
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09204072 |
Dec 3, 1998 |
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5977579 |
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Current U.S.
Class: |
438/238 ;
257/E21.652; 257/E21.653; 438/243; 438/270 |
Current CPC
Class: |
H01L 27/10867 20130101;
H01L 27/10864 20130101 |
Class at
Publication: |
438/238 ;
438/243; 438/270 |
International
Class: |
H01L 021/8234 |
Claims
What is claimed as new and desired to be protected by Letters
Patent of the United States is:
1. An integrated circuit memory cell comprising: a substrate; a
trench capacitor formed in said substrate and having a conductive
area and a first insulating layer between the conductive area and
said substrate; a vertically stacked transistor having first,
second and third stacked conductivity regions formed over said
substrate, the second region being of a first conductivity type,
and the first and third regions being of a second conductivity
type, wherein the second region resides between said first and
third regions, said vertically stacked transistor having a first
vertical side and a second vertical side, wherein one of the
vertical sides of the first stacked conductivity region is in
contact with the conductive area of said trench capacitor; a second
insulating layer between the first stacked conductivity region and
said substrate; a third insulating layer positioned on one of the
vertical sides of the second stacked conductivity region; a word
line over said third insulating layer and positioned to form a gate
of said transistor; and a bit line in contact with said third
stacked conductivity region.
2. The memory cell of claim 1, wherein the cell is a dynamic random
access memory cell.
3. The memory cell of claim 1, further comprising a body line
positioned on the other vertical side of the second stacked
conductivity region from the third insulating layer.
4. The memory cell of claim 3, wherein the body line is a doped
polysilicon line.
5. The memory cell of claim 4, wherein the body line is doped to a
first conductivity type.
6. The memory cell of claim 1, wherein the first, second, and third
conductive regions are doped polysilicon regions.
7. The memory cell of claim 1, wherein the first conductivity type
is p-type, and the second conductivity type is n-type.
8. The memory cell of claim 1, wherein the first conductivity type
is p-type, and the second conductivity type is p-type.
9. The memory cell of claim 1, wherein the first insulating layer
is a layer of oxide.
10. The memory cell of claim 1, wherein the first insulating layer
is a layer of ON.
11. The memory cell of claim 1, wherein the first insulating layer
is a layer of ONO.
12. The memory cell of claim 1, wherein said trench capacitor is
formed in a trench on one of the vertical sides of said vertically
stacked transistor.
13. The memory cell of claim 12, wherein the conductive area of
said trench capacitor comprises a lower portion that extends across
the entire width of the trench, and an upper portion that connects
the lower portion to said vertically stacked transistor.
14. The memory cell of claim 12, wherein the trench is on the same
vertical side of said vertically stacked transistor as the word
line.
15. The memory cell of claim 12, wherein the trench is on a
different vertical side of said vertically stacked transistor as
the word line.
16. The memory cell of claim 1, wherein the word line is a doped
polysilicon line.
17. The memory cell of claim 16, wherein the word line is doped to
a second conductivity type.
18. The memory cell of claim 1, wherein the bit line is a doped
polysilicon line.
19. The memory cell of claim 18, wherein the bit line is doped to a
second conductivity type.
20. The memory cell of claim 1, wherein the memory cell has an area
of approximately 4F.sup.2 or less, where F is the minimum
lithographic feature size.
21. A DRAM cell comprising: a vertical transistor having a first
doped polysilicon region formed on a substrate, a second doped
polysilicon region formed on the first doped polysilicon region,
and a third doped polysilicon region formed on the second doped
polysilicon region; a trench capacitor located below said vertical
transistor in the substrate and having a doped polysilicon
electrode, wherein the electrode is in contact with the first doped
polysilicon region; an insulating layer located between said
vertical transistor and the substrate; a conductive line gating the
second doped polysilicon region; and a bit line in contact with the
third doped polysilicon region.
22. The DRAM cell of claim 21, wherein the substrate is doped to a
first conductivity type, and the polysilicon electrode is doped to
a second conductivity type.
23. The DRAM cell of claim 22, wherein the first and third doped
polysilicon regions are doped to a second conductivity type, and
the second doped polysilicon region is doped to a first
conductivity type.
24. The DRAM cell of claim 21, wherein the first doped polysilicon
region is the drain of said vertical transistor, the second doped
polysilicon region is part of the gate of said vertical transistor,
and the third doped polysilicon region is the source of said
vertical transistor.
25. The DRAM cell of claim 21, wherein said insulating layer is a
layer of silicon dioxide.
26. The DRAM cell of claim 21, further comprising a body line in
contact with the second doped polysilicon region.
27. The DRAM cell of claim 26, wherein the word line is doped to a
second conductivity type, and the body line is doped to a first
conductivity type.
28. The DRAM cell of claim 21, wherein the bit line is a doped
polysilicon line of a second conductivity type.
29. The DRAM cell of claim 21, wherein the cell has an area of
approximately 4F.sup.2 or less, where F is the minimum lithographic
feature size.
30. A DRAM cell comprising: a vertical transistor having a first
doped polysilicon region formed on a substrate, a second doped
polysilicon region formed on the first doped polysilicon region,
and a third doped polysilicon region formed on the second doped
polysilicon region, wherein the second doped polysilicon region is
of a first conductivity type, and the first and third doped
polysilicon regions are of a second conductivity type, wherein the
vertical transistor has a first and a second vertical sides; a
trench capacitor located in a trench in the substrate on the first
vertical side of said vertical transistor and having a doped
polysilicon electrode of a second conductivity type, wherein the
electrode is in contact with the first doped polysilicon region,
and having a dielectric layer between the electrode and the
substrate; a first insulating layer located between said vertical
transistor and the substrate; a body line of a first conductivity
type in contact with the second doped polysilicon region on the
first vertical side of said vertical transistor; a conductive line
of a second conductivity type gating the second doped polysilicon
region on the second vertical side of said vertical transistor,
wherein a second insulating layer lies between the conductive line
and the second doped polysilicon region; and a bit line of a second
conductivity type in contact with the third doped polysilicon
region.
31. A semiconductor memory array comprising: a substrate; a
plurality of memory cells arranged into an array of rows and
columns, wherein each memory cell comprises a trench capacitor
located in the substrate and a vertical transistor having first,
second and third regions located above the trench capacitor,
wherein the first region of the vertical transistor adjoins the
trench capacitor, each memory cell having an area of 4F.sup.2 where
F is the minimum lithographic feature size; a plurality of bit
lines, wherein each bit line is in contact with the third region of
each vertical transistor in a respective row; and a plurality of
buried word lines, wherein each word line adjoins the second region
of each vertical transistor in a respective column, and is
separated from the second region by an insulating layer.
32. The memory array of claim 31, wherein the substrate is a
silicon substrate.
33. The memory array of claim 32, wherein the substrate is doped to
a first conductivity type.
34. The memory array of claim 33, wherein the trench capacitor of
each memory cell is located in a trench on one side of the vertical
transistor.
35. The memory array of claim 34, wherein the trench capacitor
further comprises a doped polysilicon electrode of a second
conductivity type having a lower portion that extends across the
entire width of the trench, and an upper portion that connects the
lower portion to the vertical transistor.
36. The memory array of claim 35, wherein the trench capacitor
further comprises a dielectric layer located between the lower
portion of the electrode and the walls and bottom of the
trench.
37. The memory array of claim 36, wherein the dielectric layer is a
layer of material selected from the group consisting of oxide, ON,
and ONO.
38. The memory array of claim 31, wherein the trench capacitor has
an area of approximately 1F.sup.2, where F is the minimum
lithographic feature size.
39. The memory array of claim 31, wherein the vertical transistor
has an area of approximately 1F.sup.2, where F is the minimum
lithographic feature size.
40. The memory array of claim 31, wherein the first, second and
third regions of the vertical transistor are doped polysilicon
regions, wherein the first and the third regions are doped to a
second conductivity type, and the second region is doped to a first
conductivity type.
41. The memory array of claim 40, wherein the plurality of bit
lines are doped polysilicon lines of a second conductivity type,
and the plurality of buried word lines are doped polysilicon lines
of a second conductivity type.
42. The memory array of claim 31, further comprising a plurality of
buried body lines, wherein each body line is in contact with the
second region of each vertical transistor in a respective
column.
43. A method of forming a memory cell, comprising the steps of:
providing a semiconductor substrate; providing a vertical
transistor on the substrate, wherein the vertical transistor has
first, second, and third conductive regions; providing a trench
capacitor in a trench on one side of the vertical transistor and in
connection with the first conductive region of the vertical
transistor; forming a word line gating the second conductive region
of the vertical transistor; and forming a bit line in connection
with the third conductive region of the vertical transistor.
44. The method of claim 43, wherein said step of providing the
vertical transistor comprises forming the first, second, and third
conductive regions and then patterning the first, second, and third
conductive regions to form the vertical transistor.
45. The method of claim 44, wherein said step of forming the first,
second, and third conductive regions comprises successive epitaxial
deposition of the first, second, and third conductive regions on
the substrate.
46. The method of claim 43, wherein the substrate is a silicon
substrate.
47. The method of claim 46, wherein the first, second, and third
conductive regions are doped polysilicon regions.
48. The method of claim 43, wherein the substrate is doped to a
first conductivity type, the first and third conductive regions are
doped to a second conductivity type, the second conductive region
is doped to a first conductivity type, and the electrode of the
trench capacitor is doped to a second conductivity type.
49. The method of claim 48, wherein the first conductivity type is
p-type, and the second conductivity type is n-type.
50. The method of claim 48, wherein the first conductivity type is
n-type, and the second conductivity type is p-type.
51. The method of claim 48, wherein the word line and the bit line
are doped to a second conductivity type.
52. The method of claim 43, further comprising forming a body
connector in connection with the second conductive region of the
vertical transistor.
53. A method of forming a memory cell array, comprising the steps
of: providing a substrate; providing a plurality of memory cells
arranged into an array of rows and columns, wherein each memory
cell comprises a trench capacitor located in the substrate and a
vertical transistor having first, second and third regions located
above the trench capacitor, each memory cell having an area of
4F.sup.2 where F is the minimum lithographic feature size;
providing a plurality of bit lines, wherein each bit line is in
contact with the third region of each vertical transistor in a
respective row; and providing a plurality of buried word lines,
wherein each word line gates the second region of each vertical
transistor in a respective column.
54. The method of claim 53, wherein said step of providing the
plurality of memory cells comprises forming an array of vertical
transistors on the substrate and forming an array of trench
capacitors in said substrate.
55. The method of claim 54, wherein said step of forming an array
of vertical transistors comprises forming first, second, and third
device layers on the substrate, defining a first set of trenches in
the device layers and the substrate, and defining a second set of
trenches in the device layers and the substrate, wherein the second
set of trenches is orthogonal to the first set of trenches.
56. The method of claim 55, wherein said step of forming first,
second, and third device layers comprises successive epitaxial
growth of the first device layer on the substrate, the second
device layer on the first device layer, and the third device layer
on the second device layer.
57. The method of claim 56, wherein said epitaxial growth steps
comprise vapor phase epitaxy.
58. The method of claim 56, wherein said epitaxial growth steps
comprise liquid phase epitaxy.
59. The method of claim 56, further comprising forming a pad layer
on top of the third device layer prior to said step of defining a
first set of trenches.
60. The method of claim 59, wherein said pad layer formation step
comprises forming an oxide pad layer on the third device layer and
forming a nitride pad layer on the oxide pad layer.
61. The method of claim 55, wherein said step of defining a first
set of trenches comprises photolithography and directional etching
through the device layers and the substrate.
62. The method of claim 61, wherein said directional etching step
comprises plasma etching.
63. The method of claim 61, wherein said directional etching step
comprises RIE.
64. The method of claim 55, further comprising a step of filling
the first set of trenches with oxide.
65. The method of claim 64, further comprising planarizing the
array and forming a nitride pad layer on the surface of the
array.
66. The method of claim 55, wherein said step of defining a second
set of trenches comprises photolithography and directional etching
through the device layers and the substrate to form an array of
vertical transistors.
67. The method of claim 66, further comprising forming an isolation
layer under the array of vertical transistors.
68. The method of claim 67, wherein said isolation layer forming
step comprises forming a nitride film on the sides of the second
set of trenches, deepening the second set of trenches, and thermal
oxidation of the substrate.
69. The method of claim 55, wherein said step of forming an array
of trench capacitors comprises forming the capacitors in the second
set of trenches below the level of the vertical transistors.
70. The method of claim 69, wherein said step of forming the
capacitors comprises formation of a dielectric layer on the walls
and bottom of the second set of trenches, and formation of an
electrode layer in the second set of trenches.
71. The method of claim 70, wherein the electrode layer is formed
by CVD.
72. The method of claim 70, wherein said step of providing a
plurality of buried word lines comprises forming a third set of
trenches in the electrode layer, forming an insulating layer on one
side of the vertical transistors above the third set of trenches,
and depositing conductive lines on the insulating layer.
73. The method of claim 72, wherein the conductive lines are doped
polysilicon lines of a second conductivity type.
74. The method of claim 55, further comprising providing a
plurality of buried body lines, wherein each body line is in
contact with the second region of each vertical transistor in a
respective column.
75. The method of claim 74, wherein said step of providing a
plurality of buried body lines comprises deposition of conductive
lines on one side of the vertical transistors in the second set of
trenches.
76. The method of claim 75, wherein the conductive lines are doped
polysilicon lines of a first conductivity type.
77. The method of claim 53, wherein said step of providing a
plurality of bit lines comprises, for each row in the array of rows
and columns, deposition of a conductive line on top of each
transistor in a respective row.
78. The method of claim 77, wherein said deposition step comprises
CVD.
79. The method of claim 77, wherein the conductive line is doped
polysilicon of a second conductivity type.
80. A method of forming a DRAM array, comprising the steps of:
providing a silicon substrate; forming a stack of device layers on
the substrate by epitaxial growth; patterning the stack of device
layers to form a first set of trenches in the substrate and a
second set of trenches in the substrate orthogonal to the first set
of trenches, wherein said first and second sets of trenches define
an array of device islands on the substrate, wherein each device
island has an area of approximately 4F.sup.2, where F is the
minimum lithographic feature size; forming an isolation layer
between the device islands and the substrate by thermal oxidation
of the substrate; forming trench capacitors in the substrate in the
second set of trenches below the level of the device islands;
forming word lines abutting the device islands in the second set of
trenches above the trench capacitors; and forming bit lines on top
of the device islands.
81. The method of claim 80, wherein said step of patterning the
device layer comprises photolithography and directional etching
through the device layer and into the substrate.
82. The method of claim 80, wherein said step of forming trench
capacitors comprises forming a dielectric layer on the walls and
bottom of the second set of trenches, and forming an electrode
layer in the second set of trenches.
83. The method of claim 82, wherein said step of forming an
electrode layer comprises deposition of the electrode layer and
formation of a first oxide layer on top of the electrode layer.
84. The method of claim 80, further comprising forming body lines
in contact with the device islands in the second set of
trenches.
85. The method of claim 84, wherein said step of forming body lines
comprises deposition of conductive lines on the walls of the device
islands in the second set of trenches and formation of an
insulating conformal film over the conductive lines.
86. The method of claim 85, wherein the insulating conformal film
is a nitride film.
87. The method of claim 80, wherein said step of forming word lines
comprises deposition of a gate oxide layer on the walls of the
device islands in the second set of trenches, and deposition of
conductive lines on the gate oxide layer.
88. A method of forming a DRAM array, comprising the steps of:
providing a silicon substrate of a first conductivity type; forming
a first polysilicon layer of a second conductivity type on the
substrate; forming a second polysilicon layer of a first
conductivity type on the first polysilicon layer; forming a third
polysilicon layer of a second conductivity type on the second
polysilicon layer; defining a first set of trenches in the
substrate and extending through the first, second, and third
polysilicon layers; filling the first set of trenches with oxide;
defining a second set of trenches in the substrate which extend
through the first, second, and third polysilicon layers in a
direction orthogonal to the first set of trenches to form vertical
transistors having a first and a second vertical side, wherein each
vertical transistor has an area of approximately 4F.sup.2, where F
is the minimum lithographic feature size; forming an isolation
layer between the vertical transistors and the substrate by thermal
oxidation of the substrate; forming trench capacitors in the second
set of trenches by deposition of a dielectric layer in the second
set of trenches and deposition of a polysilicon electrode layer of
a second conductivity type in the second set of trenches; forming
polysilicon body lines of a first conductivity type in contact with
one of the vertical sides of the second polysilicon layer of the
vertical transistors in the second set of trenches; forming
polysilicon word lines of a second conductivity type abutting the
other vertical side of the second polysilicon layer of the vertical
transistors in the second set of trenches; and forming bit lines of
a second conductivity type on top of the third polysilicon layer of
the vertical transistors.
89. The method of claim 88, wherein said steps of forming the
first, second and third polysilicon layers comprise epitaxial
deposition.
90. The method of claim 88, wherein the first and second sets of
trenches are defined by photolithography and subsequent anisotropic
etching.
91. The method of claim 90, wherein said step of anisotropic
etching comprises plasma etching.
92. The method of claim 90, wherein said step of anisotropic
etching comprises RIE.
93. The method of claim 88, wherein said step of forming
polysilicon body lines comprises deposition of polysilicon lines on
the first and second vertical sides of the second polysilicon layer
of the vertical transistors formation of a conformal film over the
polysilicon lines, and removal of the polysilicon lines from one of
the vertical sides of the vertical transistors.
94. The method of claim 88, wherein said step of forming
polysilicon word lines comprises deposition of a gate oxide layer
on one of the vertical sides of the second polysilicon layer of the
vertical transistors, and deposition of polysilicon lines on the
gate oxide layer.
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to an improved
semiconductor structure for high density device arrays, and in
particular to a trench DRAM cell array, and to a process for its
formation.
BACKGROUND OF THE INVENTION
[0002] There are two major types of random-access memory cells,
dynamic and static. Dynamic random-access memories (DRAMs) can be
programmed to store a voltage which represents one of two binary
values, but require periodic reprogramming or "refreshing" to
maintain this voltage for more than very short time periods. Static
random-access memories are so named because they do not require
periodic refreshing.
[0003] DRAM memory circuits are manufactured by replicating
millions of identical circuit elements, known as DRAM cells, on a
single semiconductor wafer. Each DRAM cell is an addressable
location that can store one bit (binary digit) of data. In its most
common form, a DRAM cell consists of two circuit components: a
field effect transistor (FET) and a capacitor.
[0004] FIG. 1 illustrates a portion of a DRAM memory circuit
containing two neighboring DRAM cells 42. For each cell, the
capacitor 44 has two connections, located on opposite sides of the
capacitor 44. The first connection is to a reference voltage, which
is typically one half of the internal operating voltage (the
voltage corresponding to a logical "1" signal) of the circuit. The
second connection is to the drain of the FET 46. The gate of the
FET 46 is connected to the word line 48, and the source of the FET
is connected to the bit line 50. This connection enables the word
line 48 to control access to the capacitor 44 by allowing or
preventing a signal (a logic "0" or a logic "1") on the bit line 50
to be written to or read from the capacitor 44.
[0005] The body of the FET 46 is connected to the body line 76,
which is used to apply a fixed potential to the body. Body lines
are used to avoid floating body threshold voltage instabilities
that occur when FETs are used on silicon-on-insulator (SOI)
substrates. These threshold voltage instabilities occur because the
body of the FET does not have a fixed potential. Threshold voltage
is a function of the potential difference between the source and
the body of a FET, so if the body does not have a fixed potential,
then the threshold voltage will be unstable. Because control of the
threshold voltage is especially critical in DRAM cells, a body line
may be used to provide the body of the FET with a fixed potential
so that the threshold voltage of the FET may thereby be
stabilized.
[0006] The manufacturing of a DRAM cell includes the fabrication of
a transistor, a capacitor, and three contacts: one each to the bit
line, the word line, and the reference voltage. DRAM manufacturing
is a highly competitive business. There is continuous pressure to
decrease the size of individual cells and to increase memory cell
density to allow more memory to be squeezed onto a single memory
chip, especially for densities greater than 256 Megabits.
Limitations on cell size reduction include the passage of both
active and passive word lines through the cell, the size of the
cell capacitor, and the compatibility of array devices with
non-array devices.
[0007] Conventional folded bit line cells of the 256 Mbit
generation with planar devices have a size of at least 8F.sup.2,
where F is the minimum lithographic feature size. If a folded bit
line is not used, the cell may be reduced to 6 or 7 F.sup.2. To
achieve a smaller size, vertical devices must be used. Cell sizes
of 4F.sup.2 may be achieved by using vertical transistors stacked
either below or above the cell capacitors, as in the "cross-point
cell" of W. F. Richardson et al., "A Trench Transistor Cross-Point
DRAM Cell," IEDM Technical Digest, pp. 714-17 (1985). Known
cross-point cells, which have a memory cell located at the
intersection of each bit line and each word line, are expensive and
difficult to fabricate because the structure of the array devices
is typically incompatible with that of non-array devices. Other
known vertical cell DRAMs using stacked capacitors have integration
problems due to the extreme topography of the capacitors.
[0008] There is needed, therefore, a DRAM cell having an area of
4F.sup.2 or smaller that achieves high array density while
maintaining structural commonality between array and peripheral
(non-array) features. Also needed is a simple method of fabricating
a trench DRAM cell that maximizes common process steps during the
formation of array and peripheral devices.
SUMMARY OF THE INVENTION
[0009] The present invention provides a DRAM cell array having a
cell area of 4F.sup.2 or smaller which comprises an array of
vertical transistors located over an array of trench capacitors.
The trench capacitor for each cell is located beneath and to one
side of the vertical transistor, thereby decreasing the cell area
while maintaining compatibility of the vertical transistors with
peripheral devices. Also provided is a simplified process for
fabricating the DRAM cell array which may share common process
steps with peripheral device formation so as to minimize the
fabrication cost of the array.
[0010] Additional advantages and features of the present invention
will be apparent from the following detailed description and
drawings which illustrate preferred embodiments of the
invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a schematic illustration of a known DRAM cell.
[0012] FIG. 2 is a perspective view of the memory array of the
present invention.
[0013] FIG. 3 is a cross-sectional view of a semiconductor wafer
undergoing the process of a preferred embodiment.
[0014] FIG. 4 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 3.
[0015] FIG. 5 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 4.
[0016] FIG. 6 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 5.
[0017] FIG. 7 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 6.
[0018] FIG. 8 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 7.
[0019] FIG. 9 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 8.
[0020] FIG. 10 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 9.
[0021] FIG. 11 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 10.
[0022] FIG. 12 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 11.
[0023] FIG. 13 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 12.
[0024] FIG. 14 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 13.
[0025] FIG. 15 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 14.
[0026] FIG. 16 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 15.
[0027] FIG. 17 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 16.
[0028] FIG. 18 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 17.
[0029] FIG. 19 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 18.
[0030] FIG. 20 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 19.
[0031] FIG. 21 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 20.
[0032] FIG. 22 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 21.
[0033] FIG. 23 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 22.
[0034] FIG. 24 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 23.
[0035] FIG. 25 shows the wafer of FIG. 3 at a processing step
subsequent to that shown in FIG. 24.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0036] In the following detailed description, reference is made to
the accompanying drawings which form a part hereof, and in which is
shown by way of illustration specific embodiments in which the
invention may be practiced. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention, and it is to be understood that other embodiments
may be utilized, and that structural, logical and electrical
changes may be made without departing from the spirit and scope of
the present invention.
[0037] The terms "wafer" and "substrate" are to be understood as
including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS)
technology, doped and undoped semiconductors, epitaxial layers of
silicon supported by a base semiconductor foundation, and other
semiconductor structures. Furthermore, when reference is made to a
"wafer" or "substrate" in the following description, previous
process steps may have been utilized to form regions or junctions
in the base semiconductor structure or foundation. In addition, the
semiconductor need not be silicon-based, but could be based on
silicon-germanium, germanium, or gallium arsenide. The following
detailed description is, therefore, not to be taken in a limiting
sense, and the scope of the present invention is defined by the
appended claims.
[0038] Referring now to the drawings, where like elements are
designated by like reference numerals, an embodiment of the device
array 40 of the present invention is shown in FIG. 2. The device
array 40 is comprised of a plurality of trench DRAM cells 42 formed
on a substrate 60, where the DRAM cells 42 are separated from each
other by oxide isolation layers 62. Each DRAM cell 42 comprises two
devices, a vertical transistor 46, and a trench capacitor 44
located beneath the transistor 46.
[0039] The transistor 46 forms a vertical stack of three doped
polysilicon layers resting on top of the isolation layer 62. An
exemplary n-channel device, as illustrated in FIG. 2, would be
formed using a substrate 60 of a first conductivity type, e.g., p+,
a drain 70 of a second conductivity type (n+), a lightly-doped body
region 72 of a first conductivity type (p-), and a source 74 of a
second conductivity type (n+). If a p-channel device were desired,
the doping types and levels of these elements would be adjusted as
is known in the art. The capacitor 44 comprises a polysilicon
electrode 80, which for exemplary purposes is of a second
conductivity type (n+), and a dielectric 82, which may be any
suitable dielectric material such as oxide, ON (oxide-nitride), or
ONO (oxide-nitride-oxide). The region of the substrate 60
underlying the electrode 80 acts as a capacitor plate.
[0040] The transistor 46 is a MOSFET (metal-oxide-semiconductor
FET) device having four contacts to other portions of the cell 42
or array 40. First, the drain 70 of the transistor 46 is in contact
with the capacitor electrode 80. Second, a conductive bit line 50
formed of polysilicon doped to a second conductivity type (n+) is
formed so that it contacts the source 74 of each transistor 46 of a
particular row in the array 40. Third, an active word line 48 of a
conductive material such as doped polysilicon of a second
conductivity type (n+) is formed to act as the gate of each
transistor 46, and to electrically connect all of the cells 42 of a
given column in the array 40. A thin oxide layer 132 is present
between the word line 48 and the body 72 of each transistor 46.
Fourth, a body line 76 of a conductive material such as doped
polysilicon of a first conductivity type (p+) is formed to contact
the body 72 of each transistor 46 in a given column. The presence
of the body line 76 serves to avoid floating body threshold voltage
instabilities.
[0041] The device array 40 is manufactured through a process
described as following, and illustrated by FIGS. 3 through 25. For
exemplary purposes, dimensions are suggested which are suitable for
0.2 micron critical dimension technology, and it should be
understood that dimensions should be scaled accordingly for other
critical dimension sizes. First, a substrate 60, which may be any
of the types of substrate described above, is selected as the base
for the device array 40. For exemplary purposes, the substrate 60
will be described as a silicon substrate, and the following process
should be modified as appropriate and as known in the art if a
non-silicon substrate is used. The substrate 60 may be doped or
undoped, but a p+ type doped wafer is preferred. If PMOS devices
are to be formed, photolithography is used to define areas where
n-wells (not shown) are implanted. The level of doping in the
n-wells may vary but should be of comparable or greater strength
than the doping level of the substrate 60.
[0042] As shown in FIG. 3, the first step in the process is to form
the device layers 100, 102, 104. The device layers 100, 102, 104
are formed of doped epitaxial polysilicon by known methods of
epitaxial growth, such as vapor phase, liquid phase, or solid phase
epitaxy. If a silicon substrate 60 is used, then vapor phase
epitaxy is preferred, and if a Group III-V compound substrate,
e.g., gallium arsenide or indium phosphate, is used, liquid phase
epitaxy is preferred. For the formation of the device array 40 of
the present embodiment, the first device layer 100 should be a
doped polysilicon layer of a second conductivity type (n+)
approximately 0.4 microns thick, the second device layer 102 should
be a lightly-doped polysilicon layer of a first conductivity type
(p-) approximately 0.35 microns thick, and the third device layer
104 should be a doped polysilicon layer of a second conductivity
type (n+) approximately 0.2 microns thick.
[0043] Next, as shown in FIG. 4, an oxide pad 106 approximately 10
nm thick, and a first nitride pad 108 approximately 100 nm thick
are formed on top of the third device layer 104 by chemical vapor
deposition (CVD) or other suitable means. A photoresist and mask
are then applied over the first nitride pad 108, and
photolithographic techniques are used to define a set of parallel
rows on the array surface. A directional etching process such as
plasma etching or reactive ion etching (RIE) is used to etch
through the pad layers 106, 108 and the device layers 100, 102, 104
and into the substrate 60 to form a first set of trenches 110, as
depicted in FIG. 5. The trenches 110 should be approximately 1.05
microns deep.
[0044] After removal of the resist, the first set of trenches 110
is filled with silicon oxide by CVD or other suitable process to
form a first set of silicon oxide bars 112, as shown in FIG. 6. The
device array 40 is then planarized by any suitable means, such as
chemical-mechanical polishing (CMP), stopping on the first nitride
pad 108. A second nitride pad 114 is then deposited, preferably by
CVD, to a thickness of about 60 to 100 nm. The device array 40 now
appears as shown in FIG. 6.
[0045] FIG. 7 illustrates the next step in the process, in which a
resist and mask (not shown) are applied, and photolithography is
used to define a second set of trenches 116 orthogonal to the first
set of silicon oxide bars 112. The nitride pads 108, 114, the oxide
pad 106, and the device layers 100, 102, 104 are etched out by a
directional etching process such as RIE to define the second set of
trenches 116. Etching is continued down to the level of the
substrate 60, and the second set of trenches 116 should be
approximately 0.95 microns deep. The resist is then removed. As can
be seen, the second set of trenches 116 is defined by a set of
device islands 118, which will be transformed into individual DRAM
cells by the fabrication process described herein.
[0046] As shown in FIG. 8, a first nitride film 120 is now formed
on the sides of the second set of trenches 116 by depositing a
layer of CVD nitride and directionally etching to remove excess
nitride from horizontal surfaces. The first nitride film 120, which
is about 10 nm thick, acts as an oxidation and etching barrier
during subsequent steps of the fabrication process. Anisotropic
etching such as RIE is then performed to deepen the second set of
trenches 116 an additional 0.1 microns, resulting in the structure
shown in FIG. 9.
[0047] Thermal oxidation is then performed to create an isolation
layer 62 under and between the device islands 118, as depicted by
FIG. 10. The substrate 60 is thermally oxidized by a suitable
process as known in the art, such as by heating the wafer in a
standard silicon processing furnace at a temperature of
approximately 900 to 1100 degrees Celsius in a wet ambient. The
oxidation time is selected to produce an isolation layer 62
approximately 0.1 microns thick under the device islands 118.
[0048] FIG. 11 shows the next step in the process, in which an
anisotropic etch such as RIE is performed to deepen the second set
of trenches 116 through the isolation layer 62 and into the
substrate 60 to the depth desired for the trench capacitors. When
the desired depth has been achieved, the first nitride film 120 is
stripped from the sides of the device islands 118, preferably by
isotropic etching with a nitride etchant such as phosphoric
acid.
[0049] As illustrated in FIG. 12, a capacitor dielectric layer 82
is now formed inside the second set of trenches 116 on the on the
sides of the device islands 118 and the bottom of the trenches 116.
The dielectric layer 82 may be oxide, ON, or ONO, and is preferably
formed by CVD and/or thermal oxidation. Next, the second set of
trenches 116 are filled with a polysilicon layer 80 of a second
conductivity type (n+) by CVD or other suitable means, as shown in
FIG. 13.
[0050] The polysilicon layer 120 is then etched back to a level
approximately 1 micron below the second nitride pad 114, as shown
in FIG. 14. The exposed capacitor dielectric 82 is then removed by
isotropic etching. The second set of trenches 116 are then
re-filled with polysilicon of a second conductivity type (n+) by
CVD. The polysilicon is then etched back to a level approximately
0.55 microns below the second nitride pad 114 to form a capacitor
electrode 80, depicted in FIG. 15.
[0051] FIG. 16 illustrates the next step of the process in which a
second nitride film 122 is formed on the sides of the second set of
trenches 116. The film 122, which is about 10 nm thick, is formed
by depositing a layer of CVD nitride and directionally etching to
remove excess nitride from horizontal surfaces. The second nitride
film 122 acts as an oxidation barrier during the next step of the
process.
[0052] Thermal oxidation of the capacitor electrode 80 is now
performed by methods known in the art to create a first oxide layer
124 approximately 100 nm thick on top of the electrode 80 in the
second set of trenches 116. The second nitride film 122 is then
stripped from the sides of the device islands 118, preferably by
isotropic etching with a nitride etchant such as phosphoric acid,
to form the structure shown in FIG. 17.
[0053] FIG. 18 depicts the following step of the process where
polysilicon of a first conductivity type (p+) is deposited by CVD
or other suitable means in the second set of trenches 116 to a
thickness of approximately 70 nm. A directional etch such as RIE is
performed so that no polysilicon remains on the horizontal surfaces
of the array 40, and the etch is continued to recess the top of the
polysilicon to at least 0.2 microns below the bottom of the oxide
pad 106. The resultant first and second body lines 76, 78 are shown
in FIG. 18. A conformal film 126 of nitride or other suitable
material is now formed over the first and second body lines 76, 78,
as shown in FIG. 19. The conformal film 126 is approximately 10 nm
thick, and is formed by CVD or other suitable methods.
[0054] As illustrated in FIG. 20, a photoresist and mask are
applied, and photolithography is used to define a third set of
trenches 128 inside the second set of trenches 116. The exposed
conformal film 126 is etched off by an isotropic etch, and then a
directional etch is performed to remove the second body line 78.
Directional etching is continued to remove the exposed first oxide
layer 124 and the exposed electrode 80 to a depth below the first
device layer 100.
[0055] The resist is stripped, and the third set of trenches is
filled with silicon oxide by CVD or known methods, as shown in FIG.
21. If desired, the device array 40 may be planarized by CMP or
other means at this point. The silicon oxide is then etched back to
form a second oxide layer 130 at a level approximately 0.6 to 0.7
microns below the level of the oxide pad 106.
[0056] FIG. 22 depicts the next step, in which a thin gate oxide
layer 132 is formed by thermal oxidation of the exposed side of the
device islands 118. Next, polysilicon of a second conductivity type
(n+) is deposited by CVD or other suitable means in the third set
of trenches 128 to a thickness of approximately 70 nm. A
directional etch such as RIE is performed so that no polysilicon
remains on the horizontal surfaces of the array 40. A resist and
mask (not shown) are then applied, and a selective etch is
performed to remove excess polysilicon on the body line 76 side of
the third set of trenches 128. The resultant word line 48 is shown
in FIG. 22.
[0057] The resist is stripped, and the third set of trenches 128
are filled with silicon oxide by CVD or other suitable means to
form a second set of silicon oxide bars 134, as shown in FIG. 23.
The device array 40 is then planarized by any suitable means, such
as CMP, stopping on the second nitride pad 114. FIG. 24 illustrates
the next step in the process, in which a dip etch is performed to
remove the nitride pads 108, 114 and the oxide pad 106 from the
device islands 118.
[0058] As shown in FIG. 25, the next step is to form a conductive
bit line 50 over the device array 40 so that it contacts the source
74 of each transistor 46 of a particular row in the array 40. The
bit line 50 is formed of doped polysilicon of a second conductivity
type (n+), and is deposited by means such as CVD. After deposition,
the polysilicon is patterned by photolithography and subsequent
etching to form a bit line 50 as shown in FIG. 25 and in FIG. 2.
Conventional processing methods may then be used to form contacts
and wiring to connect the device array to peripheral circuits, and
to form other connections. For example, the entire surface may then
be covered with a passivation layer of, e.g., silicon dioxide, BSG,
PSG, or BPSG, which is CMP planarized and etched to provide contact
holes which may then be metallized. Conventional multiple layers of
conductors and insulators may also be used to interconnect the
structures.
[0059] As can be seen by the embodiments described herein, the
present invention encompasses a trench DRAM cell having an area of
4F.sup.2 or smaller that comprises a vertical transistor located
over a trench capacitor. As may be readily appreciated by persons
skilled in the art, decreasing the size of the DRAM cell while
maintaining common process steps with peripheral devices decreases
fabrication costs while increasing array density. As a result, a
high density and high performance array is produced by a simplified
fabrication process.
[0060] The above description and drawings illustrate preferred
embodiments which achieve the objects, features and advantages of
the present invention. It is not intended that the present
invention be limited to the illustrated embodiments. Any
modification of the present invention which comes within the spirit
and scope of the following claims should be considered part of the
present invention.
* * * * *