U.S. patent application number 10/353506 was filed with the patent office on 2004-07-29 for forming semiconductor structures.
Invention is credited to Chen, Tian-An, Goodner, Michael D., Liou, Huey-Chiang, Meagley, Robert P., O'Brien, Kevin P., Powers, James.
Application Number | 20040145030 10/353506 |
Document ID | / |
Family ID | 32736188 |
Filed Date | 2004-07-29 |
United States Patent
Application |
20040145030 |
Kind Code |
A1 |
Meagley, Robert P. ; et
al. |
July 29, 2004 |
Forming semiconductor structures
Abstract
A semiconductor structure may be covered with a thermally
decomposing film. That film may then be covered by a sealing cover.
Subsequently, the thermally decomposing material may be decomposed,
forming a cavity.
Inventors: |
Meagley, Robert P.;
(Beaverton, OR) ; O'Brien, Kevin P.; (Portland,
OR) ; Chen, Tian-An; (Phoenix, AZ) ; Goodner,
Michael D.; (Hillsboro, OR) ; Powers, James;
(Aloha, OR) ; Liou, Huey-Chiang; (Fremont,
CA) |
Correspondence
Address: |
Timothy N. Trop
TROP, PRUNER & HU, P.C.
STE 100
8554 KATY FWY
HOUSTON
TX
77024-1841
US
|
Family ID: |
32736188 |
Appl. No.: |
10/353506 |
Filed: |
January 28, 2003 |
Current U.S.
Class: |
257/642 ;
257/E21.259; 257/E21.546; 257/E21.576; 257/E21.581; 257/E23.144;
438/725; 438/781 |
Current CPC
Class: |
H01L 21/76224 20130101;
H01L 23/5222 20130101; H01L 21/76829 20130101; H01L 21/02134
20130101; H01L 21/02118 20130101; H01L 21/0234 20130101; H01L
2924/0002 20130101; H01L 21/76828 20130101; H01L 21/76825 20130101;
H01L 21/02164 20130101; H01L 21/7682 20130101; H01L 21/02351
20130101; H01L 21/76826 20130101; H01L 21/312 20130101; H01L
21/02137 20130101; H01L 2924/0002 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
257/642 ;
438/725; 438/781 |
International
Class: |
H01L 023/58; H01L
021/302; H01L 021/31 |
Claims
What is claimed is:
1. A method comprising: covering a semiconductor structure with a
thermally decomposing layer selected from the group consisting of
polypropylene oxide, polymethylstyrene, polycaprolactone,
polycarbonate, polyamideimide, polyamide-6,6, polyphthalamide,
polyetherketone, polyethretherketone, polybutyllene terephthalate,
polyethyllene terephthalate, polystyrene, syndiotactic-polystyrene,
polyphenylene sulfide, and polyether sulfone; forming a cover over
said thermally decomposing layer; and thermally decomposing the
thermally decomposing layer underneath said cover.
2. The method of claim 1 wherein thermally decomposing includes
causing the thermally decomposing layer to pass through said
cover.
3. The method of claim 1 including allowing the thermally
decomposing material to escape through said cover and thereafter
sealing said cover.
4. The method of claim 1 including providing a thermally
decomposing layer that does not decompose at temperatures below
260.degree. C.
5. A semiconductor structure comprising: a semiconductor support; a
thermally decomposing layer formed over said support, said layer
consisting of a polymer selected from the group composed of
polypropylene oxide, polymethyl-styrene, polycaprolactone,
polycarbonate, polyamideimide, polyamide-6,6, polyphthalamide,
polyetherketone, polyethretherketone, polybutyllene terephthalate,
polyethyllene terephthalate, polystyrene, syndiotactic-polystyrene,
polyphenylene sulfide, and polyether sulfone; and a cover over said
thermally decomposing layer.
6. The structure of claim 5 wherein said structure is a
semiconductor wafer.
7. The structure of claim 5 wherein said thermally decomposing
layer is formed of a material that decomposes at a temperature
above 260.degree. C.
8. The structure of claim 5 wherein said cover includes
Silsesquioxane.
9. A method comprising: treating a semiconductor substrate to match
the surface energy of a sacrificial material; and forming said
sacrificial material over said substrate.
10. The method of claim 9 including treating the substrate to make
the substrate more hydrophobic.
11. The method of claim 10 including treating the substrate to
match the surface energy of a polymer, thermally decomposing
film.
12. The method of claim 9 including treating the substrate with
hexamethyldisilazane saturated nitrogen.
13. A semiconductor structure comprising: a substrate; a coating on
a substrate; and a decomposing layer formed on said substrate, said
layer to match the surface energies of said substrate and said
decomposing layer.
14. The structure of claim 13 wherein said decomposing layer
includes a polymer.
15. The structure of claim 13 wherein said layer includes
hexamethyldisilazane.
16. The structure of claim 13 wherein said decomposing layer is a
decomposing layer that only decomposes at a temperature above
260.degree. C.
17. A method comprising: covering a semiconductor structure with a
thermally decomposing layer; forming a cover over said thermally
decomposing layer including spin-on glass; and thermally
decomposing the thermally decomposing layer underneath said
cover.
18. The method of claim 17 including using a silsesquioxane to form
said cover.
19. The method of claim 18 including using hydrogen
silsesquioxane.
20. The method of claim 18 including using
methylsilsesquioxane.
21. The method of claim 17 including covering said spin-on glass
with a layer of oxide.
22. A semiconductor structure comprising: a semiconductor layer; a
thermally decomposing layer formed over said layer; and a cover
over said thermally decomposing layer, said cover including a
silsesquioxane.
23. The structure of claim 22 wherein said cover includes hydrogen
silsesquioxane.
24. The structure of claim 22 wherein said cover includes
methylsilsesquioxane.
25. The structure of claim 22 including an oxide layer formed over
said silsesquioxane.
Description
BACKGROUND
[0001] This invention relates generally to semiconductor
structures.
[0002] A complementary metal oxide semiconductor (CMOS) device is
generally a delicate electronic structure formed by a combination
of lithographic and etching techniques that allow the device to be
formed and exist in a microscopically clean, contamination free
environment with precisely controlled physical properties to ensure
reliable and efficient high speed operation. As a result, there is
a need to control the dielectric constant of materials used to
separate the electronic components and interconnections within the
device.
[0003] To this end, an interlayer dielectric (ILD) material is
deposited around the structures (transistors, passives, etc.) and
between the layers of interconnections that make up the CMOS device
for the purpose of establishing a dielectric constant. The
dielectric constant affects the speed with which signals may
propagate through the interconnection of the device.
[0004] While many dielectric materials have been studied, for the
lowest dielectric constants, increasing amounts of void space and
hence air have been incorporated within ILD materials. Indeed, true
air gaps have been engineered into the devices directly to optimize
the lowest effective dielectric constants. Air gap structures may
be formed and encapsulated to protect such structures from the
deleterious effects of environmental contamination.
[0005] Similarly, in a variety of other circumstances, it may be
desirable to form air gap structures in various microelectronic,
micromechanical, microbiological, and microoptical systems, as well
as, microelectromechanical system (MEMS) device.
[0006] Thus, there is a need to make airgaps in semiconductor
structures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is an enlarged cross-sectional view in accordance
with one embodiment of the present invention;
[0008] FIG. 2 is an enlarged cross-sectional view of a subsequent
stage of manufacturing in accordance with one embodiment of the
present invention.
[0009] FIG. 3 is an enlarged cross-sectional view of another
embodiment of the present invention;
[0010] FIG. 4 is an enlarged cross-sectional view of the structure
shown in FIG. 3 after further processing in accordance with one
embodiment of the present invention; and
[0011] FIG. 5 is a graph of surface energy for materials with and
without treatment according to one embodiment of the present
invention.
DETAILED DESCRIPTION
[0012] Referring to FIG. 1, a semiconductor wafer 15 may have a
thermally decomposing sacrificial layer 14 formed thereon. Defined
within the layer 14 may be an interconnect 16 in one embodiment of
the present invention. For example, the interconnect may be a
copper interconnect in accordance with the dual damascene process.
A porous etch stop capping layer 12 may be formed over the entire
structure.
[0013] In some embodiments, the structure 10 may be a portion of a
complementary metal oxide semiconductor (CMOS) integrated circuit.
In other embodiments, it may be a portion of a
microelectromechanical system.
[0014] The layer 14 may be driven off by heating the structure 10
after the capping layer 12 has been deposited on the surface of the
polymer. The capping layer 12 can also serve as an etch stop for
the creation of the next layer. If the layer 12 is porous, the
thermally decomposed sacrificial layer 14 may be driven off without
removing the layer 12. However, in other embodiments, apertures of
any type may be formed in the layer 12 as desired.
[0015] As a result of the thermally driven decomposition and
removal material of the forming the layer 14, an air gap region,
pocket, or cavity 18 of low dielectric constant may be formed as
shown in FIG. 2. Any technique for heating the layer 14 can be
used, including baking or exposure to infrared or other energy
sources.
[0016] Advantageously, the sacrificial layer 14 may be made of a
material that may be decomposed by temperatures greater than those
normally encountered during conventional semiconductor fabrication
processes. A film that decomposes at relatively high temperatures
(e.g., greater than about 260.degree. C.) into smaller molecular
weight effluents is advantageous. Advantageously, the decomposing
film exhibits a high decomposition temperature and generally lower
molecular weight byproducts on decomposition so that those
byproducts can diffuse away through the layer 12.
[0017] The following chart provides a list of components and their
thermal decomposition temperatures (Td):
1 Polymer Basis or Family Td Polypropylene oxide (PPO) 325-375 C.
Polymethylstyrene (PMS) 350-375 C. Polycaprolactone 325 C.
Polycarbonate 325-375 C. Polyamideimide (PAI) 343 C. Polyamide-6, 6
(Nylon 6/6) 302 C. Polyphthalamide (PPA, Amodel) 350 C.
Polyetherketone (PEK) 405 C. Polyethretherketone (PEEK) 399 C.
Polybutyllene terephthalate (PBT) 260 C. Polyethyllene
terephthalate (PET) 300 C. Polystyrene (PS) 260 C.
syndiotactic-Polystyrene (syn-PS) >320 C. Polyphenylene Sulfide
(PPS) 332 C. Polyether Sulfone (PES) 400 C.
[0018] In accordance with another embodiment of the present
invention, the layer 12 may be sufficiently porous to facilitate
the exhaustion of the decomposed sacrificial layer 14 upon heating.
A thin layer of hydrogen silsesquioxane (HSQ) or
methylsilsesquioxane (MSQ) spin-on glass (SOG) may be utilized as
the capping layer 12. After being cured, the HSQ or MSQ layer 14
may be exposed to electron beam or plasma conditions to densify the
HSQ or MSQ film to be like a silicon dioxide film.
[0019] In some cases, a silicon dioxide chemical vapor deposition
layer may be applied as an option to seal all remaining pores in
the HSQ or MSQ film for subsequent metal interconnect processes.
The deposited silicon dioxide layer may enhance the mechanical
properties of the HSQ or MSQ layer and/or seal the remaining pores
in the HSQ or MSQ films.
[0020] In some embodiments, the stress that is caused on the layer
12 during decomposition may be reduced. HSQ or MSQ may be
sufficiently porous to enhance the ability of the thermally
decomposing polymers to diffuse out of the air gap pocket or cavity
18, through the layer 12, without building up pressure to
excessively deform the layer 12. The layer 12 performance may be
comparable to silicon dioxide films after electron beam or plasma
treatment of the layer 12. In some cases the mechanical performance
of the layer 12 may be enhanced by forming a sealing material, such
as deposited silicon dioxide, on top-of the HSQ/MSQ layer 12.
[0021] In some cases the receiving surface may be hydrophilic while
the polymer decomposing film such as those described herein may be
relatively hydrophobic. Because of the energy mismatch, when the
decomposing film is applied over surface irregularities, such as
trenches, there may be incomplete filling of those trenches or
bridging.
[0022] As a result, it is desirable to energy match the decomposing
film to the underlying surface. In other words, if the underlying
surface or the polymer are not both hydrophilic or both
hydrophobic, it may be desirable to convert one of the surfaces to
energy match the other.
[0023] In the case of hydrophobic decomposing polymers such as
those described previously herein, it may be most feasible to
simply modify a hydrophilic surface to which they are to be applied
to make that surface hydrophobic. Thus, referring to FIG. 3, a
substrate 52 may be covered by an oxide 40 having a trench 44
formed therein. A surface coating 42 may be applied to the oxide 40
to present an energy match with the decomposing film that may be
applied. The film 42 may convert the hydrophilic material 40 to
present a more hydrophobic surface which energy matches with the
applied decomposing film.
[0024] In one embodiment, the surface 40 may be treated in the
atmosphere of hexamethyldisilazane (HMDS) saturated nitrogen for
100 seconds at a temperature of 40.degree. C. Following a cooling
step, the surface 40 may be spin coated with the sacrificial
polymer 46, as shown in FIG. 4, and baked. As shown in FIG. 5, as a
result of the surface treatment, the surface energy of the
sacrificial material "A" better matches the surface energy of the
underlying substrate "B" compared to the substrate surface energy
before treatment "C".
[0025] Other materials that may be utilized for surface energy
modification include alkyl and fluoroalkyl functionalized
silylhalides, alkoxysilanes, and nitrogen containing silation
agents. With different types of substrates such as SiON, SiOF,
carbon doped oxide (CDO), and metal, appropriate surface tension
modifying agents may be utilized. These may include self-assembled
monolayers (SAMs) formed from precursors including, but not limited
to, thiols, sulfides, phosphates, phosphites, alkenes, chelation
agents (benzotriazole (BTA), crown ethers, kryptands,
cyclodextrins, poly and oligothiophenes, poly and oligoanalines) to
mention a few examples.
[0026] While the present invention has been described with respect
to a limited number of embodiments, those skilled in the art will
appreciate numerous modifications and variations therefrom. It is
intended that the appended claims cover all such modifications and
variations as fall within the true spirit and scope of this present
invention.
* * * * *