U.S. patent application number 10/323980 was filed with the patent office on 2004-06-24 for novel layer of high-k inter-poly dielectric.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Company. Invention is credited to Hou, Tuo-Hung, Lin, Yeou-Ming.
Application Number | 20040121534 10/323980 |
Document ID | / |
Family ID | 32468967 |
Filed Date | 2004-06-24 |
United States Patent
Application |
20040121534 |
Kind Code |
A1 |
Lin, Yeou-Ming ; et
al. |
June 24, 2004 |
NOVEL LAYER OF HIGH-K INTER-POLY DIELECTRIC
Abstract
A new Inter Poly Dielectric (IPD) layer is provided for use in
creating ultra-small gate electrodes. A first and a second high-k
dielectric film are provided which remain amorphous at relatively
high processing temperatures. The first high-k dielectric film is
of Al.sub.3O.sub.5--ZrO.sub.2--Al.sub.3O.sub.5, the second high-k
dielectric film is aluminum doped ZrO.sub.2 or HfO.sub.2.
Inventors: |
Lin, Yeou-Ming; (Jungli
City, TW) ; Hou, Tuo-Hung; (Chia-Yi, TW) |
Correspondence
Address: |
GEORGE O. SAILE & ASSOCIATES
28 DAVIS AVENUE
POUGHKEEPSIE
NY
12603
US
|
Assignee: |
Taiwan Semiconductor Manufacturing
Company
|
Family ID: |
32468967 |
Appl. No.: |
10/323980 |
Filed: |
December 19, 2002 |
Current U.S.
Class: |
438/257 ;
257/E29.165 |
Current CPC
Class: |
H01L 29/511 20130101;
Y10S 438/954 20130101 |
Class at
Publication: |
438/257 |
International
Class: |
H01L 021/336 |
Claims
What is claimed is:
1. A method of creating a layer of Inter-Poly Dielectric for use in
flash memory devices, comprising the steps of: providing a silicon
substrate, an active surface area having been defined in the
surface of said substrate, said active surface area being
designated as being the surface area of the substrate over which at
least one gate structure is to be created, said gate structure
forming a gate structure for a flash memory device; depositing a
layer of gate dielectric over the surface of the substrate;
depositing a layer of floating gate material over the surface of
the layer of gate dielectric; depositing a composite layer of
Inter-Poly Dielectric over the surface of the layer of floating
gate material; depositing a layer of control gate material over the
surface of the layer of gate dielectric; patterning said layer of
control gate material, said composite layer of Inter-Poly
Dielectric, said layer of floating gate material and said layer of
gate dielectric; and forming source and drain regions in the
surface of said substrate, self-aligned with said patterned layers
of control gate material, of Inter-Poly Dielectric, of floating
gate material and of gate dielectric.
2. The method of claim 1 wherein said layer of Inter-Poly
Dielectric comprises: a first layer of Al.sub.2O.sub.3 deposited
over the surface of said layer of floating gate material; a layer
of ZrO.sub.2 deposited over the surface of said first layer of
Al.sub.2O.sub.3; and a second layer of Al.sub.2O.sub.3 deposited
over the surface of said layer of ZrO.sub.2.
3. The method of claim 1 wherein said layer of Inter-Poly
Dielectric comprises a layer of ZrO.sub.2, doped with aluminum,
deposited over the surface of said layer of floating gate
material.
4. The method of claim 1 wherein said layer of Inter-Poly
Dielectric comprises a layer of HfO.sub.2, doped with aluminum,
deposited over the surface of said layer of floating gate
material.
5. A method of creating a layer of Inter-Poly Dielectric for use in
flash memory devices, comprising the steps of: providing a silicon
substrate, an active surface area having been defined in the
surface of said substrate, said active surface area being
designated as being the surface area of the substrate over which at
least one gate structure is to be created, said gate structure
forming a gate structure for a flash memory device; depositing a
layer of gate dielectric over the surface of the substrate;
depositing a layer of floating gate material over the surface of
the layer of gate dielectric; depositing a first layer of
Al.sub.2O.sub.3 over the surface of said layer of floating gate
material; then depositing a layer of ZrO.sub.2 over the surface of
said first layer of Al.sub.2O.sub.3; then depositing a second layer
of Al.sub.2O.sub.3 over the surface of said layer of ZrO.sub.2;
then depositing a layer of control gate material over the surface
of the second layer of Al.sub.2O.sub.3; patterning said layer of
control gate material, said second layer of Al.sub.2O.sub.3, said
layer of ZrO.sub.2, said first layer of Al.sub.2O.sub.3, said layer
of floating gate material and said layer of gate dielectric; and
forming source and drain regions in the surface of said substrate,
self-aligned with said patterned layers of control gate material,
said second layer of Al.sub.2O.sub.3, said layer of ZrO.sub.2, said
first layer of Al.sub.2O.sub.3, said layer of floating gate
material and said layer of gate dielectric.
6. A method of creating a layer of Inter-Poly Dielectric for use in
flash memory devices, comprising the steps of: providing a silicon
substrate, an active surface area having been defined in the
surface of said substrate, said active surface area being
designated as being the surface area of the substrate over which at
least one gate structure is to be created, said gate structure
forming a gate structure for a flash memory device; depositing a
layer of gate dielectric over the surface of the substrate;
depositing a layer of floating gate material over the surface of
the layer of gate dielectric; depositing a layer of ZrO.sub.2,
doped with aluminum, over the surface of said layer of floating
gate material; depositing a layer of control gate material over the
surface of the layer of ZrO.sub.2; patterning said layer of control
gate material, said layer of ZrO.sub.2, doped with aluminum, said
layer of floating gate material and said layer of gate dielectric;
and forming source and drain regions in the surface of said
substrate, self-aligned with said patterned layers of control gate
material, of ZrO.sub.2, of floating gate material and of gate
dielectric.
7. A method of creating a layer of Inter-Poly Dielectric for use in
flash memory devices, comprising the steps of: providing a silicon
substrate, an active surface area having been defined in the
surface of said substrate, said active surface area being
designated as being the surface area of the substrate over which at
least on gate structure is to be created, said gate structure
forming a gate structure for a flash memory device; depositing a
layer of gate dielectric over the surface of the substrate;
depositing a layer of floating gate material over the surface of
the layer of gate dielectric; depositing a layer of HfO.sub.2,
doped with aluminum, over the surface of said layer of floating
gate material; depositing a layer of control gate material over the
surface of the layer of HfO.sub.2; patterning said layer of control
gate material, said composite layer of HfO.sub.2, said layer of
floating gate material and said layer of gate dielectric; and
forming source and drain regions in the surface of said substrate,
self-aligned with said patterned layers of control gate material,
of HfO.sub.2, of floating gate material and of gate dielectric.
Description
BACKGROUND OF THE INVENTION
[0001] (1) Field of the Invention
[0002] The invention relates to the fabrication of integrated
circuit devices, and more particularly, to a method of creating a
high-k inter-poly dielectric for the creation of small-scale gate
electrodes.
[0003] (2) Description of the Prior Art
[0004] Gate electrodes, which form the essential component of flash
memory devices, are typically created using overlying layers of
semiconductor material, with the lowest layer being a layer of pad
oxide (also referred to as a layer of gate dielectric) and the
highest layer being a layer of silicided material that serves as a
low resistivity electrical contact to the gate electrode. The
layers of the gate electrode are typically overlying layers of
dielectric, that can consist of polysilicon, separated by a layer
of Inter-Poly Dielectric (ILD).
[0005] Current technology for the creation of gate electrodes uses
a silicon dioxide layer as the gate dielectric for MOS devices.
With a sharp reduction in device feature size, the thickness of the
layer of gate dielectric must also be reduced, for the era of
device features in the sub-micron range the gate thickness is
approaching 2 nanometers or less. A continued reduction of the
thickness of the layer of gate dielectric leads to increasing the
tunneling current through this thin layer of gate dielectric. For
this reason, a thin layer of silicon dioxide (thinner than about
105 nm) cannot be used as the gate dielectric for MOS devices
having sub-micron device size.
[0006] The main issues facing the creation of ever smaller flash
memories center on maintaining fast programming and erase time
while simultaneously reducing the operating voltage of the device,
frequently resulting in a trade-off between reduced power and high
operating speed. The operating voltage must be reduced with reduced
device dimensions, resulting in the requirement to increase the
device-coupling ratio by increasing the floating gate capacitance
of the device. This leads to the requirement of reducing the
thickness of the layers of Inter Poly Dielectric (IPD) or to
provide layers of IPD of advantageous dielectric properties. Among
the most essential of these properties is the quality of the
interface between the layers of dielectric that are selected to
form the IPD. This because defects in interfaces between overlying
layers of dielectric can cause a reduction in the signal to noise
level of the device which, in sub-micron devices where a relatively
small number of charges distinguishes between data bit states,
quickly leads to an unacceptable design of the gate electrode.
[0007] Prior Art methods have primarily used silicon oxide as the
material of choice for the creation of a layer of IPD, this in part
because a layer of silicon oxide can be grown from an underlying
layer of polysilicon. It has thereby long been recognized that
grown layers of silicon oxide contain fewer defects (such as
pinholes) than deposited layers of material.
[0008] From the above it is clear that efforts to reduce flash
memory cell dimensions must focus not only on providing suitable
materials for the creation of layers of IPD but must also provide
methods whereby these layers of IPD can be properly deposited
without causing interface defects. The invention addresses the
first of these two aspects of creating flash memory cells by
providing a novel high-k layer of Inter Poly Dielectric (IPD).
[0009] U.S. Pat. No. 5,923,056 (Lee et al.) shows an Al doped Zr
dielectric layer.
[0010] U.S. Pat. No. 6,060,755 (Ma et al.) shows an Al doped Zr
dielectric.
[0011] U.S. Pat. No. 6,008,091 (Gregor et al.) reveals a
SiO.sub.2--TaO.sub.5--SiO.sub.2 dielectric layer.
[0012] U.S. Pat. No. 6,171,910 (Hobbs et al.) and U.S. Pat. No.
6,020,243 (Wallace et al.) are related patents.
SUMMARY OF THE INVENTION
[0013] A principle objective of the invention is to provide a
high-k dielectric layer for use as an Inter Poly Dielectric (IPD)
layer.
[0014] Another objective of the invention is to provide a gate
dielectric that allows for reduced programming voltage of
Electrically Erasable and Programmable Read Only Memory (EEPROM)
devices.
[0015] Another objective of the invention is to provide a gate
dielectric that allows for reduced programming time of Electrically
Erasable and Programmable Read Only Memory (EEPROM) devices.
[0016] A still further objective of the invention is to provide a
high-k dielectric layer for use as an Inter Poly Dielectric (IPD)
layer of superior thermal stability.
[0017] In accordance with the objectives of the invention a new
Inter Poly Dielectric (IPD) layer is provided for use in creating
ultra-small gate electrodes. A first and a second high-k dielectric
film are provided which remain amorphous at relatively high
processing temperatures. The first high-k dielectric film is of
Al.sub.3O.sub.5--ZrO.sub.2--Al.sub.3O.- sub.5, the second high-k
dielectric film is aluminum doped ZrO.sub.2 or HfO.sub.2.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 shows a cross section of the layer of ILD as created
under the first embodiment of the invention.
[0019] FIG. 2 shows a cross section of the layer of ILD as created
under the second embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0020] Electrically Programmable Read Only Memory (EPROM) cells are
capable of being electrically programmed. EPROM cells may or may
not be capable of being electrically erased. Electrically erasable
and electrically programmable read-only memory (EEPROM) cells are a
special type of EPROM cells. Flash EEPROM cells are specific types
of both EPROM and EEPROM cells. Flash EEPROM cells are configured
such that a plurality of the cells may be erased during a single
erasing operation. In many devices, a row of memory cells, a column
of memory cells or even the entire memory array may be erased
during the same erasing operation. EEPROM cells that are not flash
EEPROM's can be referred to as individual erasable EEPROM or
IEEPROM's.
[0021] In order to reduce the programming voltage and the
programming time of EEPROM devices, the IPD coupling capacitance
can be increased by reducing the effective dielectric thickness of
the IPD layer. However, decreasing the thickness of for instance a
layer of ONO, that is used as layer of IPD of a gate electrode,
significantly increases the leakage current through this layer.
This results in poor data retention of the memory device that is
created using the (reduced thickness) layer of ONO as an IPD layer.
One of the materials that has been mentioned for the use of a layer
of IPD is titanium oxide (Ta.sub.2O.sub.5). Since Ta.sub.2O.sub.5
has a high dielectric constant, it may be expected that
Ta.sub.2O.sub.5 provides benefits in allowing a reduction in the
thickness of the layer of ILD and thus in improving programming
performance, due to its high dielectric constant. It is known in
the art that the higher the dielectric constant of a layer of
material, the lower the barrier height of this layer, which is
critical to assuring low leakage current across the layer.
Al.sub.3O.sub.3 has a relatively high dielectric constant of 8.5,
this is still below a desired value. However, a high-k dielectric
layer comprising aluminum (such as Al.sub.3O.sub.5) or a layer of
ZrO.sub.2, which is doped by impurity implantation, provides
improved thermal stability over comparable, high-k layers which
have not been provided with an impurity implantation.
[0022] The requirements that must be met by a layer of IPD for the
application of such a layer in the creation of flash memory cells
can be summarized as follows:
[0023] must provide a high coupling ratio of the floating gate
capacitance, this to shorten programming and erase times and to
reduce required operating voltages
[0024] must have low leakage current, this to guarantee a data
retention time of at least 10 years, and
[0025] must be able to withstand high temperatures processing
environments so that the layer of ILD can be integrated with the
manufacturing of semiconductor devices.
[0026] Previous experiments have shown that high-k dielectrics,
used as a layer of ILD, provide for a high retention rate of flash
memory cells.
[0027] A layer of Al.sub.3O.sub.3 has previously been proposed to
be used as the ILD of a gate electrode. This layer of
Al.sub.3O.sub.3, deposited to a thickness of about 10 nm and having
a dielectric constant of about 9.5, provided improved performance
in erase time, voltage and leakage current when compared with
conventional layers of ONO applied for the TLD.
[0028] Also previously proposed (Ma et al. U.S. Pat. No. 6,060,755)
has been a layer of aluminum doped with ZrO.sub.2, the doping being
performed by methods of sputter or CVD. This latter approach
provided for:
[0029] improved thermal stability when compared with an undoped
layer of ZrO.sub.2, and
[0030] a thickness of the doped layer of ZrO.sub.2 Of about 7.5 nm,
a dielectric constant value in excess of 18 has been measured for
the doped layer of ZrO.sub.2.
[0031] ZrO.sub.2 and Hafnium Oxide (HfO.sub.2) have been mentioned
in the literature of the art as alternate candidates for the
materials of gate dielectric for future generations of gate
electrodes. This is due to a higher dielectric constant and to
improved thermal stability of these layers when compared with
Ta.sub.2O.sub.5 and TiO.sub.2. These materials are expected to be
increasingly used in the manufacturing of semiconductor devices if
these materials can be processed such that they can serve as a
replacement material for conventional SiO.sub.2 in creating a gate
dielectric. The use of ZrO.sub.2 and HfO.sub.2 can potentially be
extended for use as an inter-poly dielectric for non-volatile
memory applications. The coupling ratio of the non-volatile memory
can then be increased in order to reduce programming time and
programming voltage, due to the thin effective dielectric thickness
of the layer of ILD. A reasonable leakage level, required for data
retention, can be maintained due to the (actual or physical)
thickness of the layer of ILD.
[0032] The following paragraphs address the invention. A layer of
Al.sub.2O.sub.3 provides a high dielectric constant (8.5), which is
too low for further reduction of the effective thickness of the
layer of ILD. A layer of Al.sub.2O.sub.3 however has a higher
barrier height, which improves leakage current performance while
Al.sub.2O.sub.3 forms an interface with silicon of good quality. We
can therefore deposit a layer of Al.sub.2O.sub.3 over the silicon
surface (as an intermediate layer), suppressing the interaction
between the high-k material and the underlying silicon. The in this
manner created layers of
Al.sub.2O.sub.3--ZrO.sub.2--Al.sub.2O.sub.3 or
Al.sub.2O.sub.3--HfO.sub.2- --Al.sub.2O.sub.3 effectively provide
the structure of a thinner layer of dielectric, resulting in lower
leakage current, improved thermal stability and an improved
interface between the layers and the underlying silicon.
[0033] Further provided by the invention are layers ZrO.sub.2 and
HfO.sub.2 doped with aluminum, to be used as materials for the IPD.
The doping of these layers is provided by applying methods of
metallo-organic CVD (MO-CVD) and aluminum CVD (Al-CVD). These
latter layers have been demonstrated to provide excellent thermal
stability and are provided as candidates for the use as layers of
IPD.
[0034] The above paragraphs, which have addressed the invention,
are reflected in the cross sections that are shown in FIGS. 1 and
2, as follows:
[0035] FIG. 1 presents a first embodiment of the invention and
shows a cross section of a silicon substrate 10 over which have
been created:
[0036] 12, source implant for the source region of the gate
electrode
[0037] 14, drain implant for the drain region of the gate
electrode
[0038] 16, a layer of gate dielectric (pad oxide) of the gate
electrode
[0039] 18, the floating gate of the gate electrode
[0040] 20, a layer of Al.sub.2O.sub.3, deposited over of the
floating gate 18 of gate dielectric
[0041] 22, a layer of ZrO.sub.2, deposited over the layer 20 of
Al.sub.2O.sub.3
[0042] 24, a layer of Al.sub.2O.sub.3, deposited over the layer 22
of ZrO.sub.2, and
[0043] 26, the control gate of the gate electrode.
[0044] The gate electrode that is created as shown in cross section
in FIG. 1 provides the following advantages:
[0045] the processing steps are compatible with the creation of
expected (future) gate electrode structures
[0046] a layers 20/22/24 of ILD provide a higher k value when
compared with pure Al.sub.2O.sub.3
[0047] layer 20 of Al.sub.2O.sub.3 provides a good interface with
the underlying silicon 10
[0048] layer 20 of Al.sub.2O.sub.3 provides improved thermal
stability of layer 22 of ZrO.sub.2 overlying the silicon 10
[0049] layers 20 and 22 of Al.sub.2O.sub.3 provide high barrier
height, improving current leakage performance of the gate
electrode
[0050] layer 22 of ZrO.sub.2 provides for increased thickness of
the combined layers 20, 22 and 24, improving current leakage
performance of the gate electrode.
[0051] FIG. 2 presents a second embodiment of the invention and
shows a cross section of a silicon substrate 10 over the surface of
which have been created:
[0052] 12, source implant for the source region of the gate
electrode
[0053] 14, drain implant for the drain region of the gate
electrode
[0054] 16, a layer of gate dielectric (pad oxide) of the gate
electrode
[0055] 18, the floating gate of the gate electrode
[0056] 28, a layer that comprises either: 1) a layer of ZrO.sub.2,
doped with aluminum or 2) a layer of HfO.sub.2, doped with
aluminum, and
[0057] 26, the control gate of the gate electrode.
[0058] The gate electrode that is created as shown in cross section
in FIG. 2 provides the following advantages:
[0059] the processing steps are compatible with the creation of
expected (future) gate electrode constructs
[0060] layers 28 of aluminum doped ZrO.sub.2 or HfO provide a
higher k value when compared with pure Al.sub.2O.sub.3, and layer
28 of aluminum doped ZrO.sub.2 provides improved thermal stability
when overlying the silicon 10 as compared with a layer of undoped
ZrO.sub.2.
[0061] Although the invention has been described and illustrated
with reference to specific illustrative embodiments thereof, it is
not intended that the invention be limited to those illustrative
embodiments. Those skilled in the art will recognize that
variations and modifications can be made without departing from the
spirit of the invention. It is therefore intended to include within
the invention all such variations and modifications which fall
within the scope of the appended claims and equivalents
thereof.
* * * * *