U.S. patent application number 10/284508 was filed with the patent office on 2004-04-29 for orientation independent oxidation of nitrided silicon.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Gluschenkov, Oleg, Hegde, Suryanarayan G., Tews, Helmut H..
Application Number | 20040082197 10/284508 |
Document ID | / |
Family ID | 32107590 |
Filed Date | 2004-04-29 |
United States Patent
Application |
20040082197 |
Kind Code |
A1 |
Gluschenkov, Oleg ; et
al. |
April 29, 2004 |
ORIENTATION INDEPENDENT OXIDATION OF NITRIDED SILICON
Abstract
Forming a vertical MOS transistor or making another
three-dimensional integrated circuit structure in a silicon wafer
exposes planes having at least two different crystallographic
orientations. Growing oxide on different crystal planes is
inherently at different growth rates because the inter-atomic
spacing is different in the different planes. Heating the silicon
in a nitrogen-containing ambient to form a thin layer of nitride
and then growing the oxide through the thin nitrided layer reduces
the difference in oxide thickness to less than 1%.
Inventors: |
Gluschenkov, Oleg;
(Wappingers Falls, NY) ; Hegde, Suryanarayan G.;
(Hollowville, NY) ; Tews, Helmut H.; (Munich,
DE) |
Correspondence
Address: |
INTERNATIONAL BUSINESS MACHINES CORPORATION
DEPT. 18G
BLDG. 300-482
2070 ROUTE 52
HOPEWELL JUNCTION
NY
12533
US
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
Infineon Technologies North America Corp.
San Jose
CA
|
Family ID: |
32107590 |
Appl. No.: |
10/284508 |
Filed: |
October 29, 2002 |
Current U.S.
Class: |
438/787 ;
257/E21.268; 257/E21.301 |
Current CPC
Class: |
H01L 21/3141 20130101;
H01L 21/02247 20130101; H01L 21/02332 20130101; H01L 21/32105
20130101; H01L 21/3144 20130101 |
Class at
Publication: |
438/787 |
International
Class: |
H01L 021/31 |
Claims
What is claimed is:
1. A method of forming an oxide film on a complex surface of a
silicon substrate comprising the steps of; providing a silicon
substrate; forming a set of structures in the substrate having at
least two planes of different crystallographic orientation; forming
a layer of nitride, having a nitride thickness, on said at least
two planes by heating the substrate in an ambient containing
nitrogen; and growing a layer of oxide, having an oxide thickness,
on said at least two planes, such that the oxide thicknesses on
said at least two planes are substantially equal.
2. A method according to claim 1, in which said step of growing a
layer of oxide comprises forming at least some oxygen free
radicals.
3. A method according to claim 1, in which said step of growing
oxide comprises converting all of said layer of nitride to oxide
and reacting at least some of the underlying silicon.
4. A method according to claim 2, in which said step of growing
oxide comprises converting all of said layer of nitride to oxide
and reacting at least some of the underlying silicon.
5. A method according to claim 1, in which said nitride thickness
is less than one third of said oxide thickness.
6. A method according to claim 2, in which said nitride thickness
is less that one third of said oxide thickness.
7. A method according to claim 3, in which said nitride thickness
is less than one third of said oxide thickness.
8. A method according to claim 4, in which said nitride thickness
is less than one third of said oxide thickness.
9. A method according to claim 5, in which said nitride thickness
is less than 2 nm.
10. A method according to claim 6, in which said nitride thickness
is less than 2 nm.
11. A method according to claim 7, in which said nitride thickness
is less than 2 nm.
12. A method according to claim 8, in which said nitride thickness
is less than 2 nm.
13. A method according to claim 2, in which said step of forming
oxygen free radicals comprises reacting hydrogen and oxygen in the
same process chamber in which the oxidation takes place at a
pressure of less than about 30 Torr.
14. A method according to claim 13, in which said step of growing
oxide comprises converting all of said layer of nitride to oxide
and reacting at least some of the underlying silicon.
15. A method according to claim 13, in which said nitride thickness
is less than one third of said oxide thickness.
16. A method according to claim 14, in which said nitride thickness
is less than one third of said oxide thickness.
17. A method of forming a vertical field effect transistor in a
silicon substrate comprising the steps of; providing a silicon
substrate; forming a structure in the substrate having at least two
vertical planes of different crystallographic orientation; forming
a layer of nitride, having a nitride thickness, on said at least
two planes by thermally nitriding the substrate; forming an upper
and lower transistor electrode in proximity to a transistor body
region formed in said substrate; growing a gate layer of oxide,
having an oxide thickness, on said at least two planes, such that
the oxide thicknesses on said at least two planes are substantially
equal, including forming at least some oxygen free radicals that
react with said layer of nitride to form oxide; and forming a
transistor gate disposed adjacent to said gate layer.
18. A method according to claim 17, in which said step of growing
oxide comprises converting all of said layer of nitride to oxide
and reacting at least some of the underlying silicon.
19. A method according to claim 17, in which said nitride thickness
is less than one third of said oxide thickness.
20. A method according to claim 18, in which said nitride thickness
is less than one third of said oxide thickness.
21. A method according to claim 14, in which said step of forming
oxygen free radicals comprises reacting hydrogen and oxygen in the
process chamber at a pressure of less than about 30 Torr.
22. A method according to claim 21, in which said step of growing
oxide comprises converting all of said layer of nitride to oxide
and reacting at least some of the underlying silicon.
23. A method according to claim 19, in which said transistor is a
Fin-FET and said at least two crystal planes are on the outer
surfaces of a projecting column of said silicon substrate.
24. A method according to claim 19, in which said transistor is a
vertical trench transistor and said at least two crystal planes are
on the inner surfaces of an aperture formed in said silicon
substrate.
Description
TECHNICAL FIELD
[0001] The field of the invention is that of silicon semiconductor
processing, in particular forming vertical CMOS transistors.
BACKGROUND OF THE INVENTION
[0002] In the constant drive to save space, advanced CMOS
processing techniques now include CMOS transistors that are
oriented vertically. When a trench is etched into a silicon
substrate, a transistor formed in the trench with a vertical
orientation will have its gate exposed to two different crystal
orientations, and it is known in the art that oxide grows at
distinctly different rates on the <100> and <110>
crystal planes. The difference in growth rates on these planes
typically ranges between 40% and 100%.
[0003] It has been reported in U.S. Pat. No. 6,358,867 that a
growth ratio of 0.9 for the <100> and <110> planes has
been achieved using a low pressure mixture of hydrogen and
oxygen.
[0004] This improvement still falls short of the ideal goal of
equal growth rates, which will result in still better quality
transistors and other structures formed on complex multi-crystal
orientation surfaces.
[0005] The art still needs an improved method of growing
high-quality oxide on complex surfaces of silicon having at least
two crystallographic orientations.
SUMMARY OF THE INVENTION
[0006] The invention relates to a method of growing oxide on a
complex surface that achieves a ratio of growth rates of 99%.
[0007] A feature of the invention is that a small ratio of nitride
thickness to final oxide thickness is preferred.
[0008] A feature of the invention is the use of a prebake step in a
nitrogen-containing ambient.
[0009] Another feature of the invention is nitride deposition with
the use of an ammonia ambient at an elevated temperature.
[0010] Another feature of the invention is a prebake temperature
range of between 500.degree. C. and 1100.degree. C.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1A shows an exploded view of a vertical transistor.
[0012] FIG. 1B shows the spatial relationship of crystal
planes.
[0013] FIG. 3 shows a low chart according to the invention.
[0014] FIG. 2 (prior art) demonstrates the parabolic kinetic law
for the oxidation of silicon with atomic nitrogen.
[0015] FIG. 4 shows data from the practice of the invention.
[0016] FIG. 5 illustrates the memory effect in the oxidation of
silicon with atomic oxygen.
[0017] FIG. 6 illustrates the memory effect in the oxidation of
nitrided silicon with atomic oxygen.
[0018] FIG. 7 shows data from the prior art and from the
invention.
DETAILED DESCRIPTION
[0019] The process according to the invention, summarized in FIG.
3, starts with a silicon wafer, whether bulk or silicon on
insulator or patterned silicon on insulator (step 210 in FIG. 2).
Conventional preparation steps, such as well formation, threshold
implants, pad oxide (SiO.sub.2) and nitride (Si.sub.3N.sub.4), etc.
well known to those skilled in the art are performed.
[0020] A set of apertures in the silicon wafer are etched, e.g.
shallow trenches (less than 2 micro) to isolate active areas and/or
deep trenches for capacitor in DRAM cells or for other purposes
(Step 220). Forming vertical transistors to save space or to
increase performance in a logic circuits (i.e. non-DRAM) are also
included within the scope of the invention. For instance, there is
a class of high-performance 3-D logic transistor known as Fin-FETs,
the gate oxide wraps around a thin silicon pillar ("Fin") formed on
top of the substrate.
[0021] The particular order in which the various features described
above are formed in the substrate is not important. For instance,
memory cells with vertical transistors can be formed first followed
by the formation of isolation trenches, wells, high-speed logic
transistors, and interconnects.
[0022] Passivation of the vertical aperture surfaces and a cleaning
step, preferably with an HF-containing chemistry, are performed in
Step 230. The passivation process may include a conventional
(orientation-dependent) thermal oxidation of the complex silicon
surface while the cleaning process may consist of a sequence of
cleans designed to remove the optional passivation layer and to
reduce both organic and metallic contamination of the surface.
These cleaning sequences are well known in the art. Furthermore,
the final amount of a chemical oxide produced by the sequence at
the silicon surface can be easily controlled by selecting
appropriate solution parameters during the last cleaning step. It
is highly preferable for the inventive method that the amount of
chemical oxide is minimized by selecting an appropriate solution at
the last step.
[0023] The next step (Step 240) is to create a thin and uniform
layer of silicon nitride atop of the clean multi-oriented crystal
surface. The preferred way of forming such film is a thermal
nitridization process. The thermal nitridization process is slow
and often self-limiting, so that the resulting film thickness is
insensitive to the process time and the orientation of silicon
crystal, for the thermal growth of silicon nitride is diffusion
limited. In general, a diffusion-limited process is sensitive to
the process temperature and type of diffusing species but
insensitive to the crystal orientation of underlying material.
Therefore, the thickness of the thermal nitride film can be
controlled by selecting process temperature and type of nitridizing
species. The self-limiting nature of the process also produces
greater uniformity than a conventional deposition process.
Illustratively, the wafer is baked at a preferred temperature of
750.degree. C. for 20 minutes in an ammonia ambient and produces a
continuous nitride film of approximately 6-10 .ANG. thick.
Illustrative examples of other reactive nitrogen-containing gases
include, but are not limited to: N2, NH3, hydrazine (N2H4), and
mixtures thereof. The reactive nitrogen-containing gas can also
include various nitrogen-containing radicals such as atomic
nitrogen, NH2, and NH radicals. The radicals can be created with
the aid of some excitation, for instance, a plasma excitation, a
photo excitation, an electron-beam excitation, or intense heat. The
radicals can be primarily formed either in the vicinity of the
wafer or far from the processing zone. In the latter case, an
efficient delivery system should be present to transfer radicals to
the processing zone with minimal losses. If the nitrogen-containing
gas consists of an appreciable amount of atomic nitrogen or other
nitrogen-containing radicals the thermal nitride can be formed at a
substantially lower temperature. The preferred temperature range in
this case is from about room temperature to about 1100.degree.
C.
[0024] In some embodiments of the present invention, an in-situ
cleaning procedure may be incorporated in to the Step 240 of the
present invention to remove any native or chemical oxide layer that
may be present on the silicon surface prior to the nitride
formation. The in-situ cleaning procedure may include a thermal
desorption prebake in high vacuum at a pressure of below 10.sup.-6
Torr or hydrogen (H2) ambient at a reduced pressure of below 300
Torr. Specifically, both H2and vacuum prebaking are performed at a
temperature of from about 850.degree. C. to about 1000.degree. C.
(950.degree. C. being preferred) and at a reduced pressure of below
300 Torr.
[0025] It is an important advantageous feature of the present
invention that the nitride layer formed in Step 240 can be much
thinner (preferably, at least 3 time thinner) than the target
thickness of the final oxide layer. The inventive method has been
proven to work even with a monolayer of silicon-nitrogen (Si-N)
bonds over the silicon surface. Since the characteristic size of
the Si-N bond at Si surface is about 2 Angstroms, the minimal
physical thickness of the nitride film is only 2 Angstroms.
Preferably, the nitride film is less than 2 nm thick.
[0026] The ability to provide a film based on such a thin layer
permits greater throughput and therefore reduces cost. This feature
is also counter-intuitive, since workers in the art would expect
that the greatest uniformity would be provided by converting only
the nitride to oxide and that reacting the different crystal
structures to form oxide would result in a different oxide
structure and thus a different growth rate; i.e. that a smaller
ratio of nitride to oxide thickness would lead to less
uniformity.
[0027] Oxidation of silicon nitride is known in the art. Some form
of excitation is often required in order to convert a stable
silicon nitride into silicon oxide. Highly-reactive atomic oxygen
radicals can be used for this purpose. Because deposited silicon
nitride is an amorphous substance, its oxidation rate does not
depend on the underlying crystallographic orientation of silicon.
One skilled in the art might conclude that a silicon oxide film
could be produced on different orientations of silicon by first
depositing a thick amorphous silicon nitride layer and then
oxidizing it by known methods. The oxidation would be stopped
before the underlying silicon substrate is reached, so that the
different crystal orientations do not cause different growth rates.
Such a method has the drawbacks that: a) the uniformity of an oxide
layer grown through deposited nitride cannot be better than the
uniformity of the relatively thick nitride layer; and b) the
Silicon-oxide interface tends to have an excessive amount of
nitrogen, which can reduce the interface mobility. The inventive
method is substantially different from such an approach because it
does not need a thick silicon nitride layer.
[0028] Preferably, the oxidation process employs at least some
atomic oxygen, so formation of atomic oxygen is shown as Step 250.
This formation process is typically combined with the heating of
the wafer in an ambient (e.g. ozone) that generates free oxygen
radicals. If desired, the free radicals could also be produced
separately, as in an electric discharge. The atomic oxygen radicals
can be also produced by reacting hydrogen and oxygen in the process
chamber at a low pressure (less than 30 Torr). This chemical
process is known in the art as In-situ Steam Generation (ISSG)
process or as Free Radical Enhanced Rapid Thermal Oxidation (FRE
RTO).
[0029] The oxide is grown thermally, illustratively at a
temperature of 1050.degree. C. by FRE RTO at 10 Torr and with 33%
of hydrogen in the mixture, though the film properties are not
strongly dependent on the growth temperature and hydrogen content
in the mixture. Hydrogen is not required for oxidation--it is
provided as a result of the choice of a particular method of
forming oxygen radicals. The nitride is consumed during the
oxidation process, though it provides a "memory" effect and affects
the relative growth rates for the oxide on the two crystal
orientations even for oxide thickness much greater than the thin
nitride layer.
[0030] FIG. 2 (prior art) shows data for oxide growth at
1050.degree. C. by FRE RTO at 10 Torr with 33% of hydrogen in the
mixture for various times, on un-nitrided wafers. The square of the
oxide thickness is plotted versus time, showing that the growth
follows a purely parabolic kinetic law and that the oxidation
process is diffusion limited. In theory, a diffusion-limited
oxidation of silicon should be orientation independent because the
speed of oxidation depends on the speed of diffusion of oxidizing
species through the same silicon oxide. FIG. 2 demonstrates that
the diffusion property of oxidizing species is different for the
oxides grown on different planes. This means that these oxides have
a slightly different structure.
[0031] FIG. 4 shows data for oxide growth at 1050.degree. C. by FRE
RTO at 10 Torr with 33% of hydrogen in the mixture for various
times, on wafers that were nitrided according to the invention and
on un-nitrided wafers. The square of the oxide thickness is plotted
versus time, also showing that the growth follows a purely
parabolic kinetic law and that the oxidation process is diffusion
limited.
[0032] This curve demonstrate clearly that the nitrided silicon
wafers (solid lines) have oxide thickness on the <100> and
<110> planes that are much closer than the corresponding
oxide thickness for un-nitrided wafers (dotted lines). Even at the
largest thickness of oxide, the difference in oxide thickness for
the two crystal planes was less than 1 % for the nitrided wafers
(compared with 10% for the un-nitrided wafers). For oxide thickness
of about 50 .ANG., the difference in oxide thickness for the two
orientations was not detectable. This also illustrates that the
presence of a thin nitride layer altered the structure of grown
oxides such that the diffusion property became essentially the
same.
[0033] FIG. 7 compares the quality of the oxide/silicon interface
for the inventive method and standard oxidation processes. The
interface quality is judged by the interface density of states at
mid-gap (Dit) measured after a low temperature (400.degree. C., 20
minutes) forming gas anneal. Lower Dit values correspond to a lower
amount of charge traps at the interface and, therefore, to a better
oxide. Measuring Dit values is a standard way of determining the
quality of the interface. The Dit values are reported in arbitrary
units for comparison only. The furnace oxides were grown in a
conventional vertical oxidation furnace in dry oxygen ambient at
atmospheric pressure. Clearly, the oxides formed by the inventive
method have the same (or better) quality as compared to those
formed by conventional methods.
[0034] FIG. 5 and FIG. 6 illustrate the memory effect in oxidation
of nitrided silicon.
[0035] FIG. 5 shows, partially pictorial, partially schematic form,
that the conventional oxide grown on different crystallographic
orientations of silicon and on silicon nitride has a slightly
different structure represented by the cross hatching, as
elucidated above. We hypothesize that more oxide growth results in
the repetition of the same structure. An initial thickness of
oxide, 22, 42 and 62 grown on bases 20, 40 or 60 increases to a
thickness 25, 45 or 65, but keeps its original structure. The
thicknesses of layers 25, 45 and 65 are represented schematically
by rectangles of the same height, though FIG. 2 shows that actual
films will be different in thickness. FIG. 6 shows that the
presence of a thin SiN layer (121, 141) on both crystallographic
orientations results in substantially the same initial structure of
thin silicon oxide (122, 142), shown with the same cross hatching
that grows into a final thickness 125, 145. Even though the SiN is
completely converted into silicon oxide, the initial structure of
the oxide repeats itself during the subsequent oxidation of the
different crystal planes. It is this ability of the oxidation to
remember the initial oxide structure and/or the ability to
reproduce that is referred to as the "memory" effect.
[0036] Referring now to FIG. 1A, there is illustrated an exploded
view of a vertical MOS transistor according to the invention. An
aperture 20 has been etched in silicon substrate 10, having sides
(referred to as North and North-West) that have the <110> and
<100> crystal orientation, respectively. No attempt has been
made to represent the actual angle between the crystal planes
(45.degree.), which is indicated more realistically in the top view
of FIG. 1B. Speckled areas 32 denote doped areas that will be the
upper electrode of a transistor. Area 36 denotes the corresponding
lower electrode and numeral 34 denotes the silicon area that will
be the transistor body. A corresponding body area is behind the N
face of aperture 20. A polysilicon plug 25 is shown as displaced
from the aperture for clarity in presentation. In operation, poly
25 will fill the aperture and be the transistor gate. Gate oxide 12
and 14 complete the transistor and have been prepared according to
the invention, so that the difference in thickness of the two oxide
layers is about 1%.
[0037] The invention has been illustrated with reference to the
<100> and <110> planes for convenience. It has been
found that oxide growth on other planes, such as <111> is
also the same as on the <100> and <110> planes.
[0038] Those skilled in the art will be aware that such a
transistor can be used in a DRAM cell or in a logic structure
employing stacked transistors.
[0039] While the invention has been described in terms of a single
preferred embodiment, those skilled in the art will recognize that
the invention can be practiced in various versions within the
spirit and scope of the following claims.
* * * * *