Hegde; Suryanarayan G.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hegde; Suryanarayan G..The latest application filed is for "self-aligned planar double-gate transistor structure".

Company Profile

0.13.13

Hegde; Suryanarayan G. - Hollowville NY
Hegde, Suryanarayan G. - New York NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self-aligned planar double-gate transistor structure Grant 7,453,123 - Dokumaci , et al. November 18, 2	2008-11-18
Self-aligned Planar Double-gate Transistor Structure App 20080246090 - Dokumaci; Omer H. ; et al.	2008-10-09
Self-aligned Planar Double-gate Process By Self-aligned Oxidation App 20070138556 - Dokumaci; Omer H. ; et al.	2007-06-21
Self-aligned planar double-gate process by self-aligned oxidation Grant 7,205,185 - Dokumaci , et al. April 17, 2	2007-04-17
CMOS performance enhancement using localized voids and extended defects App 20050148134 - Dokumaci, Omer H. ; et al.	2005-07-07
CMOS performance enhancement using localized voids and extended defects Grant 6,878,978 - Dokumaci , et al. April 12, 2	2005-04-12
Self-aligned planar double-gate process by self-aligned oxidation App 20050059252 - Dokumaci, Omer H. ; et al.	2005-03-17
CMOS performance enhancement using localized voids and extended defects Grant 6,858,488 - Dokumaci , et al. February 22, 2	2005-02-22
Cmos Performance Enhancement Using Localized Voids And Extended Defects App 20050003605 - Dokumaci, Omer H. ; et al.	2005-01-06
CMOS performance enhancement using localized voids and extended defects App 20050003604 - Dokumaci, Omer H. ; et al.	2005-01-06
Self-aligned planar double-gate process by amorphization Grant 6,833,569 - Dokumaci , et al. December 21, 2	2004-12-21
CMOS performance enhancement using localized voids and extended defects Grant 6,803,270 - Dokumachi , et al. October 12, 2	2004-10-12
Cmos Performance Enhancement Using Localized Voids And Extended Defects App 20040166624 - Dokumaci, Omer H. ; et al.	2004-08-26
Self-aligned planar double-gate process by amorphization App 20040121549 - Dokumaci, Omer H. ; et al.	2004-06-24
Orientation Independent Oxidation Of Nitrided Silicon App 20040082197 - Gluschenkov, Oleg ; et al.	2004-04-29
Orientation independent oxidation of nitrided silicon Grant 6,727,142 - Gluschenkov , et al. April 27, 2	2004-04-27
Structure and method of providing reduced programming voltage antifuse App 20040051162 - Chidambarrao, Dureseti ; et al.	2004-03-18
Method of enhanced oxidation of MOS transistor gate corners Grant 6,514,843 - Dokumaci , et al. February 4, 2	2003-02-04
Method of forming variable oxide thicknesses across semiconductor chips App 20020197836 - Iyer, S. Sundar Kumar ; et al.	2002-12-26
Method of enhanced oxidation of MOS transistor gate corners App 20020160593 - Dokumaci, Omer ; et al.	2002-10-31
Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer Grant 6,329,704 - Akatsu , et al. December 11, 2	2001-12-11
Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer App 20010030333 - Akatsu, Hiroyuki ; et al.	2001-10-18
Application of excimer laser anneal to DRAM processing Grant 6,297,086 - Hegde , et al. October 2, 2	2001-10-02
Large area multiple-chip probe assembly and method of making the same Grant 5,977,787 - Das , et al. November 2, 1	1999-11-02
Sealed DASD having humidity control and method of making same Grant 5,392,177 - Chainer , et al. February 21, 1	1995-02-21
Capacitive measurement and control of the fly height of a recording slider Grant 4,931,887 - Hegde , et al. June 5, 1	1990-06-05

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