U.S. patent application number 10/635063 was filed with the patent office on 2004-02-12 for ferroelectric memory cell and corresponding manufacturing method.
This patent application is currently assigned to STMicroelectronics S.r.l.. Invention is credited to Casagrande, Giulio, Zambrano, Raffaele.
Application Number | 20040029298 10/635063 |
Document ID | / |
Family ID | 8243492 |
Filed Date | 2004-02-12 |
United States Patent
Application |
20040029298 |
Kind Code |
A1 |
Casagrande, Giulio ; et
al. |
February 12, 2004 |
Ferroelectric memory cell and corresponding manufacturing
method
Abstract
Presented is a memory cell integrated in a semiconductor
substrate that includes a MOS device connected in series to a
capacitive element. The MOS device has first and second conduction
terminals, and the capacitive element has a lower electrode covered
with a layer of a dielectric material and capacitively coupled to
an upper electrode. The MOS device is overlaid by at least one
metallization layer that is covered with at least one top
insulating layer. The capacitive element is formed on the top
insulating layer. The cell is unique in that the metallization
layer extends only between the MOS device and the capacitive
element.
Inventors: |
Casagrande, Giulio;
(Vignate, IT) ; Zambrano, Raffaele; (Catania,
IT) |
Correspondence
Address: |
SEED INTELLECTUAL PROPERTY LAW GROUP PLLC
701 FIFTH AVE
SUITE 6300
SEATTLE
WA
98104-7092
US
|
Assignee: |
STMicroelectronics S.r.l.
Agrate Brianza
IT
|
Family ID: |
8243492 |
Appl. No.: |
10/635063 |
Filed: |
August 5, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10635063 |
Aug 5, 2003 |
|
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09610311 |
Jul 5, 2000 |
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6627931 |
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Current U.S.
Class: |
438/3 ;
257/E21.657; 257/E21.664; 257/E27.088; 257/E27.104 |
Current CPC
Class: |
H01L 27/11502 20130101;
H01L 27/11507 20130101; H01L 27/10814 20130101; H01L 27/10885
20130101 |
Class at
Publication: |
438/3 |
International
Class: |
H01L 021/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 5, 1999 |
EP |
99830431.5 |
Claims
1. A method of fabricating a memory cell integrated in a
semiconductor substrate comprising: forming, on the semiconductor
substrate, a MOS device having first and second conduction
terminals; forming a first protective layers over the MOS device;
forming and patterning one or more metallization layers over the
MOS device; forming a second protective layer over the one or more
metallization layers;forming a capacitive element coupled in series
with the MOS device, including defining a lower electrode of the
capacitive element on the second protective layer, wherein the
capacitive element is formed after all of the one or more
metallization layers are formed and patterned without forming and
patterning any additional metallization layer after the capacitive
element is formed.
2. The method of claim 1 further comprising: forming a plurality of
contact vias through the first and second protective layers for
establishing an electrical connection between the lower electrode
of the capacitive element and at least one of the conduction
terminals of the MOS device.
3. The method of claim 2 wherein forming a capacitive element
comprises forming a ferroelectric capacitor having a ferroelectric
material layer for a dielectric layer.
4. The method of claim 1, wherein the one or more metallization
layers includes a first metallization layer formed on the first
protective layer and a second metallization layer formed between
the second protective layer and a third protective layer positioned
between the first and second protective layers, the method further
comprising forming a pad area from the second metallization layer
and electrically connecting the pad area to an upper electrode of
the capacitive element.
5. The method of claim 4 further comprising forming a flat on the
second protective layer and electrically coupling the flat to the
upper electrode of the capacitive element, and forming an
electrical contact that extends through the second protective layer
between the pad area to the flat.
6. The method of claim 1, wherein the one or more metallization
layers includes a first metallization layer formed on the first
protective layer and a second metallization layer formed between
the second protective layer and a third protective layer positioned
between the first and second protective layers, the method further
comprising: forming a pad area from the second metallization layer
before forming the second protective layer; and removing a portion
of the second protective layer from the pad area after the
capacitive element is formed, thereby exposing the pad area for an
external connection.
7. The method of claim 1, wherein the one or more metallization
layers includes a first metallization layer formed on the first
protective layer and a second metallization layer formed between
the second protective layer and a third protective layer positioned
between the first and second protective layers, the method further
comprising forming a third metallization layer on the second
protective layer before forming the lower electrode on the second
protective layer.
8. A method of making a memory cell integrated in a semiconductor
substrate, the method comprising: forming a MOS device; forming a
plurality of metallization layers including a first metallization
layer, the plurality of metallization layers overlaying the MOS
device; covering the first metallization layer with a top
insulating layer; forming a capacitive element on the top
insulating layer after forming the plurality of metallization
layers, the capacitive element having a lower electrode covered
with a layer of a dielectric material and capacitively coupled to
an upper electrode; forming a flat on the top insulating layer;
electrically connecting the flat to the upper electrode by a plate
line; and electrically connecting the flat to a pad of the first
metallization layer such that the memory cell may be driven through
the pad of the first metallization layer provided beneath the
capacitive element.
9. The method of claim 8 wherein the flat and the lower electrode
are formed by forming a conductive layer on the top insulating
layer and defining the flat and the lower electrode from the
conductive layer.
10. The method of claim 8, further comprising: forming a bottom
insulating layer on the substrate; and forming a plurality of
contact vias through the bottom and top insulating layers for
establishing an electrical connection between the lower electrode
of the capacitive element and a conduction terminal of the MOS
device.
11. The method of claim 8 wherein electrically connecting the flat
to the first metallization layer includes: forming a pad area from
the first metallization layer; and forming a contact that extends
through the top insulating layer and electrically connects the pad
area to the flat.
12. The method of claim 11, wherein the pad area is formed before
forming the top insulating layer, the method further comprising
removing a portion of the top protective layer from the pad area
after the capacitive element is formed, thereby exposing the pad
area for an external connection.
13. The method of claim 1, further comprising forming a second
metallization layer on the top protective layer and defining the
second metallization layer into a first pad area before forming the
lower electrode on the top insulating layer, and connecting the
first pad area to a second pad area formed from the first
metallization layer.
14. A method of forming a memory device integrated in a
semiconductor substrate, the method comprising: forming a matrix of
memory cells each including a MOS device and a capacitive element,
the matrix being formed by: forming a plurality of metallization
layers including a top metallization layer, the plurality of
metallization layers being formed between the MOS devices and the
capacitive elements of the memory cells; covering the top
metallization layer with a top insulating layer; forming the
capacitive elements on the top insulating layer after forming the
plurality of metallization layers, each capacitive element having a
lower electrode covered with a layer of a dielectric material and
capacitively coupled to an upper electrode; and forming a
conductive flat on the top insulating layer and outside of the
memory matrix; and electrically connecting the flat to the upper
electrodes of a plurality of the capacitive elements through a
plate line that forms and connects the upper electrodes of the
plurality of capacitive elements.
15. The method of claim 14, further comprising electrically
connecting the flat to a pad of the first metallization layer such
that the plurality of capacitive elements may be driven through the
pad of the first metallization layer provided beneath the
capacitive elements.
16. The method of claim 14 wherein the flat and the lower
electrodes of the capacitive elements are formed by forming a
conductive layer on the top insulating layer and defining the flat
and the lower electrodes from the conductive layer.
17. The method of claim 14, wherein forming the matrix of memory
cells includes: forming a bottom insulating layer on the substrate;
and forming a plurality of contact vias through the bottom and top
insulating layers for establishing an electrical connection between
the lower electrodes of the capacitive elements and conduction
terminals of the MOS devices.
18. The method of claim 14, further comprising: forming a pad area
from the first metallization layer; and forming a contact that
extends through the top insulating layer and electrically connects
the pad area to the flat.
19. The method of claim 18, wherein the pad area is formed before
forming the top insulating layer, the method further comprising
removing a portion of the top protective layer from the pad area
after the capacitive elements are formed, thereby exposing the pad
area for an external connection.
20. The method of claim 14, further comprising forming a second
metallization layer on the top protective layer and defining the
second metallization layer into a first pad area before forming the
lower electrodes on the top insulating layer, and connecting the
first pad area to a second pad area formed from the first
metallization layer.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of U.S. patent application
Ser. No. 09/610,311, filed Jul. 5, 2000, now pending, which
application is incorporated herein by reference in its
entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention relates to a ferroelectric memory cell, and a
method for its manufacture.
[0004] 2. Description of the Related Art
[0005] Electronic memory devices that include ferroelectric
components integrated on a semiconductor can include a number of
ferroelectric memory cells organized in a matrix form of rows and
columns, coupled by word and bit lines, respectively.
[0006] Each ferroelectric memory cell has a MOS transistor and a
ferroelectric capacitor.
[0007] Known processes for manufacturing such memory cells include,
after the MOS transistor is integrated in a semiconductor
substrate, covering the entire chip surface with an insulating
layer.
[0008] The ferroelectric capacitor is formed on top of this
insulating layer. The capacitor conventionally includes a lower
electrode of metal placed onto the insulating layer. A
ferroelectric material layer covers the lower electrode, and a
metal upper electrode is laid onto the ferroelectric layer.
[0009] An electrode of the ferroelectric capacitor is then
connected to a conduction electrode of the MOS transistor.
[0010] After forming the ferroelectric memory cell, the next
metallization layers are formed as necessary to complete the memory
circuit structure.
[0011] This solution has a number of drawbacks. The required
treatment for the provision of metallization levels can damage the
properties of the ferroelectric materials, and with it, the
performance of a ferroelectric memory cell.
[0012] A prior approach to attenuating this problem is described by
Amanuma in an article "Capacitor-on-Metal/Via-stacked-Plug (CMVP)
Memory Cell for 0.25 .mu.m CMOS Embedded FeRAM", published in
March, 1998 by IEEE and incorporated herein by this reference in
toto.
[0013] The article describes a ferroelectric memory cell comprising
a MOS transistor integrated in a semiconductor, the formation of
two metallization levels followed by the formation of a
ferroelectric capacitor, and ultimately the formation of a final
metallization layer.
[0014] Although achieving its objective, not even this solution is
devoid of drawbacks. The provision of a final metallization layer
after forming the ferroelectric capacitor results, in fact, in
degradation of the ferroelectric material.
[0015] Until now, no memory device or process for making a memory
device was available to provide a ferroelectric memory cell with
such construction and functional features as to retain the
ferroelectric characteristics of its component materials and
overcome the limitations and drawbacks that still beset prior art
ferroelectric memory devices.
BRIEF SUMMARY OF THE INVENTION
[0016] Embodiments of the invention provide a memory structure
which has at least one ferroelectric memory cell consisting of a
MOS transistor connected to a ferroelectric capacitor, wherein the
ferroelectric capacitor is formed after all the metallization
levels of the memory structure have been formed.
[0017] Presented is a memory cell integrated in a semiconductor
substrate that has a MOS device with an overlying metallization
layer. An insulating layer covers the metallization layer. Over the
insulating layer is formed a capacitive element having a lower
electrode covered with a layer of a dielectric material and
capacitively coupled to an upper electrode. The metallization layer
extends only between the MOS device and the lower electrode of the
capacitive element. Also presented is a method to make the cell
just described.
[0018] The invention relates, particularly but not exclusively, to
a non-volatile ferroelectric memory cell, and the description to
follow deals with this field of application for simplicity.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] FIG. 1 is an layout view showing a portion of a memory
matrix which has ferroelectric memory cells according to
embodiments invention.
[0020] FIG. 2 is a sectional view of FIG. 1 taken along line
II-II.
[0021] FIG. 3 is a sectional view of FIG. 1 taken along line
III-III.
[0022] FIG. 4 is a sectional view, similar to FIG. 2, of another
embodiment of the invention.
[0023] FIG. 5 is a sectional view of FIG. 1 taken along line
III-III, also showing an external contact area for the memory
matrix according to an embodiment of the invention.
[0024] FIG. 6 is a sectional view of FIG. 1 taken along line
III-III, also showing another embodiment of the external contact
for the memory matrix.
DETAILED DESCRIPTION OF THE INVENTION
[0025] Referring to the drawing views, a ferroelectric memory cell
according to an embodiment of the invention will now be
described.
[0026] FIG. 1 shows a portion of a memory matrix 1 including a
number of non-volatile ferroelectric memory cells 2, integrated on
a semiconductor substrate 3. These cells 2 are laid into rows and
columns, and are accessed through wordlines WL and bitlines BL.
Each of the memory cells lies at a junction of one wordline WL and
one bitline BL.
[0027] FIGS. 2 and 4 show a cross-sectional view of the
ferroelectric memory cells 2. Each ferroelectric memory cell 2
includes a MOS transistor 4 coupled to a capacitive element 5.
[0028] Each MOS transistor 4 has first and second conduction
terminals 6, which are formed in respective source and drain
regions of the substrate 3.
[0029] A gate (or control) electrode 7 of polysilicon overlies the
substrate region 3 between pairs of conduction terminals 6, and is
isolated from the substrate surface by a thin oxide layer.
[0030] The gate electrodes 7 of transistors 4 in the same row are
generally formed from polysilicon and coupled to a single word line
WL, also generally formed from polysilicon. Each word line
electrically interconnects the transistors 4 in the same row of the
matrix 1.
[0031] In this configuration, adjacent pairs of transistors 4 in
the same column BL have a conduction terminal 6 in common.
[0032] A protective insulating layer 8, such as an oxide doped with
boron and phosphorus (BPSG), is then formed over the entire
semiconductor surface. Respective openings are conventionally
provided through the protective insulating layer 8 aligned with the
conduction terminals 6, to form respective contacts 9.
[0033] Advantageously at this step, all the metallization levels
that are necessary to complete the circuit structure in which the
memory device 1 is integrated, are formed.
[0034] After the contact opening through the insulating layer 8 is
formed, a first metallization layer 10 is formed conventionally,
which is then patterned to provide specified electric
interconnections.
[0035] In particular, a number of pads 10a are formed at the
contacts 9 connected to the source terminal of the transistor 4,
and a plurality of pads 10b are formed at the drain of the
transistor 4 for connection to a respective bit line BL.
[0036] A second protective insulating layer 11 is subsequently
formed to cover the semiconductor surface. Respective openings are
provided through the insulating layer 11 aligned with the pads 10a
for conventionally producing respective contacts 12.
[0037] A second metallization layer 13 is formed and then patterned
to provide specified electric interconnections. In particular, a
number of pads 13a are formed aligned with the contacts 12 that are
connected to the source terminal of the transistor 4.
[0038] In a specially advantageous embodiment shown in FIG. 4,
auxiliary word lines WL1 are formed from this metallization layer
13.
[0039] These word lines WL1 are placed in contact, outside the
matrix 1, with the word lines WL which connect the gate electrodes
7 of the transistors 4.
[0040] In this way, the resistance of the polysilicon word lines WL
can be made lower than only using the wordlines WL themselves,
thereby making for faster response of the cells 2.
[0041] A third protective insulating layer 14 is subsequently
formed over the semiconductor surface.
[0042] Respective openings are provided through the insulating
layer 14 aligned with the pads 13a to enable the formation of
respective contacts 15.
[0043] Ferroelectric capacitors 5 are then provided at each MOS
transistor 4. Each ferroelectric capacitor 5 has a lower electrode
16 made of metal, e.g., of platinum, placed on the insulating layer
14 at the location of a respective contact 15.
[0044] In this particular embodiment, the lower electrode 16
advantageously overlaps the control electrode 7, at least
partially.
[0045] A layer 17 of a ferroelectric material covers the lower
electrode 16. Preferably, the ferroelectric material layer 12
covers the entire area occupied by the memory cells.
[0046] An upper electrode 18 of metal, e.g., of platinum, is then
formed on the ferroelectric material layer 17. This upper electrode
18 is so defined as to overlap each lower electrode 16, at least
partially.
[0047] Advantageously, the upper electrodes 18 of cells 2 in the
same matrix row are connected into a single line PL designated
"plate line", as shown in FIG. 1.
[0048] A passivation layer 19 is formed that covers the
semiconductor surface.
[0049] All of the metallization levels 10, 13 are included between
the MOS device and the lower electrode 16 of the capacitive element
5. In other words, no metallization levels are provided above the
electrodes 16, 18 of the capacitor 5.
[0050] As shown in FIG. 3, an end termination 20 can be provided,
outside the area of the memory matrix 1, which includes a pad 13b
formed from the second metallization layer 13.
[0051] This pad 13b is overlaid by an associated contact 15a which
is surrounded by the oxide layer 14. A flat 16a is formed, at the
contact 15a, from the platinum layer from which the first plates 16
of the capacitor 5 were formed.
[0052] This flat 16a is then covered with the plate line PL
interconnecting the upper plates 18 of the capacitors 5 in the same
row of the matrix 1.
[0053] This solution allows the outputs from the memory cells
(upper electrodes 18) to be driven and decoded through a
metallization level provided beneath the ferroelectric capacitor
5.
[0054] Shown in FIG. 5 is a first embodiment of a possible area of
connection to the output of the circuit. In this first embodiment,
a pad area 21 is formed from the second metallization level 13,
outside the matrix 1.
[0055] After the capacitors 5 are formed in the matrix 1 as
previously described, the top insulating layer 14 and the
passivation layer 19 are removed from a portion of the pad area 21
to provide for the connections to the output.
[0056] Another possible embodiment of this pad area is illustrated
in FIG. 6. In particular, after forming the protective insulating
layer 14, a pad area 21a is provided outside the matrix area by the
formation of a further metallization layer. Once this pad area 21a
is formed, the capacitors 5 are formed as previously described.
[0057] The passivation layer 19 deposited over the entire
semiconductor surface is then removed to produce the connections to
the output.
[0058] In summary, the memory cell 1 enables the ferroelectric
device to be fabricated after the last metallization layer has been
formed. Thus, the problems involved in integrating the
ferroelectric devices with standard CMOS fabrication processes have
been reduced substantially.
[0059] Changes can be made to the invention in light of the above
detailed description. In general, in the following claims, the
terms used should not be construed to limit the invention to the
specific embodiments disclosed in the specification and the claims,
but should be construed to include all methods and devices that are
in accordance with the claims. Accordingly, the invention is not
limited by the disclosure, but instead its scope is to be
determined by the following claims.
* * * * *