Casagrande; Giulio

Patent Applications and Registrations

Patent applications and USPTO patent grants for Casagrande; Giulio.The latest application filed is for "using a bit specific reference level to read a memory".

Company Profile

0.23.16

Casagrande; Giulio - Milan N/A IT
Casagrande; Giulio - US
Casagrande; Giulio - Vignate IT
Casagrande; Giulio - Vignate Milano
Casagrande; Giulio - Vignate MI
Casagrande; Giulio - Agrate Brianza IT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for using a bit specific reference level to read a phase change memory Grant 8,705,306 - Lowrey , et al. April 22, 2	2014-04-22
Using a Bit Specific Reference Level to Read a Memory App 20120287698 - Lowrey; Tyler ; et al.	2012-11-15
Using a bit specific reference level to read a memory Grant 8,259,525 - Lowrey , et al. September 4, 2	2012-09-04
Using A Bit Specific Reference Level To Read A Memory App 20120113711 - Lowrey; Tyler ; et al.	2012-05-10
Using a bit specific reference level to read a resistive memory Grant 8,116,159 - Lowrey , et al. February 14, 2	2012-02-14
Reading phase change memories Grant 8,098,512 - Parkinson , et al. January 17, 2	2012-01-17
Reading Phase Change Memories App 20110176358 - Parkinson; Ward D. ; et al.	2011-07-21
Reading phase change memories Grant 7,936,584 - Parkinson , et al. May 3, 2	2011-05-03
Streaming mode programming in phase change memories Grant 7,577,024 - Fackenthal , et al. August 18, 2	2009-08-18
Process for manufacturing an array of cells including selection bipolar junction transistors Grant 7,563,684 - Pellizzer , et al. July 21, 2	2009-07-21
Reading Phase Change Memories App 20090116281 - Parkinson; Ward D. ; et al.	2009-05-07
Reading phase change memories Grant 7,495,944 - Parkinson , et al. February 24, 2	2009-02-24
Streaming mode programming in phase change memories App 20080291719 - Fackenthal; Richard E. ; et al.	2008-11-27
Array of cells including a selection bipolar transistor and fabrication method thereof Grant 7,446,011 - Pellizzer , et al. November 4, 2	2008-11-04
Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof Grant 7,372,166 - Casagrande , et al. May 13, 2	2008-05-13
Array Of Cells Including A Selection Bipolar Transistor And Fabrication Method Thereof App 20070099347 - Pellizzer; Fabio ; et al.	2007-05-03
Array of cells including a selection bipolar transistor and fabrication method thereof Grant 7,135,756 - Pellizzer , et al. November 14, 2	2006-11-14
Reading phase change memories App 20060227592 - Parkinson; Ward D. ; et al.	2006-10-12
Using a bit specific reference level to read a memory App 20060221712 - Lowrey; Tyler ; et al.	2006-10-05
Method and system for controlling MRAM write current to reduce power consumption Grant 7,110,289 - Sin , et al. September 19, 2	2006-09-19
Writing circuit for a phase change memory device Grant 7,075,841 - Resta , et al. July 11, 2	2006-07-11
Magnetic memory cell with plural read transistors Grant 7,012,832 - Sin , et al. March 14, 2	2006-03-14
Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof App 20060049391 - Casagrande; Giulio ; et al.	2006-03-09
Process for manufacturing an array of cells including selection bipolar junction transistors App 20060049392 - Pellizzer; Fabio ; et al.	2006-03-09
Process for manufacturing an array of cells including selection bipolar junction transistors Grant 6,989,580 - Pellizzer , et al. January 24, 2	2006-01-24
Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof Grant 6,972,430 - Casagrande , et al. December 6, 2	2005-12-06
Writing circuit for a phase change memory device App 20050041498 - Resta, Claudio ; et al.	2005-02-24
Array of cells including a selection bipolar transistor and fabrication method thereof App 20040150093 - Pellizzer, Fabio ; et al.	2004-08-05
Process for manufacturing an array of cells including selection bipolar junction transistors App 20040130000 - Pellizzer, Fabio ; et al.	2004-07-08
Ferroelectric memory cell and corresponding manufacturing method App 20040029298 - Casagrande, Giulio ; et al.	2004-02-12
Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof App 20040012009 - Casagrande, Giulio ; et al.	2004-01-22
Ferroelectric memory cell and corresponding manufacturing method Grant 6,627,931 - Casagrande , et al. September 30, 2	2003-09-30
Semiconductor memory App 20020041534 - Gastaldi, Roberto ; et al.	2002-04-11
Voltage regulator for non-volatile semiconductor electrically programmable memory devices Grant 5,905,677 - Casagrande , et al. May 18, 1	1999-05-18
Byte erasable EEPROM fully compatible with a single power supply flash-EPROM process Grant 5,612,913 - Cappelletti , et al. March 18, 1	1997-03-18
Voltage regulator for non-volatile semiconductor memory devices Grant 5,576,990 - Camerlenghi , et al. November 19, 1	1996-11-19
Nonvolatile memory device with a high number of cycle programming endurance Grant 4,807,188 - Casagrande February 21, 1	1989-02-21
Device for the verification of memory cells on the basis of the threshold drop obtainable during writing Grant 4,802,166 - Casagrande , et al. January 31, 1	1989-01-31

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