| Patent | Date |
|---|
Contact structure for an integrated semiconductor device
Grant 7,052,985 - Zambrano , et al. May 30, 2 | 2006-05-30 |
Capacitor for semiconductor integrated devices
Grant 7,049,646 - Zambrano , et al. May 23, 2 | 2006-05-23 |
Device integrating a nonvolatile memory array and a volatile memory array
Grant 7,050,322 - Zambrano May 23, 2 | 2006-05-23 |
Method of forming a contact structure and a ferroelectric memory device
Grant 6,878,982 - Zambrano April 12, 2 | 2005-04-12 |
Method of fabricating a ferroelectric stacked memory cell
Grant 6,872,996 - Demange , et al. March 29, 2 | 2005-03-29 |
In-situ deposition and doping process for polycrystalline silicon layers and the resulting device
Grant 6,867,113 - Zambrano March 15, 2 | 2005-03-15 |
Process for selectively sealing ferroelectric capactive elements incorporated in semiconductor integrated non-volatile memory cells
App 20050009209 - Zambrano, Raffaele | 2005-01-13 |
Contact structure for an integrated semiconductor device
App 20040175927 - Zambrano, Raffaele ; et al. | 2004-09-09 |
Contact structure for semiconductor devices and corresponding manufacturing process
Grant 6,737,284 - Zambrano May 18, 2 | 2004-05-18 |
Contact structure for an integrated semiconductor device
Grant 6,734,565 - Zambrano , et al. May 11, 2 | 2004-05-11 |
Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip
Grant RE38,510 - Zambrano , et al. May 4, 2 | 2004-05-04 |
Method of fabricating a ferroelectric stacked memory cell
App 20040058493 - Demange, Nicolas ; et al. | 2004-03-25 |
Ferroelectric memory cell and corresponding manufacturing method
App 20040029298 - Casagrande, Giulio ; et al. | 2004-02-12 |
Method of forming a contact structure and a ferroelectric memory device
App 20040005725 - Zambrano, Raffaele | 2004-01-08 |
Method of fabricating a ferroelectric stacked memory cell
Grant 6,656,801 - Corvasce , et al. December 2, 2 | 2003-12-02 |
Contact structure for a ferroelectric memory device
Grant 6,633,060 - Zambrano October 14, 2 | 2003-10-14 |
Ferroelectric memory cell and corresponding manufacturing method
Grant 6,627,931 - Casagrande , et al. September 30, 2 | 2003-09-30 |
Device integrating a nonvolatile memory array and a volatile memory array
App 20030174531 - Zambrano, Raffaele | 2003-09-18 |
Capacitor for semiconductor integrated devices
App 20030146460 - Zambrano, Raffaele ; et al. | 2003-08-07 |
Contact structure for semiconductor devices and corresponding manufacturing process
App 20030082873 - Zambrano, Raffaele | 2003-05-01 |
Contact structure for an integrated semiconductor device
App 20020180054 - Zambrano, Raffaele ; et al. | 2002-12-05 |
Contact structure for a ferroelectric memory device
App 20020070397 - Zambrano, Raffaele | 2002-06-13 |
Contact structure for semiconductor devices and corresponding manufacturing process
App 20020050627 - Zambrano, Raffaele | 2002-05-02 |
ROM memory cell not decodable by visual inspection
App 20020034106 - Zambrano, Raffaele | 2002-03-21 |
Structure of a stacked memory cell, in particular a ferroelectric cell
App 20020008269 - Corvasce, Chiara ; et al. | 2002-01-24 |
Integrated circuit structure comprising capacitor element and corresponding manufacturing process
App 20010046735 - Zambrano, Raffaele | 2001-11-29 |
Structure of a stacked memory cell, in particular a ferroelectric cell
Grant 6,300,654 - Corvasce , et al. October 9, 2 | 2001-10-09 |
Integrated circuit structure comprising capacitor element and corresponding manufacturing process
Grant 6,294,798 - Zambrano September 25, 2 | 2001-09-25 |
Asymmetric MOS technology power device
App 20010001213 - Magri', Angelo ; et al. | 2001-05-17 |
Integrated circuit with improved electrostatic discharge protection circuitry
Grant 6,218,706 - Waggoner , et al. April 17, 2 | 2001-04-17 |
Integrated circuit with improved electrostatic discharge protection including multi-level inductor
Grant 6,034,400 - Waggoner , et al. March 7, 2 | 2000-03-07 |
Method for making high-frequency bipolar transistor
Grant 5,940,711 - Zambrano August 17, 1 | 1999-08-17 |
Metallization and wire bonding process for manufacturing power semiconductor devices
Grant 5,869,357 - Zambrano February 9, 1 | 1999-02-09 |
DMOS device structure, and related manufacturing process
Grant 5,838,042 - Zambrano November 17, 1 | 1998-11-17 |
Process for manufacturing a high-frequency bipolar transistor structure
Grant 5,804,486 - Zambrano , et al. September 8, 1 | 1998-09-08 |
Bonding pad for a semiconductor chip
Grant 5,773,899 - Zambrano June 30, 1 | 1998-06-30 |
Method of fabricating an integrated circuit with vertical bipolar power transistors and isolated lateral bipolar control transistors
Grant 5,679,587 - Zambrano October 21, 1 | 1997-10-21 |
Integrated structure active clamp for the protection of power devices against overvoltages, and manufacturing process thereof
Grant 5,654,225 - Zambrano August 5, 1 | 1997-08-05 |
Integrated circuit with vertical bipolar power transistors and isolated lateral bipolar control transistors
Grant 5,565,701 - Zambrano October 15, 1 | 1996-10-15 |
Integrated structure protection device for protecting logic-level power MOS devices against electro-static discharges
Grant 5,426,320 - Zambrano June 20, 1 | 1995-06-20 |
Manufacturing process for a monolithic integrated semiconductor device having multiple epitaxial layers with a low concentration of impurities
Grant 4,889,822 - Musumeci , et al. December 26, 1 | 1989-12-26 |
Process for the formation of a monolithic high voltage semiconductor device
Grant 4,780,430 - Musumeci , et al. October 25, 1 | 1988-10-25 |
| 