U.S. patent application number 10/436428 was filed with the patent office on 2003-11-06 for magnetoresistive memory (mram).
Invention is credited to Freitag, Martin, Gogl, Dietmar, Hoenigschmid, Heinz, Lammers, Stefan.
Application Number | 20030206461 10/436428 |
Document ID | / |
Family ID | 7662943 |
Filed Date | 2003-11-06 |
United States Patent
Application |
20030206461 |
Kind Code |
A1 |
Freitag, Martin ; et
al. |
November 6, 2003 |
Magnetoresistive memory (MRAM)
Abstract
The form of leads of a cell array of a multiplicity of magnetic
memory cells is optimized by deviating from a square cross section
of the leads in such a way that the magnetic field component of the
write currents lying in the cell array plane decreases sufficiently
rapidly with increasing distance from the crossover point. The cell
array is constructed from a matrix of the column leads and the row
leads.
Inventors: |
Freitag, Martin; (Munchen,
DE) ; Gogl, Dietmar; (Essex Junction, VT) ;
Hoenigschmid, Heinz; (Essex Junction, VT) ; Lammers,
Stefan; (South Burlington, VT) |
Correspondence
Address: |
LERNER AND GREENBERG, P.A.
POST OFFICE BOX 2480
HOLLYWOOD
FL
33022-2480
US
|
Family ID: |
7662943 |
Appl. No.: |
10/436428 |
Filed: |
May 12, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10436428 |
May 12, 2003 |
|
|
|
PCT/EP01/12622 |
Oct 31, 2001 |
|
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Current U.S.
Class: |
365/200 ;
257/E27.005 |
Current CPC
Class: |
B82Y 10/00 20130101;
G11C 11/16 20130101; H01L 27/222 20130101 |
Class at
Publication: |
365/200 |
International
Class: |
G11C 007/00 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 10, 2000 |
DE |
100 55 936.0 |
Claims
We claim:
1. A magnetoresistive memory, comprising: a cell array having a
matrix formed of leads including column leads and row leads and a
multiplicity of magnetic memory cells disposed at crossover points
of said column leads and said row leads, said magnetic memory cells
connected to said column leads and said row leads for conducting
read currents and write currents, in an event of a write operation,
magnetic fields generated by the write currents in said leads are
added at a random crossover point and thereby enable a
magnetization reverse of said magnetic memory cell, said leads
having a form optimized by deviating from a square cross section
thereof in such a way that a magnetic field component lying in a
cell array plane decreases sufficiently rapidly with increasing
distance from a respective crossover point.
2. The magnetoresistive memory according to claim 1, wherein said
leads have a flat rectangular cross-sectional shape.
3. The magnetoresistive memory according to claim 2, wherein said
flat rectangular cross-sectional shape has a width at least three
times greater than a given height.
4. The magnetoresistive memory according to claim 2, wherein said
leads have a laterally beveled rectangular cross-sectional
shape.
5. A magnetoresistive memory circuit, comprising: a semiconductor
substrate; a magnetoresistive memory disposed on said semiconductor
substrate, said magnetoresistive memory containing a cell array
having a matrix formed of leads including column leads and row
leads and a multiplicity of magnetic memory cells disposed at
crossover points of said column leads and said row leads, said
magnetic memory cells connected to said column leads and said row
leads for conducting read currents and write currents, in an event
of a write operation, magnetic fields generated by the write
currents in said leads are added at a random crossover point and
thereby enable a magnetization reverse of said magnetic memory
cell, said leads having a form optimized by deviating from a square
cross section thereof in such a way that a magnetic field component
lying in a cell array plane decreases sufficiently rapidly with
increasing distance from a respective crossover point; and a
circuit for generating the read currents and the write currents
integrated in said semiconductor substrate, said circuit having an
interconnect system and said leads integrated into said
interconnect system.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of copending
International Application No. PCT/EP01/12622, filed Oct. 31, 2001,
which designated the United States and was not published in
English.
BACKGROUND OF THE INVENTION
Field of the Invention
[0002] The invention relates to a magnetoresistive memory (MRAM)
having a multiplicity of magnetic memory cells, which are disposed
at the crossover points of a cell array constructed from a matrix
of column and row leads and are connected to the leads, which are
provided for conducting read and write currents. In which case, in
the event of a write operation, the magnetic fields generated by
the write currents in the respective leads are added at a random
crossover point and thereby enable a magnetization reverse of the
memory cell there.
[0003] Such a nonvolatile magnetic random access memory is
disclosed for example in Published, Non-Prosecuted German Patent
Application DE 198 07 361 A1, corresponding to U.S. Pat. No.
5,902,690.
[0004] At the present time, a multiplicity of digital memories are
being developed for read and write operations, which memories, as
memory chips having a high packing density on a magnetic basis
(MRAM), could, at least in some instances, replace the conventional
silicon chips (DRAM) as early as in a few years. The MRAM concept
provides for a respective bit of information, i.e. the logic zero
("0") or one ("1") state, to be stored in a memory cell which, in
principle, contains two magnetized layers, which may be magnetized
in a parallel or antiparallel manner with respect to one another.
The cell array of the multiplicity of memory cells is constructed
from a matrix of column and row leads. The leads contain conductive
materials and the actual memory cell is situated at the crossover
points of the leads. In order to achieve a change in the
magnetization of an individual memory cell, it is necessary to
generate a magnetic field, whose strength exceeds a specific
threshold value, selectively, that is to say as far as possible
only in direct proximity to a freely addressable crossover point.
The required magnetic field is achieved in accordance with the
customary selection mode only by vector addition of the two
magnetic fields that are associated with a specific crossover point
and are generated by the column and row leads.
[0005] While the outlined principles of the write operations in
MRAMs have already been known for a long time, more recently the
main emphasis of development has been on progressive read
operations. Present-day individual memory cells usually contain at
least two magnetic layers separated by an intermediate layer. The
individual memory cells are furthermore connected by a matrix of
leads. The leads not only serve, as described above, for generating
magnetic fields for write operations, rather they also conduct the
read currents for reading out the binary information present in the
individual memory cells. The magnetic storage state of a memory
cell is no longer determined by external magnetic sensors, but
rather by measurement of a property, namely of the resistance, at
the and through the memory cell itself. Nowadays consideration is
already being given to a plurality of different magnetoresistance
effects that are based in each case on different physical
principles of action. In practice, what is involved is, in the
context of changing the magnetization orientation from parallel to
antiparallel and vice versa, the realization of large changes in
resistance in the region of a few percent, for example by the giant
magnetoresistance effect (GMR) or the tunneling magnetoresistance
effect (TMR, other abbreviations are also common).
[0006] The general advantage of MRAMs over conventional
semiconductor memories consists in the persistent storage of the
information. Consequently, after the device in which the memory
cells are used has been switched off and switched on again, the
stored information is immediately available. Moreover, the
energy-expending refresh cycles in silicon chips could also be
obviated. In notebooks, for example, the "refresh" necessitates the
use of large and heavy rechargeable batteries.
[0007] What is problematic in the case of such MRAMs is that
magnetic leakage fields from outside the memory or from adjacent
cells can cause errors in the memory content if they have a
sufficient magnitude. Since magnetic fields can be localized only
with difficulty, there is the risk, particularly in the case of
high packing densities and, consequently, leads or memory cells
lying close together, that the magnetic state and thus the memory
content of adjacent cells will be altered.
[0008] Therefore, Published, Non-Prosecuted German Patent
Application DE 198 07 361 A1 cited in the introduction proposed a
shielding layer made of a material having a high permeability. The
shielding layer shields external magnetic leakage fields from the
coated memory cell and, moreover, concentrates the magnetic fields
generated by the write currents at the respective memory cell onto
the memory cell, so that a lower current intensity is required to
generate a total magnetic field sufficient for writing.
SUMMARY OF THE INVENTION
[0009] It is accordingly an object of the invention to provide a
magnetoresistive memory that overcomes the above-mentioned
disadvantages of the prior art devices of this general type.
[0010] With the foregoing and other objects in view there is
provided, in accordance with the invention, a magnetoresistive
memory. The magnetoresistive memory contains a cell array having a
matrix formed of leads including column leads and row leads and a
multiplicity of magnetic memory cells disposed at crossover points
of the column leads and the row leads. The magnetic memory cells
are connected to the column leads and the row leads for conducting
read currents and write currents. In an event of a write operation,
magnetic fields generated by the write currents in the leads are
added at a random crossover point and thereby enable a
magnetization reverse of the magnetic memory cell. The leads have a
form optimized by deviating from a square cross section thereof in
such a way that a magnetic field component lying in a cell array
plane decreases sufficiently rapidly with increasing distance from
a respective crossover point.
[0011] It is an aim of the present invention to configure a
magnetoresistive memory (MRAM) of the type mentioned in the
introduction in such a way as to produce, without complicated
interventions in the fabrication sequence, a controlled, in
particular greater, localization of the magnetic field at the
respective memory cell, which can thus be addressed with higher
selectivity. Moreover, the intention is to be able to generate the
magnetic fields as far as possible with a relatively low current
intensity.
[0012] In the case of a magnetoresistive memory (MRAM) of the type
mentioned in the introduction, the aim is achieved according to the
invention by virtue of the fact that the form of the leads is
optimized by deviation from a square cross section thereof in such
a way that the magnetic field component lying in the cell array
plane decreases sufficiently rapidly with increasing distance from
the crossover point.
[0013] Since the use of leads with an approximately square cross
section for the construction of an MRAM has been taken as a basis
heretofore, the invention is now based on the idea of generating
magnetic fields that are localized to a greater extent than
heretofore from the outset by optimizing the form of the leads,
also resulting at the same time in possibilities for optimizing the
required current intensity relative to the demanded threshold value
strength and selectivity of the magnetic field.
[0014] According to the invention, the new memory structures can be
integrated onto the customary wafers e.g. by thin-film technology
and optical lithography, a CMOS circuit known per se, for example,
on the MRAM chip controlling the read and write operations.
Accordingly, the leads of the memory cells are realized by special
interconnects made of Cu which are disposed for example between the
penultimate and last wiring planes. In terms of the compatibility
with the rest of the interconnect system and with regard to
properties such as simple producibility or high current-carrying
capacity, (approximately) square interconnect cross sections are
actually appropriate, but according to the invention a departure is
made from these in the direction of a rectangular cross section
flattened to a sufficiently great extent.
[0015] A particularly advantageous refinement of the MRAM according
to the invention consists in using leads having an extremely flat
or thin cross section, thereby resulting at the same time in a
higher selectivity and lower switching currents. This enables
smaller drive circuits and, consequently, also a smaller chip area,
less electromigration and lower power consumption. More
specifically, the flat rectangular cross-sectional shape has a
width at least three times greater than a given height.
Alternatively, the leads can have a laterally beveled rectangular
cross-sectional shape.
[0016] With the foregoing and other objects in view there is
provided, in accordance with the invention, a magnetoresistive
memory circuit. The magnetoresistive memory circuit contains a
semiconductor substrate and a magnetoresistive memory disposed on
the semiconductor substrate. The magnetoresistive memory contains a
cell array having a matrix formed of leads including column leads
and row leads and a multiplicity of magnetic memory cells disposed
at crossover points of the column leads and the row leads. The
magnetic memory cells connected to the column leads and the row
leads for conducting read currents and write currents. In an event
of a write operation, magnetic fields generated by the write
currents in the leads are added at a random crossover point and
thereby enable a magnetization reverse of the magnetic memory cell.
The leads have a form optimized by deviating from a square cross
section thereof in such a way that a magnetic field component lying
in a cell array plane decreases sufficiently rapidly with
increasing distance from a respective crossover point. A circuit
for generating the read currents and the write currents is
integrated in the semiconductor substrate. The circuit has an
interconnect system and the leads are integrated into the
interconnect system.
[0017] Other features which are considered as characteristic for
the invention are set forth in the appended claims.
[0018] Although the invention is illustrated and described herein
as embodied in a magnetoresistive memory (MRAM), it is nevertheless
not intended to be limited to the details shown, since various
modifications and structural changes may be made therein without
departing from the spirit of the invention and within the scope and
range of equivalents of the claims.
[0019] The construction and method of operation of the invention,
however, together with additional objects and advantages thereof
will be best understood from the following description of specific
embodiments when read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1 is a diagrammatic, perspective plan view of a
simplified illustration of part of an MRAM matrix in accordance
with the invention;
[0021] FIG. 2 is a graph showing calculation principles for the
magnetic field components with indication of a system of
coordinates;
[0022] FIG. 3 is a graph showing a profile of the magnetic field
strength as a function of a distance x from a center of a lead for
an MRAM in accordance with the prior art and also an idealized
profile;
[0023] FIG. 4 is a graph showing a profile of the magnetic field
strength as a function of the distance x from the center of the
lead for an MRAM in accordance with the prior art and also for two
embodiments of an MRAM in accordance with the invention; and
[0024] FIG. 5 is a graph showing in an identical illustration to
that in FIG. 4, the profile of the magnetic field strength for two
further embodiments of the MRAM in accordance with the
invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0025] Referring now to the figures of the drawing in detail and
first, particularly, to FIG. 1 thereof, there is shown a
configuration containing 3.times.3 memory cells 1 and 2, which are
connected by three row leads 3, also called word lines, and by
associated column leads 4 (only two leads are illustrated for
simplification), also called bit lines. The individual memory cells
1 and 2 may be constructed for example in each case from an upper
soft-magnetic layer 5, a lower hard-magnetic layer 6 and a tunnel
oxide 7, e.g. Al.sub.2O.sub.3, lying in between. The arrows in the
two lower memory cells of the foremost column indicate with their
parallel or antiparallel magnetization the logic states "1" and "0"
of these two memory cells.
[0026] A lead form optimization according to the invention is based
on the calculation of the associated magnetic field in a manner
dependent on a cross-sectional form. First, the magnetic field of a
conductor (ideally thin and of infinite length) through which
current flows is calculated, this being relatively simple to
determine. The following holds true for a magnitude of a magnetic
field B at a distance R from the center point of the lead: B=cI/R,
where I is the current and C is a constant. The direction of the
magnetic field vector can be determined using the so-called "right
hand" rule.
[0027] In accordance with the system of coordinates shown in FIG.
2, the z direction is chosen such that the current runs out from
the paper plane perpendicularly to the observer. The X-axis can be
imagined to run on the top-side of the lead. For the magnetization
state of an MRAM memory cell, almost exclusively the magnetic field
component in the cell array or wafer plane, that is to say in this
case the x-direction, is now important (on account of the
demagnetization factors) on the thin magnetic layer. The equations
for the magnetic field component B.sub.x can then be established,
see FIG. 2, and subsequently also be calculated for an extended
(non-idealized) conductor. The splitting of a real conductor having
a square cross section (approximately 0.25 .mu.m.times.0.25 .mu.m)
into 5.times.5 "ideal" conductors is indicated in FIG. 3, at the
bottom, it being necessary computationally to effect averaging over
all the individual magnetic field components B.sub.x.
[0028] Using the example of a known square lead having the
dimensions 0.25 .mu.m.times.0.25 .mu.m, FIG. 3 shows the associated
real curve 8 of the profile of the magnetic field component B.sub.x
(assumptions: I=2.5 mA; y=10 nm). As can be seen, outside the lead
considered, e.g. at x=.+-.0.25 .mu.m, that is to say in the
intermediate region with respect to the adjacent lead, there is
still a leakage field 9 of approximately 4 Oe, which, in accordance
with the profile of the real curve 8, falls only relatively slowly
toward zero even as the distance x increases still further. What is
important in any event is that the magnetic field component B.sub.x
directly above the lead reaches a value that is greater than the
switching value. This value can be determined for example from the
hysteresis curves of the tunnel element. Furthermore, the magnetic
field component B.sub.x beside the lead, that is to say already in
the immediate vicinity around the crossover point, should have
values that are as small as possible, significantly below the
switching threshold. This leads to the ideal curve 10 of the
magnetic field component B.sub.x depicted in FIG. 3, which falls
perpendicularly at the sides.
[0029] The calculations now show that the steepest possible fall in
the magnetic field component B.sub.x is not fulfilled optimally for
a conductor that is cross-sectionally square, but is fulfilled
increasingly better for a lead cross section that is flattened in
terms of the thickness, as illustrated in FIG. 4. FIG. 4 shows, in
particular, a curve 11 corresponding to an extremely flat lead 12;
the conductor cross section has decreased significantly (the
rectangle of the cross section has a width at least three times
greater than its height). However, larger field components are
generated in the x direction compared with a square cross section
13, see the associated curve 14, so that, as indicated in FIG. 4,
lower switching currents can be used. The generated slopes of the
curve 11 and of the middle curve, corresponding to the middle cross
section shown, have a significantly steeper profile than in the
case of the known square cross section (curve 14), so that better
selectivity and, at the same time, lower switching currents are
achieved.
[0030] All the considerations with regard to the magnetic field
component B.sub.x initially apply to an individual lead 3 or 4, but
can readily be extended to the vector addition of the two magnetic
fields, if appropriate also to configurations with more than two
write lines.
[0031] FIG. 5 shows the results of the calculations of the curves
for flat (thin) and additionally beveled or for trapezoidal lead
cross sections. The result for the trapezoidal cross section 15
(curve 16) shows the association of lower switching current
together with an only slightly impaired selectivity. The result in
the case of the beveled cross section 17 (curve 18) is a very
slightly improved selectivity together with a higher switching
current. The curve 19, which is shown light in the illustration in
FIG. 5, corresponds to the cross section 20 there, or the middle
cross section in FIG. 4. The difference in the amplitude of the
curve 19 with respect to the middle curve in FIG. 4 results from
the higher current intensity of 2.5 mA in FIG. 5, which are chosen
as a basis of comparison for the more extensively modified cross
sections 15 and 17.
* * * * *