U.S. patent application number 10/346536 was filed with the patent office on 2003-07-24 for field effect transistor structure with partially isolated source/drain junctions and methods of making same.
Invention is credited to Chau, Robert S., McFadden, Robert S., Morrow, Patrick, Murthy, Anand S..
Application Number | 20030136985 10/346536 |
Document ID | / |
Family ID | 23885131 |
Filed Date | 2003-07-24 |
United States Patent
Application |
20030136985 |
Kind Code |
A1 |
Murthy, Anand S. ; et
al. |
July 24, 2003 |
Field effect transistor structure with partially isolated
source/drain junctions and methods of making same
Abstract
A microelectronic structure includes at least one source/drain
terminal of a first conductivity type that is partially isolated
from a region of semiconductor material of a second conductivity
type. In a further aspect of the invention, a process for forming a
microelectronic structure, such as a MOSFET, having at least one
source/drain terminal of a first conductivity type that is
partially isolated from a region of semiconductor material of a
second conductivity type includes forming a recess having a
surface, forming a dielectric material over a portion of the
surface of the recess, and back-filling the recess to from a
source/drain terminal.
Inventors: |
Murthy, Anand S.;
(Beaverton, OR) ; Chau, Robert S.; (Beaverton,
OR) ; Morrow, Patrick; (Portland, OR) ;
McFadden, Robert S.; (Portland, OR) |
Correspondence
Address: |
Edwin H. Taylor
Blakely, Sokoloff, Taylor & Zafman LLP
Seventh Floor
12400 Wilshire Boulevard
Los Angeles
CA
90025-1030
US
|
Family ID: |
23885131 |
Appl. No.: |
10/346536 |
Filed: |
January 16, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10346536 |
Jan 16, 2003 |
|
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09474836 |
Dec 30, 1999 |
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6541343 |
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Current U.S.
Class: |
257/288 ;
257/408; 257/E21.43; 257/E21.431; 257/E29.021; 438/300; 438/301;
438/423; 438/524 |
Current CPC
Class: |
H01L 29/66636 20130101;
H01L 29/66628 20130101; H01L 29/0653 20130101 |
Class at
Publication: |
257/288 ;
257/408; 438/300; 438/301; 438/524; 438/423 |
International
Class: |
H01L 029/76; H01L
029/94; H01L 031/062; H01L 021/336 |
Claims
What is claimed is:
1. A method of forming a source/drain terminal, comprising: masking
a portion of a semiconductor surface; forming a recess in the
semiconductor surface, adjacent to the masked portion, the recess
having a bottom portion and a side portion; implanting ions into
the bottom portion; and selectively forming an undoped silicon
layer disposed at least partially within the recess.
2. The method of claim 1, wherein masking a portion of the
semiconductor surface comprises forming a gate electrode having
multi-layer sidewall spacers and a barrier layer superjacent the
gate electrode, wherein the barrier layer comprises silicon
oxynitride.
3. The method of claim 2, wherein the gate electrode comprises
polysilicon and the barrier layer further comprises silicon
dioxide.
4. The method of claim 1, wherein forming a recess comprises plasma
etching for approximately 15 seconds, in a parallel plate plasma
reactor having a plate spacing of approximately 0.8 cm, a pressure
of approximately 475 mT, an RF power of approximately 300 W, a Cl
flow rate of 150 sccm, and a He flow rate of approximately 100
sccm.
5. The method of claim 4, wherein implanting ions comprises
implanting nitrogen.
6. The method of claim 1, wherein implanting ions comprises
implanting carbon.
7. A method of forming a source/drain terminal, comprising: masking
a portion of the semiconductor surface; forming a recess in the
semiconductor surface adjacent to the masked portion, the recess
having a bottom portion and a side portion; forming a dielectric
material over the bottom portion of the recess such that the side
portion of the recess is substantially exposed; and selectively
forming a layer comprising silicon, beginning at the side portion
of the recess and extending laterally away from the side
portion.
8. The method of claim 7, wherein masking a portion of the
semiconductor surface comprises forming a gate electrode having
sidewall spacers and a barrier layer superjacent the gate
electrode.
9. The method of claim 8, wherein the gate electrode comprises
polysilicon; the sidewall spacers comprise an oxide layer and a
nitride layer; and the barrier layer comprises silicon
oxynitride.
10. The method of claim 7, wherein forming a recess comprises
plasma etching for approximately 15 seconds, in a parallel plate
plasma reactor having a plate spacing of approximately 0.8 cm, a
pressure of approximately 475 mT, an RF power of approximately 300
W, a Cl flow rate of 150 sccm, and a He flow rate of approximately
100 sccm.
11. The method of claim 7, wherein the dielectric material
comprises silicon nitride.
12. The method of claim 7, wherein the dielectric material
comprises silicon carbide.
13. The method of claim 10, wherein forming a dielectric material
over the bottom portion of the recess comprises forming a
morphologically nonconformal silicon nitride layer, the layer
covering the bottom portion of the recess and the side portion of
the recess, and wherein a portion of the layer covering the bottom
portion of the recess is thicker and denser than a portion of the
layer covering the side portion of the recess.
14. The method of claim 13, further comprising removing the portion
of the layer covering the side portion of the recess.
15. The method of claim 14, wherein removing comprises etching in
trimix.
16. The method of claim 7, further comprising, prior to selectively
forming a layer comprising silicon, cleaning the recess in an
SF.sub.6 plasma.
17. A microelectronic structure, comprising: a substrate comprising
a first crystalline material of a first conductivity type the
substrate having at least one recessed portion, the at least one
recessed portion having a bottom surface and a side surface; an
insulating layer disposed on the bottom portion surface; and a
second, substantially crystalline, material having a second
conductivity type disposed superjacent the insulating material and
adjacent a second portion of the substrate wherein the second
material substantially fills the at least one recess.
18. The structure of claim 17, wherein the first crystalline
material is silicon, and the insulating layer comprises a material
selected from the group consisting of silicon nitride and silicon
carbide.
19. The structure of claim 18, wherein the second material
comprises a material selected from the group consisting of silicon
and silicon germanium.
Description
REFERENCE TO RELATED APPLICATION
[0001] This application claims priority to U.S. application Ser.
No. 09/474,836, filed Dec. 30, 1999.
FIELD OF THE INVENTION
[0002] The trend of integrating more functions on a single
substrate while operating at ever higher frequencies has existed in
the semiconductor industry for many years. These higher operating
frequencies are generally made possible by advances in both
semiconductor manufacturing and digital systems design and
architecture.
[0003] Improvements in semiconductor manufacturing technology that
lead to improved operating frequencies are generally related to
improvements in the electrical characteristics of circuit elements,
such as transistors and capacitors, and the structures used to
interconnect the various circuit elements.
[0004] More particularly, one way to realize gains in the operating
frequency characteristics of integrated circuits includes reducing
parasitic capacitance. Parasitic capacitance tends to slow down the
operation of integrated circuits because more current is required
to charge and discharge the parasitic capacitors and therefore more
time is required to drive various circuit nodes to the desired
voltage. A significant amount of parasitic capacitance in
integrated circuits exists in the junction capacitance associated
with field effect transistors typically found on an integrated
circuit.
[0005] What is needed is a field effect transistor structure having
source/drain terminals with reduced junction capacitance. What is
further needed is a method of manufacturing such a structure.
SUMMARY OF THE INVENTION
[0006] Briefly, a microelectronic structure includes at least one
source/drain terminal of a first conductivity type that is
partially isolated from a region of semiconductor material of a
second conductivity type.
[0007] In a further aspect of the invention, a process for forming
a microelectronic structure having at least one source/drain
terminal of a first conductivity type that is partially isolated
from a region of semiconductor material of a second conductivity
type includes forming a recess having a surface, forming a
dielectric material over a portion of the surface of the recess,
and back-filling the recess to form a source/drain terminal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 is a schematic cross-section of a conventional
MOSFET.
[0009] FIG. 2 is a schematic cross-section showing the structure of
a partially completed MOSFET with recesses formed adjacent to the
sidewall spacers and nitrogen implanted into the bottom portion of
the recesses.
[0010] FIG. 3 is a schematic cross-section showing the structure of
FIG. 2, after a selective silicon epi formation operation fills the
recesses and the implanted nitrogen has been annealed.
[0011] FIG. 4 is a schematic cross-section showing the structure of
a partially completed MOSFET with recesses formed adjacent to the
sidewall spacers and silicon nitride formed over the bottom and
side surfaces of the recesses.
[0012] FIG. 5 is a schematic cross-section showing the structure of
FIG. 4, after an etching operation removes silicon nitride from
side surface of the recesses.
[0013] FIG. 6 is a schematic cross-section showing the structure of
FIG. 3, after back-filling of the recesses.
[0014] FIG. 7 is a schematic cross-section showing the structure of
FIG. 6, after excess silicon nitride is removed from the MOSFET
structure.
DETAILED DESCRIPTION
[0015] Overview
[0016] Conventional source/drain junction formation is accomplished
by one or more ion implantation operations that are generally
self-aligned to the gate electrode, or alternatively, aligned to
sidewall spacers that are adjacent to the gate electrode. In such a
process, ions of a first conductivity type (p- or n-) are implanted
into a semiconductor material of a second conductivity type (n- or
p-). A capacitance between the two nodes represented by the
different conductivity types arises at their junction and is a
function of the width of the depletion region formed at the
junction. The width of the depletion region may be affected by
various conditions including but not limited to, the materials
used, the concentrations of those materials, an externally supplied
voltage, if any, applied across the junction, and so on. In typical
circuit applications these capacitances are undesirable and are
often referred to as parasitic capacitances.
[0017] In order to reduce the parasitic junction capacitance,
various structures have been used wherein the source/drain material
is formed on an insulating layer, such as silicon dioxide. A
disadvantage of such structures is that they generally tend to
create a floating body terminal in a MOSFET because the channel
region is completely isolated from the well (or bulk
semiconductor).
[0018] Embodiments of the present invention provide partial
isolation of the source/drain terminal from the well (or bulk
semiconductor) while leaving the channel region, i.e., the body
terminal, electrically coupled to the well (or bulk semiconductor)
rather than floating.
[0019] More particularly, source/drain terminals in accordance with
the present invention include a dielectric layer, such as, for
example, silicon nitride, disposed between a portion of the
source/drain terminal and the well (or bulk semiconductor). In one
illustrative embodiment of a process in accordance with the present
invention, at least one recess having a surface is formed in a
substrate, self-aligned to a gate electrode, nitrogen is implanted,
self-aligned to the gate electrode, into a portion of the surface
of the recess, an epitaxial silicon layer is then formed to
back-fill the recess and a high temperature anneal is performed. In
an alternative illustrative embodiment of a process in accordance
with the present invention, at least one recess having a bottom
surface and a side surface is formed self-aligned to a gate
electrode; a silicon nitride layer is formed over the top and sides
of the gate electrode and over the bottom and side surfaces of the
recess with the nitride layer being thicker and denser on the
bottom surface than on the side surface; the nitride is removed
from at least the side surface of the recess thereby exposing a
portion of the substrate, and an semiconductor layer is formed
extending laterally outward from the exposed side surface to
back-fill the recess. It should be understood, that although the
illustrative embodiments above are described in connection with
various operations being self-aligned to the gate electrode, this
should also be taken to include being self-aligned to sidewall
spacers which are commonly used adjacent to the gate electrode of a
MOSFET.
[0020] Terminology
[0021] The terms, chip, integrated circuit, monolithic device,
semiconductor device or component, microelectronic device or
component, and similar terms and expressions are often used
interchangeably in this field. The present invention is applicable
to all the above as they are generally understood in the field.
[0022] Epitaxial layer refers to a layer of single crystal
semiconductor material.
[0023] The term "gate" is context sensitive and can be used in two
ways when describing integrated circuits. As used herein, gate
refers to the insulated gate terminal of a three terminal FET when
used in the context of transistor circuit configuration, and refers
to a circuit for realizing an arbitrary logical function when used
in the context of a logic gate. A FET can be viewed as a four
terminal device when the semiconductor body is considered.
[0024] Polycrystalline silicon is a nonporous form of silicon often
formed by chemical vapor deposition from a silicon source gas, or
other methods, and has a structure that contains crystallites or
domains with large-angle grain boundaries, twin boundaries, or
both. Polycrystalline silicon is often referred to in this field as
polysilicon, or sometimes more simply as poly.
[0025] Source/drain terminals refer to the terminals of a FET,
between which conduction occurs under the influence of an electric
field, subsequent to the inversion of the semiconductor surface
under the influence of an electric field resulting from a voltage
applied to the gate terminal. Source/drain terminals are typically
formed in a semiconductor substrate and have a conductivity type
(i.e., p-type or n-type) that is the opposite of the conductivity
type of the substrate. Sometimes, source/drain terminals are
referred to as junctions. Generally, the source and drain terminals
are fabricated such that they are geometrically symmetrical.
Source/drain terminals may include extensions, sometimes referred
to as tips, which are shallower than other portions of the
source/drain terminals. The tips typically extend toward the
channel region of a FET, from the main portion of the source/drain
terminal. With geometrically symmetrical source and drain terminals
it is common to simply refer to these terminals as source/drain
terminals, and this nomenclature is used herein. Designers often
designate a particular source/drain terminal to be a "source" or a
"drain" on the basis of the voltage to be applied to that terminal
when the FET is operated in a circuit.
[0026] Substrate, as used herein, refers to the physical object
that is the basic workpiece that is transformed by various process
operations into the desired microelectronic configuration. A
substrate may also be referred to as a wafer. Wafers, may be made
of semiconducting, non-semiconducting, or combinations of
semiconducting and non-semiconducting materials.
[0027] The term vertical, as used herein, means substantially
perpendicular to the surface of a substrate.
[0028] A cross-sectional view of a conventional FET is shown in
FIG. 1. A gate electrode 102 is disposed superjacent a gate
dielectric layer 104, which in turn is disposed superjacent a
semiconductor substrate 101. Sidewall spacers 106 are disposed
adjacent to the stack formed by gate dielectric 104 and gate
electrode 102. Source/drain terminals 108 are disposed, adjacent to
sidewall spacers 106, in substrate 101. Although a variety of
materials may be used, it is typical to have substrate 101 be
silicon, gate dielectric 104 be an oxide of silicon, gate electrode
102 be polysilicon, and sidewall spacers be an insulator such as
silicon nitride or silicon dioxide.
[0029] Still referring to FIG. 1, it will be appreciated that
source/drain terminals 108 are normally reversed biased with
respect to substrate 101. The reversed biased junctions act as
voltage variable capacitors since the width of the depletion region
associated with a reversed biased junction is a function of the
voltage across the junction. In addition to the capacitance
associated with these junctions, there is also a leakage current
that is associated with the junctions. Reducing both the parasitic
junction capacitance and reducing the reverse-biased junction
leakage current leads to higher performance circuits.
[0030] Additionally, source/drain terminals 108 of the conventional
FET of FIG. 1, are susceptible to alpha particle induced soft
errors. In operation, charge is often stored at the capacitor which
is formed by the reversed-biased source/drain junction. Alpha
particles from the environment frequently strike the substrate,
passing through the substrate and generating carriers. The carriers
may then migrate towards the charged source/drain junctions and
affect the voltage at those nodes by changing the amount of stored
charge. This phenomenon is sometimes referred to "zapping". As
source/drain terminals 108 are reduced in size by manufacturers to
increase integration density, the smaller source/drain terminals
are able to store correspondingly less charge and are therefore
correspondingly more susceptible to the effects of zapping.
Protecting these nodes from zapping by isolating them from alpha
particle induced carriers is desirable.
[0031] Referring to FIGS. 2-3, a first illustrative embodiment of
the present invention is described. As shown in FIG. 2, a wafer is
processed in known ways to form one or more regions of
semiconductor material 201 isolated by shallow trench isolation
(STI) structures 210, wherein gate dielectric layer 208 is formed
on the surface of semiconductor material 201, gate electrodes 202
are formed superjacent gate dielectric layer 208, and sidewall
spacers 206 are typically formed adjacent to the sidewall of gate
electrode 202. In embodiments of the present invention, sidewall
spacers 206 are typically multi-layer spacers. Multi-layer spacers
may have an oxide layer formed from tetraethylorthosilicate (TEOS)
and an overlying nitride layer formed from bis-(tertiary
butylamino) silane (BTBAS). As further shown in FIGS. 2 and 3, a
barrier layer 204 is formed over the top surface of gate electrode
202. Barrier layer 204 may be an anti-reflective coating sometimes
referred to as BARC (bottom anti-reflective coating). Barrier layer
204 may be a silicon nitride layer, however any suitable material
may be used that substantially prevents the polysilicon of gate
electrode 202 from being etched during a process operation in which
recesses 212 are formed in semiconductor material 201. For example,
barrier layer 204 may be, but is not required to be, an oxide layer
with an overlying oxynitride layer. Barrier layer 204 may also be
referred to as a poly hardmask.
[0032] Subsequent to the formation of the gate electrode and STI
structures described above, the surface of semiconductor material
201 is etched, self-aligned to the gate electrode and sidewall
spacers so as to form trenches, or recesses 212. In the
illustrative embodiment, substrate 201 is a silicon wafer, gate
dielectric layer 208 is a silicon dioxide layer, and gate electrode
202 is formed from polysilicon. Although gate dielectric layer 208
is typically a thin layer of oxidized silicon, the thickness and
chemical make-up of this gate insulator layer may be varied within
the scope of the invention.
[0033] Recesses 212 are formed in the wafer at locations where the
source/drain terminals of the FET will be located. The recesses are
formed by the anisotropic etch of the wafer. The etch chemistry and
conditions are preferably chosen such that the etch is highly
selective and preferentially etches the wafer rather than the side
wall spacers or the gate dielectric layer. In the illustrative
embodiment, wherein the wafer is silicon, the gate dielectric is an
oxide of silicon, the gate electrode is polysilicon and the side
wall spacers are silicon nitride, an plasma etch conditions such as
a pressure of 400 to 550 mT, a power of 250 to 350 Watts, a plate
spacing of 0.5 to 1 cm, a He flow rate of 50 to 150 sccm , and
Cl.sub.2 flow rate of 100 to 200 sccm.
[0034] After the recesses are formed a cleaning operation is
performed on the recess surfaces. A recess surface clean in
accordance with the present invention may include a plasma etch in
a parallel plate type plasma etcher such as those available from
LAM Research Corp. Plasma conditions for the recess surface clean
may include a pressure in the range of 200 to 300 mT, power in the
range of 25 to 100 W, a plate spacing in the range of 0.8 to 1.5
cm, a He flow rate in the range of 200 to 350 sccm, and an SF6 flow
rate in the range of 25 to 100 sccm. In one embodiment, the
pressure is approximately 250 mT, the power is approximately 50 W,
the plate spacing is approximately 1.1 cm, the He flow rate is
approximately 150 sccm, and the SF.sub.6 flow rate is approximately
50 sccm.
[0035] Those skilled in the art and having the benefit of this
disclosure will recognize that the operations and structures shown
and described herein, are compatible with various field oxide
isolation architectures. Examples of field oxide isolation
architectures include shallow trench isolation regions in a surface
of a substrate, and the older local oxidation of silicon (LOCOS),
which typically formed non-planarized oxide isolation regions.
[0036] Still referring to FIG. 2, an N.sub.2 implant operation is
performed into recesses 212, self-aligned to the gate electrode and
the sidewall spacers. The N.sub.2 implant operation is typically
carried out with a dose ranging from 5.times.10.sup.15 to
1.times.10.sup.17 atoms/cm.sup.2, and an energy ranging from 10 KeV
to 20 KeV. That is, gate electrode 204 and sidewall spacers 206 act
as barriers to the ion implantation operation. Subsequent to the
implant operation, the wafer is cleaned with an ex situ HF dip.
Alternatively, this cleaning operation may be achieved by an
SF.sub.6 dry etch.
[0037] Alternatively, carbon may be implanted rather than nitrogen.
In such an alternative process, a silicon carbide layer is formed
as a dielectric to isolate a portion of the source/drain
terminal.
[0038] Referring to FIG. 3, recesses 212 are back-filled using a
selective Si deposition process. That is, the recesses are filled
with silicon that is substantially single crystal, and takes its
crystal orientation from that of the semiconductor material 201
which is found at the surface of recesses 212. In one embodiment of
the present invention, the selective Si deposition takes place in a
reaction chamber, such as an ASM Epsilon 2000 single wafer GVD
reactor, at a temperature between 700.degree. C. and 900.degree.
C., with an H.sub.2 carrier gas with a flow rate between 10 and 40
slm, a dichlorosilane (SiH.sub.2Cl.sub.2) flow rate between 25 and
200 sccm, an HCl flow rate between 10 and 200 sccm, a pressure
between 5 Torr and 200 Torr, and a susceptor rotation of
approximately 35 rpm. In one embodiment, the deposition temperature
is approximately 800.degree. C., the H.sub.2 carrier gas with a
flow rate is approximately 20 slm, the SiH.sub.2Cl.sub.2 flow rate
is approximately 120 sccm, the HCl flow rate is approximately 45
sccm, the pressure is approximately 20 Torr, and a deposition rate
is achieved wherein a 1000 angstrom film can be deposited in
approximately 6 minutes.
[0039] Subsequent to the selective Si deposition process, layer 204
is removed, typically by a wet etch. Subsequently, a high
temperature anneal is performed, resulting in, among other things,
the formation of a silicon nitride layer 215 below the source/drain
terminals. Of course, if carbon rather than nitrogen was implanted,
region 215 would be a silicon carbide layer. Various other known
operations may then be performed in order to form the various
levels of interconnection and insulation typically found on
integrated circuits.
[0040] An alternative embodiment of the present invention is
described in conjunction with FIGS. 4-7. This embodiment differs
from that described in connection with FIGS. 2-3, in that rather
than implanting and annealing nitrogen to form a silicon nitride
layer, a deposition operation is performed to provide a silicon
nitride layer to partially isolate source/drain terminals from the
substrate in which they are formed. More particularly, FIG. 4 shows
a wafer which has been processed in known ways to form one or more
regions of semiconductor material 201 isolated by shallow trench
isolation structures 210, wherein gate dielectric layer 208 is
formed on the surface of semiconductor material 201, gate
electrodes 202 are formed superjacent gate dielectric layer 208,
and sidewall spacers 206 are typically formed adjacent to the
vertical sidewalls of gate electrode 202. As further shown in FIG.
4, a barrier layer 204 is formed over the top surface of gate
electrode 202. Barrier layer 204 may be an anti-reflective coating
such silicon nitride, however any suitable material may be used
that substantially prevents the polysilicon of gate electrode 202
from being etched during a process operation in which recesses 212
are formed in semiconductor material 201. Subsequent to the
formation of the gate electrode and STI structures described above,
the surface of semiconductor material 201 is etched, self-aligned
to the gate electrode and sidewall spacers so as to form trenches
212. In the illustrative embodiment, substrate 201 is a silicon
wafer, gate dielectric layer 208 is a silicon dioxide layer, and
gate electrode 202 is formed from polysilicon.
[0041] Still referring to FIG. 4, approximately 30-50 nm of silicon
nitride is directionally deposited over the surface of the wafer,
including the surface of recess 212, the top and side surfaces of
sidewall spacers 206, and the top surface of barrier layer 204
using plasma enhanced chemical vapor deposition (PECVD). This
deposition operation results in a silicon nitride layer 402 along
the bottom portion of recess 212 and a silicon nitride layer 403
along the side portion of recess 212 and the side surface of
sidewall spacers 206, as shown in FIG. 4. Silicon nitride layer 402
is thicker and denser than silicon nitride layer 403. In an
exemplary process in accordance with the present invention, a
morphologically non-conformal nitride layer is deposited in a
parallel plate direct plasma reactor, such as, for example, an
Applied Materials Precision 5000. A wafer is placed on a grounded
ceramic susceptor (i.e., the lower plate) and RF power (13.54 MHz)
is delivered to an upper gas distribution plate. The plate spacing
is in the range of 6 to 15 mm, the pressure is in the range of 500
to 1500 mtorr, the temperature is in the range of 250.degree. C. to
350.degree. C., the RF power is in the range of 0.02 to 0.5
W/cm.sup.2, the SiH.sub.4 flow rate is in the range of 0.01 to 0.05
sccm, the NH.sub.3 flow rate is in the range of 0.1 to 0.3 sccm,
and the N.sub.2 flow rate is in the range of 2 to 6 sccm. In one
embodiment, the plate spacing is approximately 12 mm, the pressure
is approximately 700 mTorr, the temperature is approximately
275.degree. C., the RF power is approximately 0.16 W/cm2, the
SiH.sub.4 flow rate is approximately 0.02 sccm, the NH.sub.3 flow
rate is approximately 0.2 sccm, and the N.sub.2 flow rate is
approximately 3 sccm. A nominal nitride layer thickness of 500
angstroms is used in one embodiment of the present invention.
[0042] Referring to FIG. 5, it can be seen silicon nitride 403 has
been removed from the side portion of recesses 212 and the side of
sidewall spacer 206, while silicon nitride 402 remains along the
bottom surface of recess 212. Silicon nitride 403 is typically
removed by etching in trimix for approximately 2 minutes. This
permits the removal of nitride 403 while still leaving between
approximately 20 nm to 30 nm of nitride 402 on the bottom portion
of recess 212. Following the dip in trimix, the wafer is cleaned
with a short SF.sub.6 dry etch so as to prepare the side portion of
recess 212 for selective silicon deposition. The side portion of
recesses 212 act as a nucleation site for a subsequent operation in
which recesses 212 is back-filled.
[0043] Referring to FIG. 6, recesses 212 are back-filled with a
selective silicon deposition layer 408 that is grown laterally
outward from the side portion of recess 212. This lateral formation
produces source/drain regions 408 that are partially isolated from
the substrate by silicon nitride layer 402. Typically, source/drain
regions 408 are formed of undoped silicon. Those skilled in the art
and having the benefit of this disclosure will appreciate that
alternative embodiments of the present invention may include the
formation of source/drain regions 408 that may be either p-type or
n-type depending on the gas mixtures used during the selective
silicon deposition.
[0044] FIG. 7 shows the structure of FIG. 6, after the remaining
portions of silicon nitride 403 overlying the top surface of
sidewall spacers 206, and silicon nitride 402 overlying the top
surface of barrier layer 204 have been removed by etching. As is
further shown in FIG. 7, barrier layer 204 is also removed from the
top surface of gate electrode 202. At this point the structure of
FIG. 7, may be subjected to conventional processing steps such as,
for example, the formation silicides on the exposed surfaces of the
source/drains and gate electrode.
[0045] Those skilled in the art and having the benefit of this
disclosure will recognize that the operations and structures
disclosed above are applicable to the formation of both n-channel
FETs (NFETs) and p-channel FETs (PFETs). NFETs and PFETs are
structurally similar, however the relative placement of p-type and
n-type dopants is different. That is, a PFET includes p-type
source/drain terminals in an n-type body, and an NFET includes
n-type source/drain terminals in a p-type body.
[0046] Conclusion
[0047] Embodiments of the present invention provide microelectronic
structures such as, for example, FETs with source/drain terminals
partially isolated from the well (or bulk semiconductor) in which
they are formed. Further embodiments of the present invention
provide methods of manufacturing such structures.
[0048] FETs embodying the present invention include back-filled
source/drain terminals. In one embodiment, the doping concentration
of the source/drain terminals can be controlled by controlling the
gas mixture, temperature, and pressure, in a reaction chamber.
Formation of the source/drain terminals in this way also provides
increased margin for the thermal budget of the manufacturing
process, since a high temperature operation is not required to
activate the dopants, or to thermally in-diffuse the dopants into
the tip portion of the source/drain terminals.
[0049] An advantage of particular embodiments of the present
invention is that parasitic junction capacitance is reduced.
[0050] An further advantage of particular embodiments of the
present invention is that charge leakage pathways between a
source/drain terminal and the substrate are reduced.
[0051] A still further advantage of particular embodiments of the
present invention is that source/drain terminals are provided with
a measure of shielding from carriers generated by events such as
alpha particle strikes.
[0052] It will be understood by those skilled in the art having the
benefit of this disclosure that many design choices are possible
within the scope of the present invention. For example, structural
parameters, including but not limited to, gate insulator thickness,
gate insulator materials, gate electrode thickness, sidewall spacer
material, inter-layer dielectric material, isolation trench depth,
and S/D and well doping concentrations may all be varied from that
shown or described in connection with the illustrative embodiments.
The dielectric layer formed at the bottom portion of the recesses
may be silicon carbide rather than silicon nitride. Also, the
operation of forming recesses and back filling with material may be
repeated to tailor the shape and doping profile of the source/drain
terminals.
[0053] It will be understood that various other changes in the
details, materials, and arrangements of the parts and steps which
have been described and illustrated may be made by those skilled in
the art having the benefit of this disclosure without departing
from the principles and scope of the invention as expressed in the
subjoined Claims.
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