| Patent | Date |
|---|
Non-silicon N-type And P-type Stacked Transistors For Integrated Circuit Devices
App 20220310605 - Dewey; Gilbert ; et al. | 2022-09-29 |
Backside source/drain replacement for semiconductor devices with metallization on both sides
Grant 11,444,166 - Glass , et al. September 13, 2 | 2022-09-13 |
Transistors stacked on front-end p-type transistors
Grant 11,437,405 - Dewey , et al. September 6, 2 | 2022-09-06 |
Microelectronic Assemblies
App 20220278057 - Elsherbini; Adel A. ; et al. | 2022-09-01 |
Metallization structures for stacked device connectivity and their methods of fabrication
Grant 11,430,814 - Lilak , et al. August 30, 2 | 2022-08-30 |
Self-aligned local interconnects
Grant 11,424,160 - Lilak , et al. August 23, 2 | 2022-08-23 |
Microelectronic Assemblies
App 20220254754 - ELSHERBINI; Adel A. ; et al. | 2022-08-11 |
Transistor Cells Including A Deep Via Lined With A Dielectric Material
App 20220254681 - Morrow; Patrick ; et al. | 2022-08-11 |
Vertically stacked finFETs and shared gate patterning
Grant 11,404,319 - Lilak , et al. August 2, 2 | 2022-08-02 |
Heterogeneous Ge/III-V CMOS transistor structures
Grant 11,398,479 - Rachmady , et al. July 26, 2 | 2022-07-26 |
Microelectronic assemblies
Grant 11,393,777 - Elsherbini , et al. July 19, 2 | 2022-07-19 |
Stacked transistors with Si PMOS and high mobility thin film transistor NMOS
Grant 11,393,818 - Dewey , et al. July 19, 2 | 2022-07-19 |
Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices
Grant 11,387,238 - Dewey , et al. July 12, 2 | 2022-07-12 |
Stacked transistor architecture including nanowire or nanoribbon thin film transistors
Grant 11,380,684 - Dewey , et al. July 5, 2 | 2022-07-05 |
Pedestal fin structure for stacked transistor integration
Grant 11,374,004 - Lilak , et al. June 28, 2 | 2022-06-28 |
Microelectronic assemblies
Grant 11,348,897 - Elsherbini , et al. May 31, 2 | 2022-05-31 |
Stacked transistor structures with asymmetrical terminal interconnects
Grant 11,342,227 - Lilak , et al. May 24, 2 | 2022-05-24 |
Transistor cells including a deep via lined wit h a dielectric material
Grant 11,328,951 - Morrow , et al. May 10, 2 | 2022-05-10 |
Wrap-around Source/drain Method Of Making Contacts For Backside Metals
App 20220140127 - MORROW; Patrick ; et al. | 2022-05-05 |
Wrap-around Source/drain Method Of Making Contacts For Backside Metals
App 20220140128 - MORROW; Patrick ; et al. | 2022-05-05 |
Fabrication And Use Of Through Silicon Vias On Double Sided Interconnect Device
App 20220130803 - MUELLER; Brennen K. ; et al. | 2022-04-28 |
Stacked Transistors
App 20220123128 - MORROW; Patrick ; et al. | 2022-04-21 |
Isolation Walls For Vertically Stacked Transistor Structures
App 20220115372 - LILAK; Aaron ; et al. | 2022-04-14 |
Vertically Stacked Transistor Devices With Isolation Wall Structures Containing An Electrical Conductor
App 20220102246 - LILAK; Aaron D. ; et al. | 2022-03-31 |
Forksheet Transistor Architectures
App 20220102346 - LILAK; Aaron D. ; et al. | 2022-03-31 |
Backside Contact Structures And Fabrication For Metal On Both Sides Of Devices
App 20220069094 - MORROW; Patrick ; et al. | 2022-03-03 |
Wrap-around source/drain method of making contacts for backside metals
Grant 11,264,493 - Morrow , et al. March 1, 2 | 2022-03-01 |
Semiconductor diodes employing back-side semiconductor or metal
Grant 11,264,405 - Morrow , et al. March 1, 2 | 2022-03-01 |
Vertically stacked transistor devices with isolation wall structures containing an electrical conductor
Grant 11,257,738 - Lilak , et al. February 22, 2 | 2022-02-22 |
Stacked transistors
Grant 11,257,929 - Morrow , et al. February 22, 2 | 2022-02-22 |
Fabrication and use of through silicon vias on double sided interconnect device
Grant 11,251,156 - Mueller , et al. February 15, 2 | 2022-02-15 |
Vias In Composite Ic Chip Structures
App 20220037281 - Elsherbini; Adel ; et al. | 2022-02-03 |
Isolation walls for vertically stacked transistor structures
Grant 11,239,232 - Lilak , et al. February 1, 2 | 2022-02-01 |
Forksheet transistor architectures
Grant 11,239,236 - Lilak , et al. February 1, 2 | 2022-02-01 |
Integrated Circuit Device With Crenellated Metal Trace Layout
App 20220028779 - Morrow; Patrick ; et al. | 2022-01-27 |
Stacked Forksheet Transistors
App 20210407999 - HUANG; Cheng-Ying ; et al. | 2021-12-30 |
Vertically Spaced Intra-level Interconnect Line Metallization For Integrated Circuit Devices
App 20210407895 - Lin; Kevin L. ; et al. | 2021-12-30 |
Vias in composite IC chip structures
Grant 11,205,630 - Elsherbini , et al. December 21, 2 | 2021-12-21 |
Backside contact structures and fabrication for metal on both sides of devices
Grant 11,201,221 - Morrow , et al. December 14, 2 | 2021-12-14 |
Composite Ic Chips Including A Chiplet Embedded Within Metallization Layers Of A Host Ic Chip
App 20210375830 - Elsherbini; Adel ; et al. | 2021-12-02 |
Vertically Stacked Transistors In A Fin
App 20210351078 - Lilak; Aaron D. ; et al. | 2021-11-11 |
Metallization Structures Under A Semiconductor Device Layer
App 20210343710 - Lilak; Aaron D. ; et al. | 2021-11-04 |
Integrated circuit device with crenellated metal trace layout
Grant 11,139,241 - Morrow , et al. October 5, 2 | 2021-10-05 |
Stacked Transistor Structures With Asymmetrical Terminal Interconnects
App 20210305098 - Lilak; Aaron ; et al. | 2021-09-30 |
Forksheet Transistor Architectures
App 20210296315 - LILAK; Aaron D. ; et al. | 2021-09-23 |
Apparatus With Multi-wafer Based Device And Method For Forming Such
App 20210280453 - Pancholi; Anup ; et al. | 2021-09-09 |
Systems and methods to reduce FinFET gate capacitance
Grant 11,107,924 - Lilak , et al. August 31, 2 | 2021-08-31 |
Metallization structures under a semiconductor device layer
Grant 11,107,811 - Lilak , et al. August 31, 2 | 2021-08-31 |
Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
Grant 11,094,672 - Elsherbini , et al. August 17, 2 | 2021-08-17 |
Bottom fin trim isolation aligned with top gate for stacked device architectures
Grant 11,075,202 - Lilak , et al. July 27, 2 | 2021-07-27 |
Vertically stacked transistors in a pin
Grant 11,075,119 - Lilak , et al. July 27, 2 | 2021-07-27 |
Gate-all-around Integrated Circuit Structures Having Removed Substrate
App 20210202696 - GUHA; Biswajeet ; et al. | 2021-07-01 |
Method, device and system to provide capacitance for a dynamic random access memory cell
Grant 11,049,861 - Lilak , et al. June 29, 2 | 2021-06-29 |
Pn-body-tied Field Effect Transistors
App 20210193802 - Lilak; Aaron D. ; et al. | 2021-06-24 |
Apparatus with multi-wafer based device and method for forming such
Grant 11,037,817 - Pancholi , et al. June 15, 2 | 2021-06-15 |
Apparatus with multi-wafer based device comprising embedded active devices and method for forming such
Grant 11,037,916 - Pancholi , et al. June 15, 2 | 2021-06-15 |
Integrated Circuit Device Structures And Double-sided Electrical Testing
App 20210175124 - RAO; Valluri R. ; et al. | 2021-06-10 |
Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability
Grant 11,011,537 - Lilak , et al. May 18, 2 | 2021-05-18 |
Multi-level Spin Logic
App 20210143819 - Manipatruni; Sasikanth ; et al. | 2021-05-13 |
Packaged device with a chiplet comprising memory resources
Grant 10,998,302 - Elsherbini , et al. May 4, 2 | 2021-05-04 |
Integrated Circuit Device With Back-side Inerconnection To Deep Source/drain Semiconductor
App 20210111115 - Morrow; Patrick ; et al. | 2021-04-15 |
Methods and apparatus to remove epitaxial defects in semiconductors
Grant 10,978,590 - Lilak , et al. April 13, 2 | 2021-04-13 |
Techniques For Revealing A Backside Of An Integrated Circuit Device, And Associated Configurations
App 20210104435 - SON; Il-Seok ; et al. | 2021-04-08 |
Vias In Composite Ic Chip Structures
App 20210098407 - Elsherbini; Adel ; et al. | 2021-04-01 |
Composite Ic Chips Including A Chiplet Embedded Within Metallization Layers Of A Host Ic Chip
App 20210098422 - Elsherbini; Adel ; et al. | 2021-04-01 |
Packaged Device With A Chiplet Comprising Memory Resources
App 20210098440 - Elsherbini; Adel ; et al. | 2021-04-01 |
Stacked Transistors With Si Pmos And High Mobility Thin Film Transistor Nmos
App 20210091080 - DEWEY; Gilbert ; et al. | 2021-03-25 |
Bottom Fin Trim Isolation Aligned With Top Gate For Stacked Device Architectures
App 20210074704 - Lilak; Aaron D. ; et al. | 2021-03-11 |
Backside Source/drain Replacement For Semiconductor Devices With Metallization On Both Sides
App 20210074823 - Glass; Glenn A. ; et al. | 2021-03-11 |
Multi-level spin logic
Grant 10,944,399 - Manipatruni , et al. March 9, 2 | 2021-03-09 |
Methods and apparatus for gettering impurities in semiconductors
Grant 10,937,665 - Lilak , et al. March 2, 2 | 2021-03-02 |
Iii-v Source/drain In Top Nmos Transistors For Low Temperature Stacked Transistor Contacts
App 20210057413 - DEWEY; Gilbert ; et al. | 2021-02-25 |
Vertical Integration Scheme And Circuit Elements Architecture For Area Scaling Of Semiconductor Devices
App 20210043755 - MEHANDRU; Rishabh ; et al. | 2021-02-11 |
Backside fin recess control with multi-HSI option
Grant 10,910,405 - Lilak , et al. February 2, 2 | 2021-02-02 |
Techniques for revealing a backside of an integrated circuit device, and associated configurations
Grant 10,896,847 - Son , et al. January 19, 2 | 2021-01-19 |
Metal on both sides with power distributed through the silicon
Grant 10,892,215 - Nelson , et al. January 12, 2 | 2021-01-12 |
Backside source/drain replacement for semiconductor devices with metallization on both sides
Grant 10,892,337 - Glass , et al. January 12, 2 | 2021-01-12 |
Integrated circuit device with back-side interconnection to deep source/drain semiconductor
Grant 10,886,217 - Morrow , et al. January 5, 2 | 2021-01-05 |
Stacked Trigate Transistors With Dielectric Isolation And Process For Forming Such
App 20200411511 - RACHMADY; Willy ; et al. | 2020-12-31 |
Sideways Vias In Isolation Areas To Contact Interior Layers In Stacked Devices
App 20200411430 - MANNEBACH; Ehren ; et al. | 2020-12-31 |
Stacked Source-drain-gate Connection And Process For Forming Such
App 20200411651 - MANNEBACH; Ehren ; et al. | 2020-12-31 |
Forming An Oxide Volume Within A Fin
App 20200411365 - HUANG; Cheng-Ying ; et al. | 2020-12-31 |
Devices With Air Gapping Between Stacked Transistors And Process For Providing Such
App 20200411639 - MANNEBACH; Ehren ; et al. | 2020-12-31 |
Sidewall Interconnect Metallization Structures For Integrated Circuit Devices
App 20200411433 - Lilak; Aaron ; et al. | 2020-12-31 |
Epitaxial Layer With Substantially Parallel Sides
App 20200411315 - HUANG; Cheng-Ying ; et al. | 2020-12-31 |
Device Including Air Gapping Of Gate Spacers And Other Dielectrics And Process For Providing Such
App 20200411660 - MANNEBACH; Ehren ; et al. | 2020-12-31 |
Integrated circuit structures
Grant 10,872,820 - Block , et al. December 22, 2 | 2020-12-22 |
Metallization Structures For Stacked Device Connectivity And Their Methods Of Fabrication
App 20200395386 - Lilak; Aaron D. ; et al. | 2020-12-17 |
Inverted staircase contact for density improvement to 3D stacked devices
Grant 10,861,870 - Lilak , et al. December 8, 2 | 2020-12-08 |
Backside Contact Structures And Fabrication For Metal On Both Sides Of Devices
App 20200381525 - MORROW; Patrick ; et al. | 2020-12-03 |
Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices
Grant 10,847,635 - Mehandru , et al. November 24, 2 | 2020-11-24 |
Non-silicon N-type And P-type Stacked Transistors For Integrated Circuit Devices
App 20200335501 - Dewey; Gilbert ; et al. | 2020-10-22 |
Methods of forming backside self-aligned vias and structures formed thereby
Grant 10,797,139 - Morrow , et al. October 6, 2 | 2020-10-06 |
Heterogeneous Ge/iii-v Cmos Transistor Structures
App 20200312846 - Rachmady; Willy ; et al. | 2020-10-01 |
Capacitance Reduction For Semiconductor Devices Based On Wafer Bonding
App 20200303238 - MANNEBACH; Ehren ; et al. | 2020-09-24 |
Backside contact structures and fabrication for metal on both sides of devices
Grant 10,784,358 - Morrow , et al. Sept | 2020-09-22 |
Stacked Transistors Having Device Strata With Different Channel Widths
App 20200295003 - Dewey; Gilbert W. ; et al. | 2020-09-17 |
Stacked Transistors With Different Crystal Orientations In Different Device Strata
App 20200295127 - Mannebach; Ehren ; et al. | 2020-09-17 |
Multi-layer silicon/gallium nitride semiconductor
Grant 10,763,248 - Dasgupta , et al. Sep | 2020-09-01 |
Microelectronic Assemblies
App 20200273839 - ELSHERBINI; Adel A. ; et al. | 2020-08-27 |
Vertically Stacked Transistor Devices With Isolation Wall Structures Containing An Electrical Conductor
App 20200273779 - LILAK; Aaron D. ; et al. | 2020-08-27 |
Stacked Transistors With Dielectric Between Channels Of Different Device Strata
App 20200266218 - Lilak; Aaron D. ; et al. | 2020-08-20 |
Self-aligned Local Interconnects
App 20200258778 - A1 | 2020-08-13 |
Vertical Diode In Stacked Transistor Architecture
App 20200258881 - A1 | 2020-08-13 |
3d Floating-gate Multiple-input Device
App 20200258894 - A1 | 2020-08-13 |
Backside contact resistance reduction for semiconductor devices with metallization on both sides
Grant 10,734,412 - Glass , et al. | 2020-08-04 |
Microelectronic Assemblies
App 20200235061 - Elsherbini; Adel A. ; et al. | 2020-07-23 |
Vertically Stacked Finfets & Shared Gate Patterning
App 20200235013 - Lilak; Aaron ; et al. | 2020-07-23 |
Multi-layer Silicon/gallium Nitride Semiconductor
App 20200227396 - DASGUPTA; Sansaptak W. ; et al. | 2020-07-16 |
Apparatus with multi-wafer based device comprising embedded active and/or passive devices and method for forming such
Grant 10,714,446 - Pancholi , et al. | 2020-07-14 |
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Bottom-up Oxidation Approach
App 20200219979 - RACHMADY; Willy ; et al. | 2020-07-09 |
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Multiple Bottom-up Oxidation Approache
App 20200219970 - Mannebach; Ehren ; et al. | 2020-07-09 |
Three Dimensional Integrated Circuits With Stacked Transistors
App 20200211905 - HUANG; Cheng-Ying ; et al. | 2020-07-02 |
Self-aligned Stacked Ge/si Cmos Transistor Structure
App 20200212038 - RACHMADY; Willy ; et al. | 2020-07-02 |
Silicon die with integrated high voltage devices
Grant 10,700,039 - Nelson , et al. | 2020-06-30 |
Transistors On Heterogeneous Bonding Layers
App 20200194570 - Jun; Kimin ; et al. | 2020-06-18 |
Vertical Memory Cells
App 20200194435 - LILAK; Aaron ; et al. | 2020-06-18 |
Backside Fin Recess Control With Multi-hsi Option
App 20200176482 - LILAK; Aaron D. ; et al. | 2020-06-04 |
High density memory architecture using back side metal layers
Grant 10,672,831 - Wang , et al. | 2020-06-02 |
Metallization Structures Under A Semiconductor Device Layer
App 20200161298 - Lilak; Aaron D. ; et al. | 2020-05-21 |
Metal on both sides with clock gated-power and signal routing underneath
Grant 10,658,291 - Nelson , et al. | 2020-05-19 |
Integrated Circuit Contact Structures
App 20200152750 - Morrow; Patrick ; et al. | 2020-05-14 |
Deep EPI enabled by backside reveal for stress enhancement and contact
Grant 10,636,907 - Lilak , et al. | 2020-04-28 |
Stacked Transistor Architecture Including Nanowire Or Nanoribbon Thin Film Transistors
App 20200105751 - Dewey; Gilbert ; et al. | 2020-04-02 |
Vertically Stacked Cmos With Upfront M0 Interconnect
App 20200098921 - RACHMADY; Willy ; et al. | 2020-03-26 |
Backside fin recess control with multi-hsi option
Grant 10,600,810 - Lilak , et al. | 2020-03-24 |
High Density Memory Architecture Using Back Side Metal Layers
App 20200043980 - Wang; Yih ; et al. | 2020-02-06 |
Integrated Circuit Device Structures And Double-sided Fabrication Techniques
App 20200035560 - BLOCK; Bruce ; et al. | 2020-01-30 |
Long channel MOS transistors for low leakage applications on a short channel CMOS chip
Grant 10,529,827 - Mehandru , et al. J | 2020-01-07 |
Pedestal Fin Structure For Stacked Transistor Integration
App 20200006340 - LILAK; AARON D. ; et al. | 2020-01-02 |
Transistors Stacked On Front-end P-type Transistors
App 20200006388 - DEWEY; Gilbert ; et al. | 2020-01-02 |
Interconnect Techniques For Electrically Connecting Source/drain Regions Of Stacked Transistors
App 20200006329 - LILAK; AARON D. ; et al. | 2020-01-02 |
Heterogeneous integration of ultrathin functional block by solid phase adhesive and selective transfer
Grant 10,522,510 - Jun , et al. Dec | 2019-12-31 |
Isolation Walls For Vertically Stacked Transistor Structures
App 20190393214 - LILAK; Aaron ; et al. | 2019-12-26 |
Stacked Thin Film Transistors
App 20190393249 - LILAK; Aaron ; et al. | 2019-12-26 |
Multi-level Spin Logic
App 20190386661 - Manipatruni; Sasikanth ; et al. | 2019-12-19 |
Techniques For Revealing A Backside Of An Integrated Circuit Device, And Associated Configurations
App 20190371666 - SON; Il-Seok ; et al. | 2019-12-05 |
Integrated circuit layout using library cells with alternating conductive lines
Grant 10,490,542 - Nelson , et al. Nov | 2019-11-26 |
Techniques for revealing a backside of an integrated circuit device, and associated configurations
Grant 10,490,449 - Son , et al. Nov | 2019-11-26 |
High density memory architecture using back side metal layers
Grant 10,483,321 - Wang , et al. Nov | 2019-11-19 |
Systems And Methods To Reduce Finfet Gate Capacitance
App 20190348535 - Lilak; Aaron D. ; et al. | 2019-11-14 |
Apparatus With Multi-wafer Based Device Comprising Embedded Active And/or Passive Devices And Method For Forming Such
App 20190348389 - Pancholi; Anup ; et al. | 2019-11-14 |
Back Side Processing Of Integrated Circuit Structures To Form Insulation Structure Between Adjacent Transistor Structures
App 20190341297 - LILAK; AARON D. ; et al. | 2019-11-07 |
Isolation structures for an integrated circuit element and method of making same
Grant 10,468,489 - Lilak , et al. No | 2019-11-05 |
Apparatus With Multi-wafer Based Device And Method For Forming Such
App 20190333803 - Pancholi; Anup ; et al. | 2019-10-31 |
Apparatus With Multi-wafer Based Device Comprising Embedded Active Devices And Method For Forming Such
App 20190333906 - Pancholi; Anup ; et al. | 2019-10-31 |
Vertically Stacked Transistors In A Pin
App 20190326175 - Lilak; Aaron D. ; et al. | 2019-10-24 |
Methods Of Forming Backside Self-aligned Vias And Structures Formed Thereby
App 20190326405 - Morrow; Patrick ; et al. | 2019-10-24 |
Methods and devices integrating III-N transistor circuitry with Si transistor circuitry
Grant 10,453,679 - Dasgupta , et al. Oc | 2019-10-22 |
Integrated Circuit Device With Crenellated Metal Trace Layout
App 20190312023 - Morrow; Patrick ; et al. | 2019-10-10 |
Multi-gate high electron mobility transistors and methods of fabrication
Grant 10,439,057 - Jun , et al. O | 2019-10-08 |
Metal On Both Sides With Power Distributed Through The Silicon
App 20190267316 - NELSON; Donald W. ; et al. | 2019-08-29 |
Metal on both sides of the transistor integrated with magnetic inductors
Grant 10,396,045 - Morrow , et al. A | 2019-08-27 |
Integrated Circuit Device With Back-side Inerconnection To Deep Source/drain Semiconductor
App 20190259699 - Morrow; Patrick ; et al. | 2019-08-22 |
Vertical Integration Scheme And Circuit Elements Architecture For Area Scaling Of Semiconductor Devices
App 20190252525 - MEHANDRU; Rishabh ; et al. | 2019-08-15 |
Methods of forming backside self-aligned vias and structures formed thereby
Grant 10,367,070 - Morrow , et al. July 30, 2 | 2019-07-30 |
Vertical channel transistors fabrication process by selective subtraction of a regular grid
Grant 10,361,090 - Jun , et al. | 2019-07-23 |
Vertical Interconnect Methods For Stacked Device Architectures Using Direct Self Assembly With High Operational Parallelization
App 20190221577 - LILAK; Aaron D. ; et al. | 2019-07-18 |
Backside Source/drain Replacement For Semiconductor Devices With Metallization On Both Sides
App 20190221649 - Glass; Glenn A. ; et al. | 2019-07-18 |
Stacked Transistors With Different Gate Lengths In Different Device Strata
App 20190196830 - Lilak; Aaron D. ; et al. | 2019-06-27 |
Methods And Apparatus To Remove Epitaxial Defects In Semiconductors
App 20190189795 - Lilak; Aaron D. ; et al. | 2019-06-20 |
Methods And Apparatus For Gettering Impurities In Semiconductors
App 20190189464 - Lilak; Aaron D. ; et al. | 2019-06-20 |
Inverted Staircase Contact For Density Improvement To 3d Stacked Devices
App 20190189635 - Lilak; Aaron ; et al. | 2019-06-20 |
Metal on both sides with power distributed through the silicon
Grant 10,325,840 - Nelson , et al. | 2019-06-18 |
Finfet Transistor With Channel Stress Induced Via Stressor Material Inserted Into Fin Plug Region Enabled By Backside Reveal
App 20190172950 - LILAK; Aaron D. ; et al. | 2019-06-06 |
Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices
Grant 10,304,946 - Mehandru , et al. | 2019-05-28 |
Backside Contact Resistance Reduction For Semiconductor Devices With Metallization On Both Sides
App 20190157310 - GLASS; GLENN A. ; et al. | 2019-05-23 |
Monolithic three-dimensional (3D) ICs with local inter-level interconnects
Grant 10,297,592 - Morrow , et al. | 2019-05-21 |
Metal On Both Sides With Clock Gated-power And Signal Routing Underneath
App 20190122985 - NELSON; Donald W. ; et al. | 2019-04-25 |
Semiconductor Diodes Employing Back-side Seimconductor Or Metal
App 20190096917 - Morrow; Patrick ; et al. | 2019-03-28 |
Partial layer transfer system and method
Grant 10,236,282 - Morrow , et al. | 2019-03-19 |
Transistor Cells Including A Deep Via Lined With A Dielectric Material
App 20190067091 - Morrow; Patrick ; et al. | 2019-02-28 |
Permanent Functional Carrier Systems And Methods
App 20190057950 - Mueller; Brennen K. ; et al. | 2019-02-21 |
Backside Fin Recess Control With Multi-hsi Option
App 20190027503 - LILAK; Aaron D. ; et al. | 2019-01-24 |
Metal on both sides with clock gated-power and signal routing underneath
Grant 10,186,484 - Nelson , et al. Ja | 2019-01-22 |
Metal On Both Sides Of The Transistor Integrated With Magnetic Inductors
App 20190006296 - MORROW; Patrick ; et al. | 2019-01-03 |
Methods And Devices Integrating Iii-n Transistor Circuitry With Si Transistor Circuitry
App 20190006171 - Dasgupta; Sansaptak ; et al. | 2019-01-03 |
Fabrication And Use Of Through Silicon Vias On Double Sided Interconnect Device
App 20180323174 - MUELLER; Brennen K. ; et al. | 2018-11-08 |
Stacked Transistors
App 20180315838 - MORROW; Patrick ; et al. | 2018-11-01 |
High Density Memory Architecture Using Back Side Metal Layers
App 20180286916 - Wang; Yih ; et al. | 2018-10-04 |
Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)
Grant 10,068,874 - Nelson , et al. September 4, 2 | 2018-09-04 |
Methods Of Forming Backside Self-aligned Vias And Structures Formed Thereby
App 20180248012 - Morrow; Patrick ; et al. | 2018-08-30 |
Techniques For Revealing A Backside Of An Integrated Circuit Device, And Associated Configurations
App 20180233409 - SON; Il-Seok ; et al. | 2018-08-16 |
Isolation Structures For An Integrated Circuit Element And Method Of Making Same
App 20180226478 - LILAK; Aaron D. ; et al. | 2018-08-09 |
Long Channel Mos Transistors For Low Leakage Applications On A Short Channel Cmos Chip
App 20180226492 - MEHANDRU; Rishabh ; et al. | 2018-08-09 |
Techniques for forming vertical transistor architectures
Grant 10,043,797 - Jun , et al. August 7, 2 | 2018-08-07 |
Metal On Both Sides With Power Distributed Through The Silicon
App 20180218973 - NELSON; Donald W. ; et al. | 2018-08-02 |
Method, Device And System To Provide Capacitance For A Dynamic Random Access Memory Cell
App 20180219012 - LILAK; Aaron ; et al. | 2018-08-02 |
Backside Contact Structures And Fabrication For Metal On Both Sides Of Devices
App 20180219075 - MORROW; Patrick ; et al. | 2018-08-02 |
Wrap-around Source/drain Method Of Making Contacts For Backside Metals
App 20180219090 - MORROW; Patrick ; et al. | 2018-08-02 |
Deep Epi Enabled By Backside Reveal For Stress Enhancement & Contact
App 20180212057 - LILAK; Aaron D. ; et al. | 2018-07-26 |
Planar heterogeneous device
Grant 10,014,374 - Jun , et al. July 3, 2 | 2018-07-03 |
Heterogeneous Integration Of Ultrathin Functional Block By Solid Phase Adhesive And Selective Transfer
App 20180151541 - JUN; Kimin ; et al. | 2018-05-31 |
Integrated Circuit Layout Using Library Cells With Alternating Conductive Lines
App 20180145063 - NELSON; Donald W. ; et al. | 2018-05-24 |
High electron mobility transistor fabrication process on reverse polarized substrate by layer transfer
Grant 9,935,191 - Jun , et al. April 3, 2 | 2018-04-03 |
Methods of forming buried vertical capacitors and structures formed thereby
Grant 9,818,751 - Baskaran , et al. November 14, 2 | 2017-11-14 |
Field effect transistor structure with abrupt source/drain junctions
Grant 9,793,373 - Murthy , et al. October 17, 2 | 2017-10-17 |
MONOLITHIC THREE-DIMENSIONAL (3D) ICs WITH LOCAL INTER-LEVEL INTERCONNECTS
App 20170287905 - Morrow; Patrick ; et al. | 2017-10-05 |
Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
Grant 9,761,514 - Ma , et al. September 12, 2 | 2017-09-12 |
Multi-gate High Electron Mobility Transistors And Methods Of Fabrication
App 20170229565 - JUN; Kimin ; et al. | 2017-08-10 |
Methods Of Forming Buried Vertical Capacitors And Structures Formed Thereby
App 20170221901 - Baskaran; Rajashree ; et al. | 2017-08-03 |
Methods of forming under device interconnect structures
Grant 9,721,898 - Morrow , et al. August 1, 2 | 2017-08-01 |
Field Effect Transistor Structure With Abrupt Source/drain Junctions
App 20170186855 - Murthy; Anand S. ; et al. | 2017-06-29 |
Monolithic three-dimensional (3D) ICs with local inter-level interconnects
Grant 9,685,436 - Morrow , et al. June 20, 2 | 2017-06-20 |
Methods of forming buried vertical capacitors and structures formed thereby
Grant 9,646,972 - Baskaran , et al. May 9, 2 | 2017-05-09 |
Field effect transistor structure with abrupt source/drain junctions
Grant 9,640,634 - Murthy , et al. May 2, 2 | 2017-05-02 |
Embedded Memory In Interconnect Stack On Silicon Die
App 20170077389 - NELSON; Donald W. ; et al. | 2017-03-16 |
Metal On Both Sides With Clock Gated-power And Signal Routing Underneath
App 20170077030 - NELSON; Donald W. ; et al. | 2017-03-16 |
High Electron Mobility Transistor Fabrication Process On Reverse Polarized Substrate By Layer Transfer
App 20170077281 - JUN; Kimin ; et al. | 2017-03-16 |
Silicon Die With Integrated High Voltage Devices
App 20170069597 - NELSON; Donald W. ; et al. | 2017-03-09 |
Method For Direct Integration Of Memory Die To Logic Die Without Use Of Thru Silicon Vias (tsv)
App 20170069598 - NELSON; Donald W. ; et al. | 2017-03-09 |
Heterogeneous layer device
Grant 9,590,051 - Jun , et al. March 7, 2 | 2017-03-07 |
Methods Of Forming Under Device Interconnect Structures
App 20170025355 - Morrow; Patrick ; et al. | 2017-01-26 |
Techniques For Forming Vertical Transistor Architectures
App 20170025412 - JUN; KIMIN ; et al. | 2017-01-26 |
Vertical Channel Transistors Fabrication Process By Selective Subtraction Of A Regular Grid
App 20170011929 - JUN; Kimin ; et al. | 2017-01-12 |
Methods of forming under device interconnect structures
Grant 9,490,201 - Morrow , et al. November 8, 2 | 2016-11-08 |
Substrate For Integrated Circuit Devices Including Multi-layer Glass Core And Methods Of Making The Same
App 20160322290 - Ma; Qing ; et al. | 2016-11-03 |
Debond interconnect structures
Grant 9,461,010 - Ma , et al. October 4, 2 | 2016-10-04 |
Heterogeneous Layer Device
App 20160247887 - JUN; KIMIN ; et al. | 2016-08-25 |
Planar Heterogeneous Device
App 20160247882 - JUN; KIMIN ; et al. | 2016-08-25 |
Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
Grant 9,420,707 - Ma , et al. August 16, 2 | 2016-08-16 |
Partial Layer Transfer System And Method
App 20160233206 - MORROW; PATRICK ; et al. | 2016-08-11 |
Methods Of Forming Buried Vertical Capacitors And Structures Formed Thereby
App 20160204110 - Baskaran; Rajashree ; et al. | 2016-07-14 |
MONOLITHIC THREE-DIMENSIONAL (3D) ICs WITH LOCAL INTER-LEVEL INTERCONNECTS
App 20160197069 - Morrow; Patrick ; et al. | 2016-07-07 |
Debond Interconnect Structures
App 20160133596 - Ma; Qing ; et al. | 2016-05-12 |
Debond interconnect structures
Grant 9,269,686 - Ma , et al. February 23, 2 | 2016-02-23 |
Die Assembly On Thin Dielectric Sheet
App 20160043056 - Chiu; Chia-Pin ; et al. | 2016-02-11 |
Die assembly on thin dielectric sheet
Grant 9,177,831 - Chiu , et al. November 3, 2 | 2015-11-03 |
Die Assembly On Thin Dielectric Sheet
App 20150091182 - Chiu; Chia-Pin ; et al. | 2015-04-02 |
Methods Of Forming Under Device Interconnect Structures
App 20140264739 - Morrow; Patrick ; et al. | 2014-09-18 |
Debond Interconnect Structures
App 20140106560 - Ma; Qing ; et al. | 2014-04-17 |
Debond interconnect structures
Grant 8,637,778 - Ma , et al. January 28, 2 | 2014-01-28 |
Three-dimensional stacked substrate arrangements
Grant 8,421,225 - Ramanathan , et al. April 16, 2 | 2013-04-16 |
Three-dimensional Stacked Substrate Arrangements
App 20120280387 - Ramanathan; Shriram ; et al. | 2012-11-08 |
Three-dimensional stacked substrate arrangements
Grant 8,203,208 - Ramanathan , et al. June 19, 2 | 2012-06-19 |
Three-dimensional Stacked Substrate Arrangements
App 20110260319 - Ramanathan; Shriram ; et al. | 2011-10-27 |
Debond Interconnect Structures
App 20110247872 - Ma; Qing ; et al. | 2011-10-13 |
Three-dimensional stacked substrate arrangements
Grant 7,973,407 - Ramanathan , et al. July 5, 2 | 2011-07-05 |
Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
App 20110147059 - Ma; Qing ; et al. | 2011-06-23 |
Portable NMR device and method for making and using the same
Grant 7,800,371 - Park , et al. September 21, 2 | 2010-09-21 |
Laminating magnetic materials in a semiconductor device
Grant 7,755,124 - Fajardo , et al. July 13, 2 | 2010-07-13 |
Field Effect Transistor Structure With Abrupt Source/drain Junctions
App 20100133595 - Murthy; Anand S. ; et al. | 2010-06-03 |
Conveyor System
App 20100108474 - Knigge; Darrell ; et al. | 2010-05-06 |
Field effect transistor structure with abrupt source/drain junctions
Grant 7,682,916 - Murthy , et al. March 23, 2 | 2010-03-23 |
Three-dimensional stacked substrate arrangements
App 20090174070 - Ramanathan; Shriram ; et al. | 2009-07-09 |
Field effect transistor structure with abrupt source/drain junctions
App 20090011565 - Murthy; Anand S. ; et al. | 2009-01-08 |
Method of fabricating a field effect transistor structure with abrupt source/drain junctions
Grant 7,436,035 - Murthy , et al. October 14, 2 | 2008-10-14 |
Method of forming self-passivating interconnects and resulting devices
Grant 7,402,509 - Kobrinsky , et al. July 22, 2 | 2008-07-22 |
MOS transistor structure and method of fabrication
Grant 7,391,087 - Murthy , et al. June 24, 2 | 2008-06-24 |
Laminating magnetic materials in a semiconductor device
App 20080075974 - Fajardo; Arnel M. ; et al. | 2008-03-27 |
Portable NMR device and method for making and using the same
Grant 7,345,479 - Park , et al. March 18, 2 | 2008-03-18 |
Method of fabricating a field effect transistor structure with abrupt source/drain junctions
Grant 7,338,873 - Murthy , et al. March 4, 2 | 2008-03-04 |
Portable Nmr Device And Method For Making And Using The Same
App 20070296413 - Park; Chang-Min ; et al. | 2007-12-27 |
Integrated on-chip NMR and ESR device and method for making and using the same
Grant 7,274,191 - Park , et al. September 25, 2 | 2007-09-25 |
Sealed Three Dimensional Metal Bonded Integrated Circuits
App 20070212815 - Morrow; Patrick ; et al. | 2007-09-13 |
Integrated On-chip Nmr And Esr Device And Method For Making And Using The Same
App 20070152669 - Park; Chang-Min ; et al. | 2007-07-05 |
Portable NMR device and method for making and using the same
App 20070152670 - Park; Chang-Min ; et al. | 2007-07-05 |
Sealed three dimensional metal bonded integrated circuits
Grant 7,217,595 - Morrow , et al. May 15, 2 | 2007-05-15 |
Deposition of diffusion barrier
Grant 7,214,605 - Ramanathan , et al. May 8, 2 | 2007-05-08 |
Method of making semiconductor device using a novel interconnect cladding layer
Grant 7,214,594 - Wong , et al. May 8, 2 | 2007-05-08 |
Stacked device underfill and a method of fabrication
Grant 7,180,180 - Kloster , et al. February 20, 2 | 2007-02-20 |
Bonded wafer processing method
Grant 7,129,172 - Morrow , et al. October 31, 2 | 2006-10-31 |
Method of forming self-passivating interconnects and resulting devices
App 20060220197 - Kobrinsky; Mauro J. ; et al. | 2006-10-05 |
Method of fabricating a field effect transistor structure with abrupt source/drain junctions
App 20060220153 - Murthy; Anand S. ; et al. | 2006-10-05 |
Methods of forming backside connections on a wafer stack
Grant 7,056,813 - Morrow , et al. June 6, 2 | 2006-06-06 |
Dual-damascene interconnects without an etch stop layer by alternating ILDs
Grant 6,992,391 - Ott , et al. January 31, 2 | 2006-01-31 |
Bonded wafer processing method
App 20050215056 - Morrow, Patrick ; et al. | 2005-09-29 |
Dual-damascene interconnects without an etch stop layer by alternating ILDs
App 20050208753 - Ott, Andrew ; et al. | 2005-09-22 |
Stacked device underfill and a method of fabrication
Grant 6,946,384 - Kloster , et al. September 20, 2 | 2005-09-20 |
Sealed three dimensional metal bonded integrated circuits
App 20050189632 - Morrow, Patrick ; et al. | 2005-09-01 |
Methods of forming backside connections on a wafer stack
App 20050164490 - Morrow, Patrick ; et al. | 2005-07-28 |
Methods of forming backside connections on a wafer stack
Grant 6,897,125 - Morrow , et al. May 24, 2 | 2005-05-24 |
Method of fabricating a field effect transistor structure with abrupt source/drain junctions
Grant 6,887,762 - Murthy , et al. May 3, 2 | 2005-05-03 |
Deposition of diffusion barrier
App 20050079685 - Ramanathan, Shriram ; et al. | 2005-04-14 |
Method for making a dual damascene interconnect using a dual hard mask
Grant 6,872,666 - Morrow March 29, 2 | 2005-03-29 |
Methods Of Forming Backside Connections On A Wafer Stack
App 20050059217 - Morrow, Patrick ; et al. | 2005-03-17 |
Method of fabricating a field effect transistor structure with abrupt source/drain junctions
App 20050012146 - Murthy, Anand S. ; et al. | 2005-01-20 |
Three-dimensional stacked substrate arrangements
App 20050003650 - Ramanathan, Shriram ; et al. | 2005-01-06 |
Stacked device underfill and a method of fabrication
App 20040245634 - Kloster, Grant M. ; et al. | 2004-12-09 |
Stacked device underfill and a method of fabrication
App 20040245616 - Kloster, Grant M. ; et al. | 2004-12-09 |
MOS transistor structure and method of fabrication
Grant 6,797,556 - Murthy , et al. September 28, 2 | 2004-09-28 |
Method of making semiconductor devices using carbon nitride, a low-dielectric-constant hard mask and/or etch stop
App 20040119163 - Wong, Lawrence ; et al. | 2004-06-24 |
Method for making a dual damascene interconnect using a dual hard mask
App 20040087166 - Morrow, Patrick | 2004-05-06 |
Semiconductor device having a dual damascene interconnect spaced from a support structure
Grant 6,661,094 - Morrow , et al. December 9, 2 | 2003-12-09 |
Method of making semiconductor device using a novel interconnect cladding layer
App 20030186535 - Wong, Lawrence D. ; et al. | 2003-10-02 |
Method of making a semiconductor device using a damascene interconnect with a laminated dielectric
App 20030173651 - Wong, Lawrence D. ; et al. | 2003-09-18 |
Field effect transistor structure with partially isolated source/drain junctions and methods of making same
App 20030136985 - Murthy, Anand S. ; et al. | 2003-07-24 |
Novel MOS transistor structure and method of fabrication
App 20030098479 - Murthy, Anand ; et al. | 2003-05-29 |
Dual-damascene interconnects without an etch stop layer by alternating ILDs
App 20030064580 - Ott, Andrew ; et al. | 2003-04-03 |
Methods of making field effect transistor structure with partially isolated source/drain junctions
Grant 6,541,343 - Murthy , et al. April 1, 2 | 2003-04-01 |
Novel Mos Transistor Structure And Method Of Fabrication
App 20020190284 - MURTHY, ANAND ; et al. | 2002-12-19 |
Semiconductor device having a dual damascene interconnect spaced from a support structure
App 20020175417 - Morrow, Patrick | 2002-11-28 |
Method for making a dual damascene interconnect using a multilayer hard mask
Grant 6,479,391 - Morrow , et al. November 12, 2 | 2002-11-12 |
Method Of Making A Semiconductor Device Having A Dual Damascene Interconnect Spaced From A Support Structure
App 20020140104 - Morrow, Patrick ; et al. | 2002-10-03 |
Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer
App 20020140103 - Kloster, Grant ; et al. | 2002-10-03 |
Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure
Grant 6,448,177 - Morrow , et al. September 10, 2 | 2002-09-10 |
Method for making a dual damascene interconnect using a multilayer hard mask
App 20020081854 - Morrow, Patrick ; et al. | 2002-06-27 |
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