U.S. patent application number 10/287832 was filed with the patent office on 2003-03-27 for methods of fabrication of electronic interface structures.
Invention is credited to Fillion, Raymond Albert, Kolc, Ronald Frank, Wojnarowski, Robert John.
Application Number | 20030057515 10/287832 |
Document ID | / |
Family ID | 23760695 |
Filed Date | 2003-03-27 |
United States Patent
Application |
20030057515 |
Kind Code |
A1 |
Fillion, Raymond Albert ; et
al. |
March 27, 2003 |
Methods of fabrication of electronic interface structures
Abstract
One type of electronic interface structure includes a base; at
least one elastomeric island supported by the base; and patterned
metallization overlying the at least one elastomeric island and
including at least one floating pad at least partially overlying
the at least one elastomeric island. Another type of electronic
interface structure includes a base; a first dielectric layer
overlying the base and having at least one first dielectric layer
opening therein; a second dielectric layer overlying the first
dielectric layer; and patterned metallization overlying the second
dielectric layer and including at least one floating pad at least
partially overlying the at least one opening.
Inventors: |
Fillion, Raymond Albert;
(Niskayuna, NY) ; Wojnarowski, Robert John;
(Ballston Lake, NY) ; Kolc, Ronald Frank; (Cherry
Hill, NJ) |
Correspondence
Address: |
GENERAL ELECTRIC COMPANY
GLOBAL RESEARCH CENTER
PATENT DOCKET RM. 4A59
PO BOX 8, BLDG. K-1 ROSS
NISKAYUNA
NY
12309
US
|
Family ID: |
23760695 |
Appl. No.: |
10/287832 |
Filed: |
November 5, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10287832 |
Nov 5, 2002 |
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09443410 |
Nov 19, 1999 |
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6507113 |
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Current U.S.
Class: |
257/508 ;
257/E23.02; 257/E23.068; 257/E23.07; 438/508 |
Current CPC
Class: |
H01L 2924/01322
20130101; H05K 2201/0367 20130101; H05K 1/0271 20130101; H01L
2224/05548 20130101; H05K 2201/09663 20130101; H01L 2224/05551
20130101; H05K 3/4007 20130101; H01L 2224/02125 20130101; H01L
2924/01079 20130101; H01L 2224/0401 20130101; H01L 2224/05552
20130101; H01L 2924/12042 20130101; H01L 23/49811 20130101; H01L
23/49838 20130101; H01L 2224/13024 20130101; H01L 24/02 20130101;
H01L 24/05 20130101; H05K 3/326 20130101; H05K 2201/0187 20130101;
H01L 2924/01078 20130101; H05K 2201/0133 20130101; H05K 1/114
20130101; H05K 3/4644 20130101; H01L 2224/02125 20130101; H01L
2924/00012 20130101; H01L 2924/01322 20130101; H01L 2924/00
20130101; H01L 2924/12042 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/508 ;
438/508 |
International
Class: |
C30B 001/00 |
Claims
1. An electronic interface structure comprising: a base; at least
one elastomeric island supported by the base; and patterned
metallization overlying the at least one elastomeric island and
including at least one floating pad at least partially overlying
the at least one elastomeric island.
2. The structure of claim 1 wherein the base comprises a dielectric
layer, a flexible interconnect layer, a printed circuit board, a
circuit chip, a chip package, a multichip package, or a
semiconductor wafer.
3. The structure of claim 1 wherein the base includes at least one
electrical contact pad and further including a dielectric layer
overlying the base and the at least one electrical contact pad and
having at least one opening therein and at least one via therein
with the at least one via extending to the at least one electrical
contact pad, the at least one elastomeric island being situated in
the at least one opening, and wherein the patterned metallization
extends into the at least one via.
4. The structure of claim 3 wherein the at least one floating pad
includes a central pad overlying the at least one elastomeric
island, an outer ring overlying the dielectric layer, and at least
one extension coupling the central pad and the outer ring.
5. The structure of claim 4 wherein the base comprises a flexible
interconnect layer, a printed circuit board, a circuit chip, a chip
package, a multichip package, or a semiconductor wafer.
6. The structure of claim 1 wherein the base includes at least one
electrical contact pad; and further including a dielectric layer
overlying the base and the at least one electrical contact pad and
having at least one via therein with the at least one via extending
to the at least one electrical contact pad, the at least one
elastomeric island overlying the dielectric layer, and wherein the
patterned metallization extends into the at least one via.
7. The structure of claim 6 wherein the at least one floating pad
includes a central pad overlying the at least one elastomeric
island, an outer ring overlying the dielectric layer, and at least
one extension coupling the central pad and the outer ring.
8. The structure of claim 6 wherein the dielectric layer comprises
a polymer layer, or passivation layer, or an interconnect
layer.
9. The structure of claim 6 wherein the base comprises a circuit
chip and the dielectric layer comprises a flexible interconnect
layer.
10. The structure of claim 1 wherein the base has a through hole
extending therethrough; the at least one elastomeric island
overlies the base; and the patterned metallization overlies the at
least one elastomeric island and both surfaces of the base and
extends through the at least one through hole.
11. The structure of claim 10 wherein the at least one floating pad
includes a central pad overlying the at least one elastomeric
island, an outer ring overlying the dielectric layer, and at least
one extension coupling the central pad and the outer ring.
12. The structure of claim 11 wherein the at least one elastomeric
island comprises a plurality of elastomeric islands situated on
both surfaces of the base.
13. The structure of claim 12 wherein a first elastomeric island is
situated on an opposing side of the base and across from a second
elastomeric island.
14. An electronic interface structure comprising: a base; a first
dielectric layer overlying the base and having at least one first
dielectric layer opening therein; a second dielectric layer
overlying the first dielectric layer and the at least one first
dielectric layer opening; and patterned metallization overlying the
second dielectric layer and including at least one floating pad at
least partially overlying the at least one opening.
15. The structure of claim 14 wherein the floating pad includes
central pad overlying the at least one opening, an outer ring
overlying the first and second dielectric layers, and at least one
extension coupling the central pad and the outer ring.
16. The structure of claim 15 wherein: the base includes at least
one electrical contact pad; the first and second dielectric layers
have at least one via extending therethrough to the at least one
electrical contact pad; the patterned metallization extends into
the at least one via.
17. The structure of claim 16 further including a solder mask
overlying the second dielectric layer and the patterned
metallization and having a solder mask opening over at least a
portion of the central pad.
18. The structure of claim 17 wherein the base comprises a wafer
and the at least one first dielectric layer opening comprises at
least two dielectric openings with at least one of the at least two
dielectric openings being situated over a wafer scribe lane.
19. The structure of claim 14 wherein: the base includes at least
one electrical contact pad; the first and second dielectric layers
have at least one via extending therethrough to the at least one
electrical contact pad; the patterned metallization extends into
the at least one via.
20. The structure of claim 14 further including elastomeric
material situated in the at least one opening.
21. The structure of claim 14 wherein the base comprises a wafer
and the at least one first dielectric layer opening comprises at
least two dielectric openings with at least one of the at least two
dielectric openings being situated over a wafer scribe lane.
22. A method for fabricating an electronic interface structure
comprising applying patterned metallization over at least one
elastomeric island supported by a base including at least one
floating pad at least partially overlying the elastomeric
island.
23. The method of claim 22 wherein the base includes at least one
electrical contact pad and further including, prior to applying the
patterned metallization, applying a dielectric layer over the base
and the at least one electrical contact pad; providing at least one
opening in the dielectric layer; forming the elastomeric island in
the at least one opening; providing at least one via in the
dielectric layer extending to the at least one electrical contact
pad, and wherein patterning the metallization includes patterning
metallization extending into the at least one via.
24. The method of claim 23 wherein providing the at least one via
occurs subsequent to forming the elastomeric island.
25. The method of claim 24 wherein forming the elastomeric island
comprises coating the dielectric layer with a polymer and
photo-curing the polymer in the at least one opening of the
dielectric layer.
26. The method of claim 24 wherein forming the elastomeric island
comprises dispensing a polymer into the at least one opening of the
dielectric layer and thermally curing the polymer.
27. The method of claim 23 wherein applying the patterned
metallization includes patterning the at least one floating pad to
include a central pad overlying the at least one elastomeric
island, an outer ring overlying the dielectric layer, and at least
one extension coupling the central pad and the outer ring.
28. The method of claim 22 wherein the base includes at least one
electrical contact pad and further including, prior to applying the
patterned metallization: applying a dielectric layer overlying the
base and the at least one electrical contact pad; providing at
least one via in the dielectric layer with the at least one via
extending to the at least one electrical contact pad; applying the
at least one elastomeric island over the dielectric layer, and
wherein applying the patterned metallization includes applying
patterned metallization into the at least one via.
29. The method of claim 28 wherein applying the patterned
metallization includes patterning the at least one floating pad to
include a central pad overlying the at least one elastomeric
island, an outer ring overlying the dielectric layer, and at least
one extension coupling the central pad and the outer ring.
30. The method of claim 22 further including, prior to applying the
patterned metallization, applying the at least one elastomeric
island on a surface of the base, and providing a through hole
extending through the base, wherein applying the patterned
metallization includes patterning metallization extending through
the at least one through hole and on both surfaces of the base.
31. The method of claim 30 wherein applying the patterned
metallization includes patterning the at least one floating pad to
include a central pad overlying the at least one elastomeric
island, an outer ring overlying the dielectric layer, and at least
one extension coupling the central pad and the outer ring.
32. The method of claim 31 wherein applying the at least one
elastomeric island on a surface of the base, comprises applying a
plurality of elastomeric islands on both surfaces of the base.
33. The method of claim 32 wherein a first elastomeric island is
applied on an opposing side of the base and across from a second
elastomeric island.
34. A method for fabricating an electronic interface structure
comprising: providing a second dielectric layer overlying a first
dielectric layer overlying a base, with the first dielectric layer
having at least one first dielectric layer opening therein; and
applying patterned metallization over the second dielectric layer
including at least one floating pad at least partially overlying
the at least one first dielectric layer opening.
35. The method of claim 34 wherein applying the patterned
metallization includes patterning the floating pad to include a
central pad overlying the at least one opening, an outer ring
overlying the first and second dielectric layers, and at least one
extension coupling the central pad and the outer ring.
36. The method of claim 35 wherein the base includes at least one
electrical contact pad, and further including providing at least
one via extending through the first and second dielectric layers to
the at least one electrical contact pad, wherein patterned the
metallization includes patterning metallization extending into the
at least one via.
37. The method of claim 36 further including situating an
elastomeric material in the opening of the first dielectric layer
prior to applying the second dielectric layer.
38. The method of claim 36 further including applying a solder mask
over the second dielectric layer and the patterned metallization
and providing a solder mask opening over at least a portion of the
central pad.
39. The method of claim 34 wherein providing includes forming at
least two first dielectric layer openings in the first dielectric
layer with at least one first of the at least two dielectric layer
openings comprising an opening over which the metallization will be
patterned and at least one second of the at least two dielectric
layer openings situated over a wafer scribe lane of the base.
40. The method of claim 39 further including removing portions of
the second dielectric layer overlying the at least one second of
the at least two dielectric layer openings.
Description
BACKGROUND
[0001] The invention relates generally to electrical
interconnections and more particularly to electronic interface
structure fabrication methods.
[0002] Ball grid array (BGA) technology provides a high density of
interconnections per unit area, but mismatches of coefficients of
thermal expansion (CTEs) occur when ceramic or polymer BGA
substrates and printed circuit boards are joined and often result
in cracked solder joints, especially as the size of the substrates
and temperature ranges are increased. In column grid array (CGA)
techniques and other BGA techniques, a eutectic solder is applied
to printed circuit board and multi-chip module array pads and the
resulting joint is soldered to a higher temperature solder column
or ball which does not melt. Both BGA and CGA structures can be
inflexible and vulnerable to damage. For various types of BGA and
CGA, increases in reliability are attempted by elaborate
under-filling of the structures with polymer glues to reinforce the
interfaces and reduce the effects of the CTE mismatch on the solder
joints. The polymer glues, however, impair repairability because of
the difficulty in removing the glues after hardening. Furthermore,
these types of structures require two separate solder steps, are
more expensive than conventional solder structures, and require
more vertical space due to increased height of the joints.
[0003] One conventional micro ball grid array interface technique
for attaching a semiconductor circuit chip directly to a substrate
is to use a series of solder bumps clustered at the center of the
chip to constrain the area over which stresses between differing
coefficients of thermal expansion occur. In this embodiment, chips
have their pads reconfigured and solder micro bumps are applied
over the reconfigured pads. In one embodiment, ball grid array
processes are used with the temperature range being constrained
during device operation to 30.degree. C. to 70.degree. C. in an
effort to avoid CTE stress effects. In another ball grid array
interface technique, the area where the chip faces the printed
circuit board or substrate is not used for direct interconnection.
Instead, metallization is routed from the chip to adjacent support
structures which then have solder ball connections. This technique
can create size and pin count limitations as well as electrical
parasitic effects.
[0004] Commonly assigned Wojnarowski et al., U.S. Pat. No.
5,900,674, describes an interface including a surface having an
electrically conductive pad; a compliant coating over the surface
having a via extending to the pad; metallization patterned over the
compliant coating and extending into the via; a low modulus
dielectric interface layer overlying the compliant coating and
having an interface via extending to the metallization; and a
floating pad structure including floating pad metallization
patterned over the dielectric interface layer with a first portion
forming a central pad and a second portion forming an extension
from the central pad extending into the interface via. The
"floating pad" structure is used to increase reliability by
providing stress and thermal accommodation of the two materials and
permitting movement of the floating pad independent of the base
pad. The extension provides stress relief for different
coefficients of thermal expansion. The floating pad interface
structures can include a single pad and extension or several
extensions in situations wherein a single extension is not
sufficient for extreme thermal stress/strain situations. The
resulting structure accommodates thermal and material stresses
without submitting the via interconnect areas to forces that can
crack vias or break connections at the pads. The floating pads
permit movement independent of a base surface underlying the pads
while providing electrical interconnections through selected
materials that are specifically patterned to provide low forces at
the via areas and thus accommodate differential thermal stresses
which may be caused by large CTE differences.
[0005] Commonly assigned Wojnarowski et al., U.S. Pat. No.
5,938,452 describes a more flexible interface structure for
electronic devices that does not require an underlying base surface
and that can be used for relieving stress from structures such as
multi-chip modules (MCMs), wafers, individual dies or chips,
microelectromechanical structures (MEMs), printed circuit boards,
and surface mount technologies which may be caused from coefficient
of thermal expansion mismatches with connections such as those
formed by ball grid arrays, micro ball grid arrays, column grid
arrays, flip chips, solder Joints, or tape automated bonding
connections. In one embodiment, a film interface includes a film;
flexible material attached to a portion of the film; and surface
metallization on the flexible material. The film has at least one
via extending therethrough to the surface metallization. A floating
pad structure including floating pad metallization patterned over
the flexible material and the surface metallization has a first
portion forming a central pad and a second portion forming at least
one extension from the central pad and extending into the at least
one via.
[0006] The floating pad embodiments of aforementioned U.S. Pat.
Nos. 5,900,674 and 5,938,452 can extend solder attach life by a
factor of about ten. However, the fabrication sequences involve
complex deposition and via formation processes and are therefore
expensive.
SUMMARY
[0007] It would therefore be desirable to have an electronic
interface structure with a simplified fabrication sequence as
compared with fabrication sequences of present electronic interface
structures.
[0008] In accordance with one embodiment of the present invention,
an electronic interface structure includes a base; at least one
elastomeric island supported by the base; and patterned
metallization overlying the at least one elastomeric island and
including at least one floating pad at least partially overlying
the at least one elastomeric island.
[0009] In accordance with another embodiment of the present
invention, an electronic interface structure includes a base; a
first dielectric layer overlying the base and having at least one
first dielectric layer opening therein; a second dielectric layer
overlying the first dielectric layer; and patterned metallization
overlying the second dielectric layer and including at least one
floating pad at least partially overlying the at least one
opening.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The features of the invention believed to be novel are set
forth with particularity in the appended claims. The invention
itself, however, both as to organization and method of operation,
together with further objects and advantages thereof, may best be
understood by reference to the following description taken in
conjunction with the accompanying drawings, where like numerals
represent like components, in which:
[0011] FIGS. 1-2 are sectional side views of fabrication stages of
one embodiment of the present invention wherein a elastomeric
island is formed within a dielectric layer.
[0012] FIGS. 3-5 are top views of floating pad embodiments that can
be used with any of the embodiments of FIGS. 1-2 and 6-19.
[0013] FIGS. 6-11 are sectional side views of fabrication stages in
other embodiments of the present invention wherein an elastomeric
island is formed on a dielectric layer.
[0014] FIGS. 12-15 are sectional side views of fabrication stages
in other embodiments of the present invention where metallization
is patterned on multiple surfaces.
[0015] FIGS. 16-19 are sectional side views of fabrication stages
in other embodiments of the present invention wherein a floating
pad is formed on a dielectric layer overlying an opening.
DETAILED DESCRIPTION OF THE INVENTION
[0016] FIGS. 1-15 relate to embodiments of the present invention
wherein an electronic interface structure fabrication method
comprises applying patterned metallization 22 over at least one
elastomeric island 18 supported by a base 10 including at least one
floating pad 24 at least partially overlying the elastomeric
island. The word "supported" is intended to cover situations
wherein the island is within the base, directly on top of the base,
and/or on top of any material overlying the base. Although the
figures generally show single floating pads for purposes of
illustration, in practice large arrays of floating pads can be
simultaneously formed on a common base.
[0017] FIGS. 1-2 are sectional side views of fabrication stages of
one embodiment of the present invention wherein elastomeric island
18 is formed within a dielectric layer 14, and FIGS. 3-5 are top
views of floating pad 24 embodiments that can be used with any of
the embodiments of FIGS. 1-2 and 6-19.
[0018] In the embodiment of FIG. 1, base 10 includes at least one
electrical contact pad 12. A dielectric layer 14 is applied over
the base and the at least one electrical contact pad, at least one
opening 16 is provided in the dielectric layer, the elastomeric
island 18 is formed in the at least one opening, and at least one
via 20 is provided in the dielectric layer to extend to the at
least one electrical contact pad. Metallization 22 is then applied
over the surface of the dielectric layer 14 and patterned such that
the metallization 22 extends into the at least one via and over the
at least one elastomeric island 18.
[0019] Base 10 may comprise a semiconductor wafer that has not yet
been cut into segmented individual chips or a chip which has been
segmented from a wafer. Processing on a wafer that has not yet been
segmented enables mass fabrication of interface structures and
prevents single chip handling problems such as corner edge
separations of the compliant coating and alignment difficulties
associated with single die handling for photolithographic
processing. Base 10 may alternatively comprise, for example, a
passive component, a chip package, a multichip package, a printed
circuit (PC) board, a multi-chip module (MCM), a flexible
interconnect layer structure such as described in Cole et al., U.S.
Pat. No. 5,527,741, or a substrate or wafer including photonic
structures, liquid crystal structures, or microelectromechanical
structures (MEMS), for example. Contact pads 12 may comprise pads
or metallization on any of the above-discussed bases.
[0020] Dielectric layer 14 typically comprises a polymer material
such as a polyimide and has a thickness ranging from about 10
micrometers to about 100 micrometers, for example. Dielectric layer
14 can be deposited on base 10 by spin, spray, or extrusion
coating, for example, or can be laminated onto base 10 with heat
and/or an adhesive (not shown).
[0021] Openings 16 are formed in dielectric layer 14 by any
appropriate method in the areas where floating pads 24 will be
situated. In one embodiment, the dielectric layer can be scanned
repeatedly with a high energy, continuous wave laser to create
openings of desired size and shape. Other appropriate methods
include, for example, photopatterning photopatternable polyimides
and using an excimer laser with a mask (not shown). Openings 16 may
extend completely through dielectric layer 14, as shown, or partly
through dielectric layer 14.
[0022] In one embodiment, after dielectric layer 14 is cured,
elastomeric island 18 is formed by coating the dielectric layer
with a polymer such as siloxane polyimide epoxy, for example, and
photo-curing the polymer to form the at least one opening of the
dielectric layer. Elastomeric island 18 can be deposited by any one
of a number of methods. One method is using a squeegee to spread
liquid polymer over the surface and deposit it into each opening. A
second deposition method involves the use of a squeegee with a
stencil that has openings within the stencil that are aligned to
the openings 16 in dielectric layer 14, which would be able to
dispense additional material into each opening 16 and to avoid
having residue polymer material onto the surface of dielectric
layer 14. A third deposition method is to use a pump-actuated
dispense nozzle to inject a selected volume of liquid polymer into
each opening 16. A fourth deposition method includes using an ink
jetting system to shoot droplets of liquid polymer into each
opening 16.
[0023] The deposited liquid elastomeric island material can be
cured by using one of a number of standard polymer curing methods
such as thermal curing, photo-curing or microwave curing or by a
combination of these methods. Residue liquid material that is
inadvertently dispensed onto areas of dielectric layer 14 can be
either removed by a solvent wash or left in place to become an
integral part of the dielectric layer 14.
[0024] Referring to FIG. 2, vias 20 are formed in dielectric layer
14 to extend to respective electrical contact pads 12. In one
embodiment, the vias are formed by laser ablation.
[0025] Then patterned metallization 22 is applied. Patterned
metallization can be applied either by depositing a blanket layer
of metallization over the interface structure (by sputtering and/or
plating, for example) and then patterning the metallization with a
standard photoresist and etch process or by a single step of
depositing the metallization directly in the desired pattern such
as by using an adaptive lithography system. Metallization 22 in one
embodiment comprises a thin adhesion layer of 1000 .ANG. sputtered
titanium, coated by a thin layer of 3000 .ANG. sputtered copper,
coated by a layer of electroplated copper to a thickness of four
microns, for example. An optional buffer layer of 1000 .ANG. of
titanium can be applied over the electroplated copper. Other
example metallization materials include molybdenum, tungsten, and
gold. The appropriate material of the metallization will vary
depending on the materials of base 10 and contact pads 12 and on
the environment, such as a high temperature environment or an
oxidizing environment for example, in which the interface structure
will be used. The thickness of the plated copper within the
patterned metallization 22 varies based upon the current
requirement of the electrical circuit, with a thickness in the
range of about 1 to about 4 micrometers for lower current levels
such as about 0.1 amps or less, to a thickness in the range of
about 10 to about 50 microns for higher currents such as about 1
amp or more.
[0026] The size of central pads 26 will vary according to the
specific planned use of the floating pad structure. For example, if
a solder ball or solder bump will be attached directly to the
central pad, the central pad must be large enough to accommodate
the attachment. The size of the central pad will also affect the
length of extensions. Smaller diameter central pads require less
space than larger diameter pads and therefore leave more space for
longer extensions.
[0027] The thickness of metallization for the floating pad
structures can be uniform, as shown, or variable, as described in
aforementioned U.S. Pat. Nos. 5,900,674 and 5,938,452, for example,
wherein a modified central pad includes an additional metallization
area. In one embodiment, the extensions have a thickness ranging
from about 2 microns to about 8 microns, and the central pad has a
thickness ranging from about 4 microns to about 20 microns. This
embodiment is useful because thin extensions are more flexible than
thicker extensions whereas the central pad is preferably
sufficiently thick to be solderable to another electrically
conductive surface.
[0028] In one embodiment, applying patterned metallization 22
includes patterning at least one floating pad 24 to include a
central pad 26 overlying the at least one elastomeric island 18, an
outer ring 28 overlying dielectric layer 14, and at least one
extension 30 coupling the central pad and the outer ring. In this
embodiment, the central pad is mechanically isolated from the
underlying base 10. Extensions 30 may be planar or may include dip
portions (not shown) as described in aforementioned U.S. Pat. Nos.
5,900,674 and 5,938,452 for reducing mechanical stress on the
extensions.
[0029] The top views of FIGS. 3-5 are for purposes of example only.
In FIG. 3, floating pad 124 includes an additional ring 127 between
central pad 126 and ring 128 with additional extensions 131 for
further stress relief. In FIG. 4, floating pad 224 includes four
curved extensions 230 between central pad 226 and ring 228. In FIG.
5, floating pad 324 includes serpentine shaped extensions 330
between central pad 326 and ring 328.
[0030] The above described example embodiment of FIGS. 1-5 includes
only two deposition sequences, one metallization sequence, and one
via formed per contact pad connection and is thus simpler than the
aforementioned U.S. Pat. Nos. 5,900,674 and 5,938,452. If desired,
in the embodiments described above, as well as in the embodiments
described below, passivation material (not shown) such as a
polymeric dielectric material or a solder mask material can be
applied to the surface of patterned metallization 22 to protect the
patterned metallization.
[0031] FIGS. 6-11 are sectional side views of fabrication stages in
other embodiments of the present invention wherein an elastomeric
island 118 is formed on a dielectric layer 14. In these
embodiments, base 10 again optionally includes at least one
electrical contact pad 12.
[0032] The dielectric layer 14 is applied over the base and the at
least one electrical contact pad, at least one via 20 is provided
in the dielectric layer and extends to the at least one electrical
contact pad, and the at least one elastomeric island 18 is applied
over the dielectric layer. Metallization 22 is then applied over
the surface of the dielectric layer 14 and onto the at least one
elastomeric island 118 and patterned such that the metallization 22
extends into the at least one via and over the at least one
elastomeric island 18.
[0033] Unlike the embodiment of FIGS. 1-2, in the embodiments of
FIGS. 6-11, dielectric layer 14 is not patterned to include
openings 16. Instead, a layer of elastomeric material 32 (FIG. 6)
is applied over the dielectric layer and patterned to provide at
least one elastomeric island 118 over dielectric layer 14 and base
10. In the embodiment of FIGS. 6-8, vias 20 can be formed prior to
or subsequent to patterning of elastomeric islands 118 (FIG. 7) and
metallization 122 (FIG. 8) can then be applied as discussed
above.
[0034] The embodiment of FIGS. 9-10 is similar to that of FIGS. 7-8
except that dielectric layer 114 comprises a passivation layer
including an inorganic dielectric material such as silicon nitride,
silicon dioxide, or amorphous hydrogenated carbon. Depending on the
material of base 10, dielectric layer 114 can be grown on the
surface of base 10 without growing on the electrical contact pads
12. In this situation, "vias" will be provided for the contact pads
without a separate laser ablation step. Alternatively, dielectric
layer 114 can be grown over the entire surface and later patterned
using standard photomask and etch processes to form the openings
over the contact pads 12. Inorganic dielectric layers have better
dielectric breakdown characteristics and are less prone to pin hole
openings than organic dielectric layers and can therefore be
applied with reduced thicknesses (such as in the range of about 200
.ANG. to about 5000 .ANG., for example).
[0035] In the embodiment of FIG. 11, base 10 comprises a circuit
chip and dielectric layer 214 comprises a flexible interconnect
layer. The circuit chip and flexible interconnect layer are coupled
by adhesive 215, via 20 extends through the flexible interconnect
layer, and patterned metallization 322 forms the floating pad and
electrical contact connections. The elastomeric island 118 is
formed in the same manor as shown in FIG. 7 on the flexible
interconnect layer either prior to the bonding of the flexible
interconnect layer onto the base 10 or after the bonding.
[0036] FIGS. 12-15 are sectional side views of fabrication stages
in other embodiments of the present invention where an interface
structure is fabricated that can be added to commercial area array
devices to provide the advantages of the above described
embodiments of this invention. In this embodiment at least one
through hole 50 is provided to extend through base 10 that may
comprise a number of materials such as polyimides or
polytetrafluoroethelynes (PTFEs), or a composite material made out
of a combination of these materials, for example. The flexible
structure could be as thin as 10 micrometers or less, or as thick
as 100 micrometers or more. Metallization 222 is patterned on
multiple surfaces of base 10 and through the at least one through
hole.
[0037] As shown in FIG. 12, a plurality of elastomeric islands can
be formed on both surfaces of the base with each being formed using
the process described with respect to FIGS. 6 and 7, for example.
In one embodiment, a first elastomeric island 118 is applied on an
opposing side of the base and across from a second elastomeric
island 218. Typically the upper elastomeric island 118 will be
aligned to the lower elastomeric island 218. This alignment
facilitates the use of the interface structure on an area array
device that would be mounted down onto a circuit board or substrate
that has a matching area array of contact pads. Although other
alignments of the elastomeric islands 118 and 218 are possible and
may be useful in certain applications, the alignment shown in FIGS.
12-14 is directly applicable to existing area array devices and
board pad layouts.
[0038] FIG. 13 illustrates a through hole 50 that is formed through
base 10, and FIG. 14 illustrates patterned metallization 222 on
both surfaces of the base coupled via through hole 50. Base 10 may
include through holes prior to application of elastomeric islands
118 and 218, or depending on the material of base 10, through holes
can be provided after application of the elastomeric islands. If
base 10 comprises a flexible interconnect layer or other material
that can be ablated or etched, processes such as laser ablation,
plasma etching, or chemical etching can be used to form the through
holes. Through holes 50 can be situated close to (about 50 to about
100 micrometers) or farther away (about 2-5 millimeters or farther)
from the floating pad, for example.
[0039] Elastomeric islands 118 and 218 may be formed sequentially
or simultaneously. In a sequential process, a layer of elastomeric
material 32 (FIG. 6) is applied on one side of base 10 and
patterned to provide at least one elastomeric island 118 on base
10. This would be followed by repeating these process steps on the
other side of base 10. In the alternative process, the two
elastomeric islands 118 and 218 would be formed in parallel. In the
parallel process, first one side of the base 10 is coated with a
layer of elastomeric material 32 (FIG. 6) followed by coating the
second side. This is followed by one side being patterned to
provide at least one elastomeric island 118 then repeating the
patterning step on the other side of the base 10.
[0040] In one embodiment, metallization 222 is applied to both
sides and to the through holes. This can be done by electroplating,
electroless plating or other metallization techniques. The
metallization 222 is photopatterned by applying photoresist (not
shown) over the top and bottom surfaces of the structure and in or
over the through holes 50. The photoresist is pattern developed by
exposing predetermined areas of the photoresist to a UV or visible
light source, either with a direct write laser system or with a
laser or light source that exposes selected areas through a mask
such as a metal mask. The developed photoresist is then used as an
etch mask for a chemical metal etch back process leaving metal in
through holes 50 and on selected areas of the surfaces to form the
floating pads and interconnection lines. Either side of the
resulting electronic interface structure of FIG. 14 can then be
attached to a component (not shown) such as a packaged device or
multichip module via solder or a conductive adhesive, for example.
The opposite side would be used to attach the interface structure
and its attached device to a board or substrate. This structure not
only provides a method of applying the floating pads to existing
area array devices but provides the stress relieving compliance of
two sets of elastomeric islands 118 and 218.
[0041] In the embodiment of FIG. 15, elastomeric islands 118 are
formed on only one side of the base 10. Through holes 50 are formed
through base 10. The top and bottom surfaces of the base 10 and the
through holes 50 are metallized and patterned leaving patterned
metallization 222 on the surfaces of base 10 and through hole 50,
and elastomeric islands 118. The patterned metallization 222 forms
a contact pad on the bottom of the base 10 that is aligned under
the top elastomeric island 118. In one attachment method of this
embodiment the elastomeric island side of the resulting interface
structure can be attached to an area array device and the other
side of the interface structure can be attached to a mating board
or substrate.
[0042] FIGS. 16-19 are sectional side views of fabrication stages
in other embodiments of the present invention wherein a floating
pad is formed on a dielectric layer overlying an opening.
[0043] In this embodiment, dielectric layer 14 can be formed on
base 10 and opening 16 can be provided in a similar manner as
discussed with respect to FIG. 1. A second dielectric layer 34
overlies first dielectric layer 14. Second dielectric layer 34 can
be formed by laminating a thin polymer film over the surface of
first dielectric layer 14 and bridging the opening 16.
Metallization 322 is applied and patterned over the second
dielectric layer to include at least one floating pad 24 at least
partially overlying opening 16.
[0044] If desired, an elastomeric island or other flexible material
can be added in the resulting areas 17 of openings 16. In such
embodiments elastomeric material is deposited into the opening 16
in the same manor as in FIG. 1. Metallization 120 is applied and
patterned as in FIGS. 1-2. Additionally, in such embodiments second
dielectric layer 34 can optionally be applied by techniques such as
spin coating, spray coating or extrusion coating.
[0045] In one embodiment, base 10 includes at least one electrical
contact pad 12, and at least one via 120 is provided to extend
through the first and second dielectric layers to the at least one
electrical contact pad. Patterned metallization 422 includes
metallization extending into the at least one via.
[0046] As shown in FIG. 17, a solder mask 36 can be applied over
the second dielectric layer and the patterned metallization with a
solder mask opening over at least a portion of the central pad.
Solder 38 can be used in the solder mask opening for attachment of
the interface structure.
[0047] FIGS. 18-19 illustrate an option that can be used to
simplify separation of base 10, particularly if base 10 comprises a
semiconductor wafer. In the embodiment of FIG. 18, at the same time
that openings 16 are being formed in dielectric layer 14, openings
116 can be formed over wafer scribe lanes 40. Later, as shown in
FIG. 19, solder mask 36 and second dielectric layer 34 can be
removed to expose wafer scribe lane 40. Removal of the dielectric
layer 34 can be accomplished by the same processes that are used to
form vias 120, such as laser ablation or with a mask based etch
process. This embodiment facilitates sawing of wafer scribe lanes
without interference from overlying dielectric layers. This same
process of opening the regions between die sites can be applied to
any of the structures depicted in FIGS. 1-2 and 6-17.
[0048] While only certain features of the invention have been
illustrated and described herein, many modifications and changes
will occur to those skilled in the art. It is, therefore, to be
understood that the appended claims are intended to cover all such
modifications and changes as fall within the true spirit of the
invention.
* * * * *