U.S. patent application number 10/191107 was filed with the patent office on 2002-11-21 for system to improve ser immunity and punchthrough.
This patent application is currently assigned to LSI Logic Corporation. Invention is credited to Giust, Gary K., Kong, Weiran, Puchner, Helmut.
Application Number | 20020173087 10/191107 |
Document ID | / |
Family ID | 24441171 |
Filed Date | 2002-11-21 |
United States Patent
Application |
20020173087 |
Kind Code |
A1 |
Puchner, Helmut ; et
al. |
November 21, 2002 |
System to improve SER immunity and punchthrough
Abstract
A method for fabricating an SRAM device having a standard well
tub, where an additional well tub is deposited within the standard
well tub. In this manner, the dopant concentration is increased in
the well area of the SRAM device, which increases both the
isolation punchthrough tolerance and the SER immunity of the
device. The additional well tub is deposited to a depth that is
shallower than the standard well tub. The additional well tub is
deposited using an ion implantation process using the same mask set
as that used for the threshold voltage adjustment deposition. Thus,
no additional mask layer is required to deposit the additional well
tub, and the all of the expenses normally associated with an
additional mask layer are avoided.
Inventors: |
Puchner, Helmut; (Santa
Clara, CA) ; Giust, Gary K.; (Cupertino, CA) ;
Kong, Weiran; (Sunnyvale, CA) |
Correspondence
Address: |
LSI LOGIC CORPORATION
Intellectual Property Department
1551 McCarthy Boulevard, MS D-106
Milpitas
CA
95035
US
|
Assignee: |
LSI Logic Corporation
|
Family ID: |
24441171 |
Appl. No.: |
10/191107 |
Filed: |
July 9, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10191107 |
Jul 9, 2002 |
|
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09609527 |
Jul 3, 2000 |
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6455363 |
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Current U.S.
Class: |
438/152 ;
257/E21.551; 257/E21.642; 257/E21.644; 257/E27.063 |
Current CPC
Class: |
H01L 27/0921 20130101;
H01L 21/823878 20130101; H01L 21/76237 20130101; H01L 21/823892
20130101 |
Class at
Publication: |
438/152 |
International
Class: |
H01L 021/00; H01L
021/84 |
Claims
What is claimed is:
1. In a method for fabricating an SRAM device having a standard
well tub, the improvement comprising the step of depositing an
additional well tub within the standard well tub, where the
additional well tub is deposited to a depth that is shallower than
the standard well tub.
2. The method of claim 1 wherein the SRAM device is isolated from
adjacent devices with a shallow trench isolation structure that
extends to a depth, and the additional well tub is deposited to a
depth that is deeper than the depth of the shallow trench isolation
structure.
3. The method of claim 1 wherein the additional well tub is
deposited to a depth of between about 0.1 microns and about 0.5
microns.
4. The method of claim 1 wherein the additional well tub is
deposited to a concentration of between about 10.sup.17 ions per
cubic centimeter and about 10.sup.20 ions per cubic centimeter.
5. The method of claim 1 wherein the standard well tub is doped P
type and the additional well tub is deposited with Boron at an
energy of between about 25 keV and about 190 keV.
6. The method of claim 1 wherein the standard well tub is doped N
type and the additional well tub is deposited with Phosphorous at
an energy of between about 80 keV and about 360 keV.
7. The method of claim 1 wherein the additional well tub is
deposited with a dose of between about 1e11 ions per square
centimeter and about 1e14 ions per square centimeter.
8. The method of claim 1 wherein the additional well tub is
deposited prior to implanting a threshold voltage layer using an
existing threshold voltage adjustment mask set.
9. An SRAM device having a standard well tub, the improvement
comprising an additional well tub within the standard well tub,
where the additional well tub is shallower than the standard well
tub.
10. The device of claim 9 wherein the SRAM device is isolated from
adjacent devices with a shallow trench isolation structure that
extends to a depth, and the additional well tub is deposited to a
depth that is deeper than the depth of the shallow trench isolation
structure.
11. The device of claim 9 wherein the additional well tub is at a
depth of between about 0.1 microns and about 0.5 microns.
12. The device of claim 9 wherein the additional well tub has a
dopant concentration of between about 10.sup.17 ions per cubic
centimeter and about 10.sup.20 ions per cubic centimeter.
13. A method for increasing the SER immunity and isolation
punchthrough tolerance of an SRAM device having a standard well
tub, comprising the step of doping the device with an additional
well tub within the standard well tub, where the additional well
tub is deposited to a depth that is shallower than the standard
well tub.
14. The method of claim 13 wherein the SRAM device is isolated from
adjacent devices with a shallow trench isolation structure that
extends to a depth, and the additional well tub is deposited to a
depth that is deeper than the depth of the shallow trench isolation
structure.
15. The method of claim 13 wherein the additional well tub is
deposited to a depth of between about 0.1 microns and about 0.5
microns.
16. The method of claim 13 wherein the additional well tub is
deposited to a concentration of between about 10.sup.17 ions per
cubic centimeter and about 10.sup.20 ions per cubic centimeter.
17. The method of claim 13 wherein the standard well tub is doped P
type and the additional well tub is deposited with Boron at an
energy of between about 25 keV and about 190 keV.
18. The method of claim 13 wherein the standard well tub is doped N
type and the additional well tub is deposited with Phosphorous at
an energy of between about 80 keV and about 360 keV.
19. The method of claim 13 wherein the additional well tub is
deposited with a dose of between about 10.sup.11 ions per square
centimeter and about 10.sup.14 ions per square centimeter.
20. The method of claim 13 wherein the additional well tub is
deposited prior to implanting a threshold voltage layer using an
existing threshold voltage adjustment mask set.
Description
FIELD
[0001] This invention relates to the field of semiconductor wafer
processing. More particularly the invention relates to a system for
improving the electrical characteristics of static random access
memory devices.
BACKGROUND
[0002] As semiconductor device geometries shrink, design engineers
encounter new problems that tend to reduce the reliability of the
devices. In addition, solutions that were developed to overcome
previously identified problems may become ineffectual or create
other problems as the geometries shrink and other processing
constraints change. Thus, there is a continual need to improve upon
the methods and structures relied upon in the past.
[0003] One issue that is always of high priority is that of
maintaining electrical pathway integrity within the device. In
other words, ensuring that charge carrier flow is limited to those
pathways and those times at which it is desired. For example, it is
typically desired to electrically isolate semiconductor devices
that are formed adjacent to one another in a semiconducting
substrate. This is accomplished in a variety of ways, such as by
using locos oxidation or shallow trench isolation techniques.
However, as the size of the semiconductor device decreases, the
size of these structures must also preferably decrease, which tends
to reduce the inherent effectiveness of the isolation structure.
This may result in a number of different problems, such as an
increase in the soft error rate (SER), where devices become
unstable and lose their specified state. Thus, additional systems
need to be found to augment the isolation provided by these
structures.
[0004] As a further example, the ability to open and close the
current pathway in a semiconductor device such as a MOS transistor
is fundamental to the proper operation of the device. Again,
however, as device geometries are reduced, the standard structures
that were developed for larger devices tend to be less effectual in
preventing inadvertent leakage through the isolation region of
smaller transistors. Thus, current interwell punchthrough in the
isolation tends to become a bigger problem as the devices are made
smaller. Here again, additional systems are needed to augment the
strength of the isolation region.
[0005] While there may be many systems that could be devised to
alleviate these and other problems, they tend to add complexity,
expense and time to the device fabrication process. Typically,
these added steps come in the form of additional mask layers that
must be developed and used. Thus, the financial pressures inherent
in semiconductor device fabrication must also be weighed in finding
solutions to these conditions.
[0006] What is needed, therefore, is a system to improve the soft
error rate immunity and isolation punchthrough tolerance of a
device, without requiring additional mask layers.
SUMMARY
[0007] The above and other needs are met by a method for
fabricating an SRAM device having a standard well tub, where an
additional well tub is deposited within the standard well tub. The
additional well tub is deposited to a depth that is shallower than
the standard well tub. In this manner, the dopant concentration is
increased in the well area of the SRAM device, which increases both
the isolation punchthrough tolerance and the SER immunity of the
device.
[0008] In a preferred embodiment, the additional well tub is
deposited using an ion implantation process to a depth that is
shallower than the standard well tub. Further, the SRAM device is
preferably isolated from adjacent devices with a shallow trench
isolation structure that extends to a depth, and the additional
well tub is deposited to a depth that is deeper than the depth of
the shallow trench isolation structure. In a most preferred
embodiment, the additional well tub is implanted using the same
mask set as that used for the threshold voltage adjustment
deposition of the SRAM device. Thus, in the preferred embodiment,
no additional mask layer is required to deposit the additional well
tub, and all of the expenses normally associated with an additional
mask layer are avoided.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Further advantages of the invention are apparent by
reference to the detailed description when considered in
conjunction with the figures, which are not to scale so as to more
clearly show the details, wherein like reference numbers indicate
like elements throughout the several views, and wherein:
[0010] FIG. 1 is a cross-sectional dopant profile of a standard
well tub,
[0011] FIG. 2 is a cross-sectional dopant profile of a
semiconductor device receiving the additional well tub
deposition,
[0012] FIG. 3 is a cross-sectional dopant profile of a
semiconductor device after receiving the additional well tub
deposition, and
[0013] FIG. 4 is a dopant profile chart.
DETAILED DESCRIPTION
[0014] Turning now to the drawings, there is depicted in FIG. 1 a
cross-sectional view of a substrate 10 having semiconductor device
regions 22, 24, 26, and 28 in a wafer 14. In the depiction of FIG.
1, the devices that will be formed in device regions 22, 24, 26,
and 28 are only in the very beginning phases of construction. At
the phase depicted, isolation structures 16, such as shallow trench
isolation oxide structures, have been formed in the semiconductor
material 14. Wells 18 and 20 have also been formed. In the
embodiment depicted, wells 18 represent N doped wells and wells 20
represent P doped wells. A layer of sacrificial oxide 12 has been
deposited over the surface of the substrate 14.
[0015] In FIG. 2, a layer of photoresist 30 has been deposited on
the sacrificial oxide 12. The photoresist 30 has been cured,
exposed, developed, and baked to provide a deposition mask on the
substrate 10. Through the openings in the photoresist 30, such as
the opening that is overlying the semiconductor device region 24, a
dopant 32 is deposited through the sacrificial oxide layer 12 and
into the semiconductor material 14. The dopant material 32 is
selected to be of the same type, either P or N, as the well of the
device region into which it is deposited. Therefore, in the
embodiment depicted in FIG. 2, the dopant 32 is a P type species,
because the well 20 is P type.
[0016] The dopant 32 is preferably deposited to a depth that is
greater than the isolation structure 16 and shallower than the well
20. In this manner, the additional dopant 32 is concentrated within
a region 34 of the device 24 where it provides a higher junction
capacitance for the device 24, thus enhancing SER immunity, and
also strengthens the channel region that is to be further defined
at later stages of the processing, thus enhancing deep channel
punchthrough resistance as well as increasing interwell
punchthrough resistance. This region 34 is essentially the
deposition of an additional well 34.
[0017] An additional benefit of this system is that the mask layers
and methods used to form the photoresist layer 30 are not in
addition to those required for the standard processing of the
devices 22, 24, 26, and 28. The reason for this is that an SRAM
device, such as device 24, typically requires a threshold depletion
deposition, which uses a mask structure that is identical to that
described above and depicted in FIG. 2. Thus, after the dopant 32
for the additional well 34 has been deposited, the threshold
depletion dopant can be deposited. In this manner, only a single
deposition step is added to the fabrication process, without any
additional mask layer processing required.
[0018] Further, this system is compatible with the fabrication of
SRAM devices 22 and 24 that are formed on the same substrate 10 as
logic devices 26 and 28, which do not typically require a threshold
depletion deposition. Thus, the processing used to enhance the
electrical characteristics of the SRAM devices 22 and 24 does not
add complexity to the processing of or degrade the performance of
the logic devices 26 and 28.
[0019] A similar mask layer is used to provide a photoresist mask
layer through which to deposit a similar well structure 33 into the
SRAM device 22 as depicted in FIG. 3. As mentioned above, this is
the same mask layer through which the threshold adjustment layer
for the SRAM device 22 is deposited. Thus, the formation of the
additional well 33 does not require any additional masking steps,
and likewise does not impact the fabrication or reliability of the
logic devices 26 and 28. Similar to that as described above,
because the dopant used for the well 18 is N type, the dopant used
for the additional well 33 is also N type. FIG. 3 depicts the
devices 22, 24, 26, and 28 at a later stage of processing, where
the sacrificial oxide layer 12 has been removed, gate structures 40
have been created, and source and drain regions have been deposited
with P+ dopant 36 and N+ dopant 38. FIG. 4 depicts the relative
concentration of the various dopants as a function of depth in
semiconductor material 14, as viewed along section 35 in FIG. 3.
Line 42 represents the concentration of the N+ source/drain region
38, line 44 represents the concentration of the P additional well
34, and line 46 represents the concentration of the standard P well
20. Line 48 represents the depth of the bottom of the isolation
structure 16.
[0020] As seen in FIG. 4, that portion of the additional well 34 at
which the concentration of dopant is the greatest as represented by
line 44 on the chart of FIG. 4, extends to a depth in the
semiconductor material 14 that is greater than the depth of the
isolation structure 16 as represented by line 48 on the chart of
FIG. 4. Further, that portion of the additional well 34 at which
the concentration of dopant is the greatest, as represented by line
44 on the chart of FIG. 4, extends to a depth in the semiconductor
material 14 that is shallower or less than the depth of that
portion of the standard well 20 at which the concentration of
dopant is the greatest, as represented by line 46 on the chart of
FIG. 4.
[0021] In a most preferred embodiment, the dopants for the various
structures are deposited using an ion implantation process. Thus,
for example, the additional P well 34 of SRAM device 24 may be
preferably formed by ion implantation of Boron (B.sub.11) at an
energy of between about 25 keV and about 190 keV and a ion dose of
between about 10.sup.11 ions/cm.sup.2 and about 10.sup.14
ions/cm.sup.2, which implants the species at a nominal depth of
between about 0.1 microns and about 0.5 microns. The additional N
well 33 of SRAM device 22 may be preferably formed by ion
implantation of Phosphorus (P.sub.31) at an energy of between about
80 keV and about 360 keV and a ion dose of between about 10.sup.11
ions/cm.sup.2 and about 10.sup.14 ions/cm.sup.2, which implants the
species at a nominal depth of between about 0.1 microns and about
0.5 microns.
[0022] As is apparent from the foregoing discussion, the dopant
type of the additional well tubs 33 or 34 is the same as the dopant
type of the corresponding standard well tubs 18 or 20,
respectively. Thus, other dopant species of the corresponding
dopant type, whether P or N, may be used in place of those
specifically described in the example above. For a standard well
tub 18 or 20 having a nominal concentration of about 10.sup.18
ions/cm.sup.3, the doses described above yield a resultant
concentration of between about 10.sup.17 ions/cm.sup.3 and about
10.sup.20 ions/cm.sup.3 within the additional well tubs 33 and 34.
The processes described above are preferably used when the nominal
depth of the standard well tubs 18 and 20 is between about 0.2
microns and about 1.0 microns, and the depth of the isolation
structures 16 is between about 0.08 microns and about 0.45 microns.
For standard well tubs 18 and 20 having different nominal depths
and dopant concentrations, and for isolation structures 16 having
different depths, the processes described above for the deposition
of the additional well tubs 33 and 34 would be adjusted
commensurately.
[0023] The foregoing description of preferred embodiments for this
invention have been presented for purposes of illustration and
description. They are not intended to be exhaustive or to limit the
invention to the precise form disclosed. Obvious modifications or
variations are possible in light of the above teachings. The
embodiments are chosen and described in an effort to provide the
best illustrations of the principles of the invention and its
practical application, and to thereby enable one of ordinary skill
in the art to utilize the invention in various embodiments and with
various modifications as is suited to the particular use
contemplated. All such modifications and variations are within the
scope of the invention as determined by the appended claims when
interpreted in accordance with the breadth to which they are
fairly, legally, and equitably entitled.
* * * * *