Puchner; Helmut

Patent Applications and Registrations

Patent applications and USPTO patent grants for Puchner; Helmut.The latest application filed is for "sonos type stacks for nonvolatile changetrap memory devices and methods to form the same".

Company Profile

0.39.12

Puchner; Helmut - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory cell array latchup prevention Grant 9,842,629 - Kapre , et al. December 12, 2	2017-12-12
High reliability non-volatile static random access memory devices, methods and systems Grant 9,570,152 - Zain , et al. February 14, 2	2017-02-14
SONOS type stacks for nonvolatile charge trap memory devices and methods to form the same Grant 9,553,175 - Puchner , et al. January 24, 2	2017-01-24
SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same App 20160104789 - Puchner; Helmut ; et al.	2016-04-14
Memory controller devices, systems and methods for translating memory requests between first and second formats for high reliability memory devices Grant 9,304,953 - Zain , et al. April 5, 2	2016-04-05
SONOS type stacks for nonvolatile changetrap memory devices and methods to form the same Grant 9,105,740 - Puchner , et al. August 11, 2	2015-08-11
High reliability non-volatile static random access memory devices, methods and systems Grant 8,861,271 - Zain , et al. October 14, 2	2014-10-14
Circuit with electrostatic discharge protection Grant 8,841,727 - Walker , et al. September 23, 2	2014-09-23
Memory Cell Array Latchup Prevention App 20140211547 - Kapre; Ravindra M ; et al.	2014-07-31
Sonos Type Stacks For Nonvolatile Changetrap Memory Devices And Methods To Form The Same App 20140103418 - PUCHNER; Helmut ; et al.	2014-04-17
Memory Controller Devices, Systems And Methods For High Reliability Memory Devices App 20140006730 - Zain; Suhail ; et al.	2014-01-02
Circuit with electrostatic discharge protection Grant 8,283,727 - Walker , et al. October 9, 2	2012-10-09
Voltage protection device Grant 8,278,684 - Walker , et al. October 2, 2	2012-10-02
SONOS type stacks for nonvolatile change trap memory devices and methods to form the same Grant 8,163,660 - Puchner , et al. April 24, 2	2012-04-24
Circuit with electrostatic discharge protection Grant 8,143,673 - Walker , et al. March 27, 2	2012-03-27
Capacitor triggered silicon controlled rectifier Grant 8,129,788 - Walker , et al. March 6, 2	2012-03-06
Method and circuit for reducing degradation in a regulated circuit Grant 8,063,655 - Puchner , et al. November 22, 2	2011-11-22
High voltage diode Grant 7,936,023 - Jang , et al. May 3, 2	2011-05-03
Non-volatile memory and method of operating the same Grant 7,859,899 - Shakeri , et al. December 28, 2	2010-12-28
Circuits providing ESD protection to high voltage laterally diffused metal oxide semiconductor (LDMOS) transistors Grant 7,838,937 - Walker , et al. November 23, 2	2010-11-23
Drain extended MOS transistor with increased breakdown voltage Grant 7,768,068 - Jang , et al. August 3, 2	2010-08-03
Electrostatic discharge protection device Grant 7,667,241 - Walker , et al. February 23, 2	2010-02-23
SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same App 20100041222 - Puchner; Helmut ; et al.	2010-02-18
Silicon controlled rectifier electrostatic discharge clamp for a high voltage laterally diffused MOS transistor Grant 7,659,558 - Walker , et al. February 9, 2	2010-02-09
CMOS embedded high voltage transistor Grant 7,592,661 - Lee , et al. September 22, 2	2009-09-22
Method and circuit for reducing degradation in a regulated circuit App 20070018678 - Puchner; Helmut ; et al.	2007-01-25
Methods for forming super-steep diffusion region profiles in MOS devices and resulting semiconductor topographies Grant 7,105,413 - Nahm , et al. September 12, 2	2006-09-12
Silicon germanium CMOS channel Grant 6,977,400 - Puchner , et al. December 20, 2	2005-12-20
Methods for forming super-steep diffusion region profiles in MOS devices and resulting semiconductor topographies App 20050215024 - Nahm, Jeong-Yeop ; et al.	2005-09-29
Integrated circuit isolation system Grant 6,831,348 - Puchner , et al. December 14, 2	2004-12-14
Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate Grant 6,759,337 - Aronowitz , et al. July 6, 2	2004-07-06
Shallow trench isolation structure for laser thermal processing Grant 6,734,081 - Puchner , et al. May 11, 2	2004-05-11
Fabrication of metal contacts for deep-submicron technologies Grant 6,727,165 - Puchner , et al. April 27, 2	2004-04-27
Integrated circuit isolation system Grant 6,613,651 - Puchner , et al. September 2, 2	2003-09-02
Integrated circuit isolation system App 20030162366 - Puchner, Helmut ; et al.	2003-08-28
Shallow junction formation Grant 6,605,846 - Puchner August 12, 2	2003-08-12
Silicon germanium CMOS channel App 20030146494 - Puchner, Helmut ; et al.	2003-08-07
Shallow junction formation App 20030045062 - Puchner, Helmut	2003-03-06
Process for forming high dielectric constant gate dielectric for integrated circuit structure Grant 6,511,925 - Aronowitz , et al. January 28, 2	2003-01-28
System to improve SER immunity and punchthrough App 20020173087 - Puchner, Helmut ; et al.	2002-11-21
Reduced soft error rate (SER) construction for integrated circuit structures Grant 6,472,715 - Liu , et al. October 29, 2	2002-10-29
Process For Forming Thin Gate Oxide With Enhanced Reliability By Nitridation Of Upper Surface Of Gate Of Oxide To Form Barrier Of Nitrogen Atoms In Upper Surface Region Of Gate Oxide, And Resulting Product Grant 6,413,881 - Aronowitz , et al. July 2, 2	2002-07-02
Silicon carbide CMOS channel Grant 6,358,806 - Puchner March 19, 2	2002-03-19
Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers Grant 6,331,468 - Aronowitz , et al. December 18, 2	2001-12-18
Dual nitrogen implantation techniques for oxynitride formation in semiconductor devices Grant 6,323,106 - Huang , et al. November 27, 2	2001-11-27
Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same Grant 6,156,620 - Puchner , et al. December 5, 2	2000-12-05
Well formation For CMOS devices integrated circuit structures Grant 6,144,076 - Puchner , et al. November 7, 2	2000-11-07

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