U.S. patent application number 09/467207 was filed with the patent office on 2002-06-20 for dual damascene interconnect structure using low stress flourosilicate insulator with copper conductors.
Invention is credited to BARTH, EDWARD P, BIERY, GLENN A, GAMBINO, JEFFREY P, IVERS, THOMAS H, LEE, HYUN K, LEVINE, ERNEST N, MCDONALD, ANN, STAMPER, ANTHONY K.
Application Number | 20020076917 09/467207 |
Document ID | / |
Family ID | 23854812 |
Filed Date | 2002-06-20 |
United States Patent
Application |
20020076917 |
Kind Code |
A1 |
BARTH, EDWARD P ; et
al. |
June 20, 2002 |
DUAL DAMASCENE INTERCONNECT STRUCTURE USING LOW STRESS
FLOUROSILICATE INSULATOR WITH COPPER CONDUCTORS
Abstract
A metallization insulating structure, having a substrate; a
substantially fluorine free insulating layer formed on the
substrate, having a height, h.sub.i; a fluorine containing
insulating layer formed on the substantially fluorine free
insulating layer, having a height h.sub.f.
Inventors: |
BARTH, EDWARD P;
(RIDGEFIELD, CT) ; BIERY, GLENN A; (HYDE PARK,
NY) ; GAMBINO, JEFFREY P; (WESTFORD, VT) ;
IVERS, THOMAS H; (WAPPINGERS FALLS, NY) ; LEE, HYUN
K; (LAGRANGEVILLE, NY) ; LEVINE, ERNEST N;
(POUGHKEEPSIE, NY) ; MCDONALD, ANN; (NEW WINDSOR,
NY) ; STAMPER, ANTHONY K; (WILLISTON, VT) |
Correspondence
Address: |
TIFFANY L. TOWNSEND
IBM CORPORATION
INTELLECTUAL PROPERTY LAW
BLDG. 300-482, 2070 ROUTE 52
HOPEWELL JUNCTION
NY
12533-6531
US
|
Family ID: |
23854812 |
Appl. No.: |
09/467207 |
Filed: |
December 20, 1999 |
Current U.S.
Class: |
438/624 ;
257/E21.576; 257/E21.579 |
Current CPC
Class: |
H01L 21/76801 20130101;
H01L 21/76807 20130101; H01L 2221/1036 20130101 |
Class at
Publication: |
438/624 |
International
Class: |
H01L 021/4763 |
Claims
What is claimed:
1. A metallization insulating structure, comprising: a substrate; a
substantially fluorine free insulating layer formed on the
substrate, having a height, h.sub.i; a fluorine containing
insulating layer formed on the substantially fluorine free
insulating layer, having a height h.sub.f.
2. The insulating structure according to claim 1 further comprising
a capping layer formed on the fluorine containing insulating
layer.
3. The insulating structure according to claim 2 wherein the
fluorine containing insulating layer comprises a material selected
from the group consisting of fluorinated silicon oxide, fluorinated
amorphous carbon, fluorinated diamondlike carbon and fluorinated
organic polymers.
4. The insulating structure according to claim 2 wherein the
substantially free insulating layer comprises undoped silicon
glass.
5. The insulating structure according to claim 1 further comprising
a capping layer formed prior on the substrate prior to the
substantially fluorine free insulating layer.
6. The insulating structure according to claim 5 wherein the
capping layer comprises a material selected from the group
consisting of silicon nitride, silicon carbide and hydrogenated
silicon carbide, or combinations thereof.
7. The insulating structure according to claim 5 wherein the
substantially free insulating layer comprises undoped silicon
glass.
8. The insulating structure according to claim 5 wherein the
fluorine containing insulating layer comprises a material selected
from the group consisting of fluorinated silicon oxide, fluorinated
amorphous carbon, fluorinated diamondlike carbon and fluorinated
organic polymers.
9. A metallization structure, comprising: a substrate; a
substantially fluorine free insulating layer formed on the
substrate, having a height, h.sub.i; a fluorine containing
insulating layer formed on the substantially fluorine free
insulating layer, having a height h.sub.f; a patterned metal
structure, the metal structure having sidewalls and a bottom, the
bottom of the metal structure in contact with the substrate and the
sidewalls of the metal structure in contact with the substantially
fluorine free insulating layer and the fluorine containing
insulating layer.
10. The metallization structure according to claim 9 wherein the
patterned metal structure comprises at least two portions, each
portion having a height.
11. The metallization according to claim 10 wherein the height of
one of the at least two portions is greater than the height of the
substantially fluorine free layer.
12. The metallization according to claim 10 wherein the height of
one of the at least two portions is less than the height of the
fluorine containing layer.
13. The metallization according to claim 11 wherein the height of
one of the at least two portions is less than the height of the
fluorine containing layer.
14. The metallization according to claim 13 wherein the portion
with the height less than the height of the fluorine containing
layer is a line.
15. The metallization according to claim 14 wherein the portion
with the height greater than the height of the substantially
fluorine free layer is a via.
16. A method of forming a metallization insulating structure,
comprising the following steps: depositing a substantially fluorine
free insulating layer on a preexisting substrate, having a height,
h.sub.i; and forming a fluorine containing insulating layer on the
substantially fluorine free insulating layer, having a height
h.sub.f.
17. The method according to claim 16 further comprising the steps
of patterning the layer and depositing a metal.
18. The method according to claim 17 wherein the patterning
comprises at least two portions, each portion having a height.
19. The method according to claim 18 wherein the height of one of
the at least two portions is greater than height of the
substantially fluorine free insulating layer and the height of the
other of the at least two portions is less than the height of the
fluorine containing insulating layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention generally relates to semiconductor
devices and manufacturing and, more particularly, to methods and
structures which prevent degradation in semiconductor device
wiring.
[0003] 2. Background Description
[0004] Degradation can occur in metal lines in contact with
insulator materials containing fluorine. This degradation is a
serious concern because it represents a potential failure mechanism
for an integrated circuit, IC. The degradation problem is costly to
the industry by virtue of the process monitoring, inspections, and
equipment maintenance requirements that it entails.
[0005] The performance of advanced semiconductor devices is
becoming increasingly limited by the delays in the back-end-of-line
(BEOL) interconnections. These delays are dependent on both the
resistance and capacitance of the wiring structures, which are
partially determined by the material properties (resistivity and
dielectric constant) of the conductors and insulators used.
[0006] Copper is being used as the conductor for several emerging
technology generations to address at least the issue of
resistivity. Copper metallurgy formation is possible using a dual
damascene integration scheme. In an ongoing effort to lower overall
capacitance wherever possible, several low dielectric constant
insulators are being investigated for reducing BEOL capacitance.
One leading candidate is fluorosilicate glass (FSG) which can
reduce the insulator dielectric constant while maintaining many
advantages of inorganic, plasma-enhanced CVD films.
[0007] Dual damascene wiring consists of wiring trenches and
vertical vias between the trenches, which are filled with copper.
Typically the copper in the trenches and vias is cladded with a
thin layer of refractory metal or metal nitrides containing Ta, Ti,
or W. There are a number of specific challenges in using FSG
insulators with dual-damascene copper integration. Chiefly, the
compatibility of commonly used metallization schemes (liners,
diffusion barriers, seed layers, etc) with free fluorine species is
of concern. Additionally, the reliability of damascene
interconnects is generally thought to be sensitive to the stresses
imposed by the insulators and other layers necessary when forming
conducting lines and vias. It is recognized that fluorine stability
of FSG materials can be increased by careful control of deposition
variables. For some FSG films which are otherwise suitable for
integration with copper dual damascene interconnections, this
stability is inversely related to the mechanical stresses in the
FSG insulator films. This relationship, along with the
contamination susceptibility of copper interconnections to fluorine
species, poses particular difficulties for this integration.
[0008] For example, undoped PECVD silane oxide has a relative
dielectric constant of 4.3. As SiF.sub.4 doping is added to the
plasma, the resulting fluorine incorporation into the film
decreases the dielectric constant. The fluorine content in the film
is typically quantified by FTIR measurement of the Si--F:SiO bond
ratio. Film stress correlates with the fluorine content. Table 1
exemplifies the relationship between fluorine content, dielectric
constant and stress of some FSG films. Based on reliability data
collected on standard homogeneous FSG films (i.e. single layer)
integrated into dual damascene copper wiring, we have determined
that films with Si--F:Si--O bond ratios above 1.2% can attack the
interface between the via and the underlying copper wire resulting
in increased via resistance and via opens. Although decreasing the
Si--F:Si--O ratio to less than 0.6% eliminates the via interface
problem, the high stress of the low fluorine-content FSG film
causes significant manufacturing and reliability problems with the
resulting structures.
1 Si--F:SiO k stress 0 4.1 -1.0E.sup.9 dynes/cm.sup.2 <0.5% 4.1
-1.8E.sup.9 0.6% 3.8 -1.2E.sup.9 1.2% 3.8 -1.1E.sup.9 1.9% 3.7
-1.0E.sup.9 2.2% 3.6 -0.9E.sup.9 2.5% 3.6 -0.9E.sup.9
[0009] Table 1: Dielectric constant and film stress as a function
of fluorine content (Si--F:Si--O bond ratio) for FSG films.
SUMMARY OF THE INVENTION
[0010] It is therefore an object of the present invention to
provide degradation resistance for metals in contact with
fluorine-containing insulator materials.
[0011] It is another objective of this invention to minimize
fluorine poisoning of metals used in IC metallization schemes to
reduce undesired via resistance growth and to enhance the contact
between a metallization layer and the metal in a via plug.
[0012] These and other objectives are achieved in the present
invention by providing a metallization insulating structure,
comprising:
[0013] a substrate;
[0014] a substantially fluorine free insulating layer formed on the
substrate, having a height, h.sub.i;
[0015] a fluorine containing insulating layer formed on the
substantially fluorine free insulating layer, having a height,
h.sub.f.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 is a cross sectional view of a typical line/via
configuration
[0017] FIG. 2 is a cross sectional view of an embodiment of the
structure of the instant invention.
[0018] FIG. 3 is a cross sectional view of an embodiment of the
structure of the instant invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0019] For purposes of the present invention, the terminology
"degradation", can mean two things. First as used in connection
with metal contact and metal-based conductors of electricity,
degradation encompasses "corrosion" or "poisoning" of a metal.
"Corrosion" of a metal line or metal contact by exposure to
fluorine means formation of a metal fluoride compound from fluorine
and the metal via chemical reaction. "Poisoning" of a metal by
exposure to fluorine means physical infiltration of the metal by
fluorine as a contaminant in an amount adequate to increase the
contact resistance of the contaminated metal interfaces. Second,
degradation is the negative effect on the reliability or electrical
properties of the interconnection, due either to the chemical or
physical influence of a species.
[0020] While not desiring to be bound to any particular theory, it
is thought that fluorine-containing insulating materials tend to
release fluorine constituents during patterning of metal lines and
metal conductors, particularly in the form of fluorine (F) or
fluorine gas (F.sub.2), which initiates and/or promotes the
corrosion and/or poisoning of metals, such as aluminum, copper,
tantalum, or titanium, that become exposed to and infiltrated by
the released fluorine. This phenomenon has been observed to occur
whether the fluorine is an intentional component of the insulator
material or even an inadvertent contaminant thereof. For instance,
fluorine has been found by the present investigators to be a
contaminant in commonly-used TEOS (i.e., tetraethylorthosilicate)
based insulator films which are commonly-used as insulating films
between metal conductor lines. The presence of fluorine as a
contaminant in the insulator layer nonetheless poses a potential
degradation threat, once released, to adjacent metal conductor
lines.
[0021] It has been observed by the investigators of this invention
that the rate of corrosion experienced in metal exposed to fluorine
is positively related to the concentration of fluorine in the
adjoining insulator film; that is, a lower-concentration of
fluorine in the insulator film causes less metal corrosion than the
case where higher concentrations of fluorine are present in the
insulator film.
[0022] In general, the thickness of the fluorine-free barrier layer
will partially depend on the barrier material and its particular
morphology. The thickness of the fluorine-free barrier layer will
also be based on the depth of the conducting line that will be
formed later. In an embodiment of this invention, the fluorine-free
barrier layer is especially useful in a situation where insulator
films are intentionally doped with fluorine for the purpose of
reducing the dielectric constant of the insulator films in order to
reduce capacitive coupling between adjacent metal lines.
[0023] This invention relates to a structure with a two component
dual damascene dielectric for copper wiring consisting of low
stress SiO.sub.2 (USG), and low stress SiO.sub.xF.sub.y (FSG). In
this structure, the lower and middle portions of the vias are
surrounded by USG; the upper portion of the vias are surrounded by
either FSG or USG; and the wiring trenches are surrounded by an FSG
insulator. Note the interface between the USG and FSG insulators
need not correspond with the intersection of the vias and lines,
but could be tailored for optimal performance, manufacturability
and reliability. Typically the overall height of the FSG insulator
would be greater than the height of the interconnection lines,
while still maintaining a fraction of the via height surrounded by
USG. Finally note that a layer of silicon nitride or other etch
stops could be included between the USG and FSG dielectrics or at
the bottom of the wire trench, to allow for a selective trench RIE
process and more controlled trench depth.
[0024] Referring to the figures generally and FIG. 1 specifically,
there is shown a representation of a typical line/via structure.
The line portion, 1, has a height represented by h.sub.l, and the
via portion has a height represented by h.sub.v. The overall height
of the structure, h.sub.t equals h.sub.v+h.sub.l. When forming the
structure of the instant invention, as shown in FIG. 2, a layer of
a first undoped insulator, 10, is deposited according to any means
known in the art. The height of the undoped layer should not be
equal to h.sub.t. A substantial portion of the beneficial effects
of the structure as outlined in this invention are not achieved
when the height of the undoped layer is significantly greater than
height of the via, h.sub.v. It is preferable if the height of the
undoped material is significantly less than the height of the via,
h.sub.v. A second insulating layer of a doped insulating material,
15, is then deposited. The height of the doped layer should be
equal to h.sub.t-h.sub.v. One of the objectives of the instant
invention is to balance mechanical stress needs with increased
interconnect capacitance. The balance of those two should be kept
in mind when choosing the thicknesses of the doped and undoped
materials. Also in a preferred embodiment, a layer of capping
layer, 20, would be deposited prior to the deposition of the
undoped first insulating layer. The maximum via height, h.sub.v
should then be greater than the height of the undoped insulating
material plus the capping layer material.
[0025] The undoped insulating material can be selected from any
material known in the art. Preferably, the undoped insulating
material would be any silicon dioxide based film which is
compatible with back end of the line (BEOL) processing and does not
contain any significant fluorine content, whether intention or
unintentional. More preferably, the undoped insulating material
would be undoped silica glass (USG). Most preferably, the undoped
material would be plasma enhanced chemical vapor deposited (PECVD)
silica glass from silane or tetraethylorthosilicate (TEOS)
precursors. The doped insulating material can be selected from any
material where the use of the material causes capacitance/stress
tradeoffs. In a preferred final structure should have a mean
compressive stress (as-deposited) of between 0.8E.sup.9 and
1.4E.sup.9 dynes/cm.sup.2. Preferably, the doping would be
fluorine. The fluorinated insulators could be any insulator with
sufficient fluorine content to have a risk of degradation when
integrated with metallization susceptible to fluorine poisoning.
The fluorinated insulating material could be any of the following,
including but not limited to, fluorinated silicon dioxide,
fluorinated amorphous or diamondlike carbon or fluorinated organic
polymers. Preferably, the doped insulating material would be
fluorinated silica glass (FSG). The capping material could be any
material with suitable etch selectivity relative to the chosen
undoped insulator, appropriate copper diffusion barrier properties
and other properties compatible with BEOL processes. An example of
preferred embodiment capping layer materials include, but are not
limited to silicon nitride, silicon carbide or hydrogenated silicon
carbide. Preferably, the capping layer would comprise silicon
nitride Si.sub.xN.sub.y.
[0026] Each of the three layers could be deposited by any means
known in the art. Examples of deposition methods for depositing the
undoped layer include any PECVD or HDP-CVD processed silica film,
for example from SiH.sub.4 or tetraethylorthosilicate (TEOS)
precursors, provided that the average stress of the bilayer stack
is as described above. The FSG film would similarly preferably be
either PECVD or HDP-CVD, using either SiH.sub.4 or TEOS precursors
and using any of a numerous fluorine sources, including SiF.sub.4
or C.sub.2F.sub.6. The dielectric constant of the FSG film can
range from about 3.5 to about 3.9. An example of the method leading
to the final structure of the instant invention is given in Example
I.
EXAMPLE I
[0027] In the instant invention we are presupposing that
h.sub.v=0.6 .mu. and h.sub.l=0.4 .mu.. An underlying wiring level
is capped with 700A of silicon nitride, A 0.4 um layer of undoped
silica glass (USG) is then deposited. A layer of doped silica
glass, FSG, 0.53 .mu. is then deposited. The FSG film which is used
is a dual frequency PECVD film, deposited from SiH.sub.4, N.sub.2O,
inert carrier gases and SiF.sub.4 as the fluorine doping gas. The
deposition is at 380.degree.-400.degree. C., with 2000W of total RF
power. The dielectric constant of the film is about 3.75, the
refractive index is about 1.445 and the as-deposited stress of the
film is about 1.5E.sup.9 dynes/cm.sup.2 in the compressive
direction. The USG film is a single frequency PECVD film, deposited
from SiH.sub.4, N.sub.2O and inert carrier gases. The deposition is
at 380.degree.-400.degree. C., with 1100W of total power. The
dielectric constant is about 4.1, the refractive index is about
1.46 and the stress is about 0.8E.sup.9 in the compressive
direction.
[0028] After forming the two, or three layers metallization can
occur. The metallization can be formed, or patterned, using any
process known in the art but preferably, a dual damascene process
would follow. It should be noted that the instant invention is
independent of the metallization deposition process. When a dual
damascene formation process is used either a line first or a via
first approach is possible. A representation of the insulation
barrier layers with the metallization is shown in FIG. 3, where the
capping layer, 20, is silicon nitride, the undoped layer, 10, is
USG, the doped layer, 15, is FSG and the metallization, 30, is
copper.
[0029] While the invention has been described in terms of its
preferred embodiments, those skilled in the art will recognize that
the invention can be practiced with modification within the spirit
and scope of the appended claims.
* * * * *