U.S. patent application number 09/727426 was filed with the patent office on 2002-05-30 for pin placement method for integrated circuits.
Invention is credited to Dixit, Charutosh, Tetelbaum, Alexander, Yeap, Soon-lin.
Application Number | 20020066066 09/727426 |
Document ID | / |
Family ID | 24922611 |
Filed Date | 2002-05-30 |
United States Patent
Application |
20020066066 |
Kind Code |
A1 |
Tetelbaum, Alexander ; et
al. |
May 30, 2002 |
Pin placement method for integrated circuits
Abstract
A method of pin placement for an integrated circuit includes the
steps of (a) receiving as input a corresponding set of pin
constraints for each pin of a hard macro, (b) receiving as input a
specification for the hard macro, (c) locating pin slots on each
side of the hard macro, (d) finding at least one of a horizontal
interval and a vertical interval on a side of the hard macro for
each pin of the hard macro, and (e) assigning each pin of the hard
macro to a pin slot within the horizontal interval and the vertical
interval that satisfies the corresponding set of pin
constraints.
Inventors: |
Tetelbaum, Alexander;
(Hayward, CA) ; Dixit, Charutosh; (Sunnyvale,
CA) ; Yeap, Soon-lin; (San Jose, CA) |
Correspondence
Address: |
LSI Logic Corporation
1551 McCarthy Blvd.
M/S: D-106 Patent Department
Milpitas
CA
95035
US
|
Family ID: |
24922611 |
Appl. No.: |
09/727426 |
Filed: |
November 30, 2000 |
Current U.S.
Class: |
716/122 |
Current CPC
Class: |
G06F 30/392
20200101 |
Class at
Publication: |
716/10 |
International
Class: |
G06F 017/50 |
Claims
What is claimed is:
1. A method of pin placement for an integrated circuit comprising
the steps of: (a) receiving as input a corresponding set of pin
constraints for each pin of a hard macro; (b) receiving as input a
specification for the hard macro; (c) creating pin slots on each
side of the hard macro; (d) finding at least one of a horizontal
interval and a vertical interval on a side of the hard macro for
each pin of the hard macro; and (e) assigning each pin of the hard
macro to a pin slot within the horizontal interval and the vertical
interval that satisfies the corresponding set of pin
constraints.
2. The method of claim 1 wherein each corresponding set of pin
constraints includes at least one of no constraint, a horizontal
position constraint, a vertical position constraint, a row
constraint, a column constraint, a side constraint, and a metal
layer constraint.
3. The method of claim 1 wherein step (c) comprises assigning a
metal layer to each of the pin slots.
4. The method of claim 3 wherein step (c) comprises assigning a
metal layer to each of the pin slots in an alternating
sequence.
5. The method of claim 1 wherein step (e) includes creating an
additional pin slot within the horizontal interval or the vertical
interval if no pin slot therein is available.
6. A computer program product comprising: a medium for embodying a
computer program for input to a computer; and a computer program
embodied in the medium for causing the computer to perform the
following functions: (a) receiving as input a corresponding set of
pin constraints for each pin of a hard macro; (b) receiving as
input a specification for the hard macro; (c) creating pin slots on
each side of the hard macro; (d) finding at least one of a
horizontal interval and a vertical interval on a side of the hard
macro for each pin of the hard macro; and (e) assigning each pin of
the hard macro to a pin slot within the horizontal interval and the
vertical interval that satisfies the corresponding set of pin
constraints.
7. The computer program product of claim 6 wherein each
corresponding set of pin constraints includes at least one of no
constraint, a horizontal position constraint, a vertical position
constraint, a row constraint, a column constraint, a side
constraint, and a metal layer constraint.
8. The computer program product of claim 6 wherein function (c)
comprises assigning a metal layer to each of the pin slots.
9. The computer program product of claim 6 wherein function (c)
comprises assigning a metal layer to each of the pin slots in an
alternating sequence.
10. The computer program product of claim 6 wherein function (e)
includes creating an additional pin slot within the horizontal
interval or the vertical interval if no pin slot therein is
available.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates generally to design tools for
integrated circuits. More specifically, but without limitation
thereto, the present invention relates to a method of pin placement
for hard macros.
[0002] Integrated circuits typically include building block
circuits called hard macros or "hardmacs". Previous methods of
defining pin placement for hard macros in the design of an
integrated circuit do not consider all possible constraints on pin
placement, disadvantageously resulting in a less than optimum pin
placement. Pin constraints are created by a floorplanning tool or a
circuit designer to ensure timing closure and efficient interface
to the top-level block where the hard macro is instantiated. Also,
the pin constraints impact the placement of cells inside the hard
macro. For example, a pin constraint may place a pin on a certain
side of the hard macro (side constraint), on a selected layer
(layer constraint), in a given row (row constraint) or column
(column constraint) defining the hard macro area, in a given
position, or in a specific sequence.
SUMMARY OF THE INVENTION
[0003] The present invention advantageously addresses the problems
above as well as other problems by providing a method of pin
placement for hard macros that recognizes all pin constraints and
satisfies a maximum number thereof.
[0004] In one embodiment, the present invention may be
characterized as a method of pin placement for an integrated
circuit that includes the steps of (a) receiving as input a
corresponding set of pin constraints for each pin of a hard macro,
(b) receiving as input a specification for the hard macro, (c)
creating pin slots on each side of the hard macro, (d) finding at
least one of a horizontal interval and a vertical interval on a
side of the hard macro for each pin of the hard macro, and (e)
assigning each pin of the hard macro to a pin slot within the at
least one of a horizontal interval and a vertical interval that
satisfies the corresponding set of pin constraints.
[0005] In another embodiment, the present invention may be
characterized as a computer program product that includes a medium
for embodying a computer program for input to a computer and a
computer program embodied in the medium for causing the computer to
perform the following functions: (a) receiving as input a
corresponding set of pin constraints for each pin of a hard macro,
(b) receiving as input a specification for the hard macro, (c)
creating pin slots on each side of the hard macro, (d) finding at
least one of a horizontal interval and a vertical interval on a
side of the hard macro for each pin of the hard macro, and (e)
assigning each pin of the hard macro to a pin slot within the
horizontal interval or the vertical interval that satisfies the
corresponding set of pin constraints.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] The above and other aspects, features and advantages of the
present invention will be more apparent from the following more
specific description thereof, presented in conjunction with the
following drawings wherein:
[0007] FIG. 1 is a diagram of a pin placement method on a hard
macro according to an embodiment of the present invention;
[0008] FIG. 2 is a diagram of pin slots illustrating a layer
assignment for the pin placement method of FIG. 1; and
[0009] FIG. 3 is a flowchart of the method for pin placement
illustrated in FIG. 1 and FIG. 2.
[0010] Corresponding reference characters indicate corresponding
elements throughout the several views of the drawings.
DETAILED DESCRIPTION OF THE DRAWINGS
[0011] The following description is presented to disclose the
currently known best mode for making and using the present
invention. The scope of the invention is defined by the claims.
[0012] Any combination (or none) of non-conflicting constraints
such as horizontal position, vertical position, side, row, and
column constraints may be specified in a pin definition file using
a convenient syntax by a user or as the output of the TERA system,
a floorplanning design tool that determines hard macro placement
inside the top-level block and creates pin and cell constraints for
the hard macro. For example, if a horizontal position pin
constraint is specified, then either the top or bottom side is also
specified to indicate on which side the pin is to be placed. If a
vertical position pin constraint is specified, then either the left
or right side is also specified to indicate on which side the pin
is to be placed. Horizontal and vertical position constraints may
be conveniently specified as positive integers assigned to pin
positions, i.e., if 100 pins are to be placed on the top side of
the hard macro, then "2" corresponds to position 2 among pin
positions (1, 2, 3, . . . , 100). Offsets from the horizontal and
vertical positions, if specified, are ignored, because offsets are
specified in physical units, while symbolic units are used to
determine relative placement of pins and cells. Pins having top or
bottom side constraints may only be constrained to odd layers such
as one, three, or five, because wires in odd-numbered layers
generally run vertically, while wires in even-numbered layers
generally run horizontally. Likewise, pins having left and right
side constraints may only be constrained to even layers such as two
and four. If a pin is not constrained, then its placement is
determined by placement of the data path or net and the control
cells that are connected to the pin.
[0013] FIG. 1 is a diagram 100 of a pin placement for an
unconstrained pin on a hard macro. Shown in FIG. 1 are a hard macro
boundary 102, hard macro cells 104, a net 106, a vertical interval
108, a horizontal interval 110, a pin 112, and placement columns
114. The hard macro boundary 102, the hard macro cells 104, and the
net 106 are included in a hard macro specification that may be
generated according to well known techniques. The vertical interval
108 and the horizontal interval 110 are selected so that if the pin
112 is placed at any point within either the vertical interval 108
and the horizontal interval 110, then the net 106 connecting the
pin 112 to the cells 104 has minimal length.
[0014] Unconstrained pins are usually connected to control signals
and are located on the left or right side of a datapath hard macro,
which have a special structure in which data paths run vertically
and control signals run horizontally.
[0015] A layer constraint specifies a metal layer of the hard macro
to which the pin is to be assigned. If a layer constraint is
specified for a bus connected to many pins, then that layer
constraint is propagated to every pin connected to the bus that
does not already have a pin constraint that override the layer
constraint. For example, a left side constraint would override a
layer 1 constraint because a left side constraint requires a
horizontal wire, which generally is only available in an
even-numbered layer. If no layer constraint is specified for a bus
connected to many pins, individual bus pins may be constrained to
different layers. If there are no layer constraints for a pin, then
a layer is assigned to the pin by assigning the pin to a pin
slot.
[0016] FIG. 2 is a diagram 200 of pin slots illustrating a layer
assignment for the pin placement method of FIG. 1. Shown in FIG. 2
are the hard macro boundary 102 and pin slots 202. Each pin slot is
located, for example, on a spacing of one grid unit defined in the
hard macro specification. Layers are then assigned to the pin slots
202 in an alternating sequence. For example, along the top and
bottom sides metal layer 1 may be assigned to one pin slot, metal
layer 3 may be assigned to the next pin slot, metal layer 1 may be
assigned to the next pin slot, metal layer 3 may be assigned to the
next pin slot, etc. Along the left and right sides, metal layer 2
may be assigned to one pin slot, metal layer 4 may be assigned to
the next pin slot, metal layer 2 may be assigned to the next pin
slot, metal layer 4 may be assigned to the next pin slot, and so
on. Current hard macro designs do not generally use layer 5,
however, a set of pin slots in layer 5 may be created. The x-y
coordinates of pin slots in layer 5 may coincide with the x-y
coordinates in layers 1 and 3, but in 3D space, the z-coordinates
will differ for each layer.
[0017] Each pin of the hard macro is assigned to one of the pin
slots 202. If a layer constraint is specified for the pin, the pin
may be assigned to a pin slot 202 having the same layer assignment
as the layer constraint. A pin for which no layer constraint is
specified may be assigned to any pin slot.
[0018] If there is not enough space on a side of the hard macro to
place all the pins assigned to the side, then the side is increased
accordingly. Typically, all the space on a side is available for
pin placement. This includes the space between placement columns
114 in FIG. 1, unless that space has been reserved for other
applications, such as clock, signal, or power. For example, if
there is insufficient space for pin placement on the top side of
the hard macro, then additional pin slots are created at the right
end of the hard macro boundary 102 to accommodate all unplaced pins
that are not column constrained. If a pin is column constrained and
cannot be placed in the column to which the pin is constrained,
then the pin is placed in the adjacent space to the right of the
column. If the column pin capacity is exceeded, an additional pin
slot is created between columns to accommodate the pin. Because the
pin slot positions are only relative (not physical), no changes
need be made to the pin slots that were assigned before the
additional pin slots are inserted.
[0019] FIG. 3 is a flowchart 300 of the method for pin placement
illustrated in FIG. 1 and FIG. 2 that may be used to implement a
computer program. Step 302 is the entry point for the flow chart
300. Step 304 receives as inputs the hard macro specifications
described above for pin placement and the pin constraints. Step 306
defines pin slots along each side of the hard macro. Step 308
assigns a metal layer to each pin slot. Step 310 initializes a
current pin to the first pin of the hard macro. Step 312 finds a
horizontal interval and a vertical interval for pin placement in
which the net connecting the current pin and associated cells has
minimal length. Step 314 checks whether the current pin is
constrained to a horizontal position, a vertical position, a side,
a row, a column, or a metal layer. If yes, step 316 checks whether
a pin slot within the vertical interval and the horizontal interval
that satisfies the pin constraints is available. If not, Step 318
creates an additional pin slot within the vertical interval and the
horizontal interval. Step 320 assigns the current pin to the pin
slot. Step 322 checks whether all the pins of the hard macro have
been assigned to pin slots. If not, Step 324 increments the current
pin to the next pin and transfers control back to step 312. If all
the pins of the hard macro have been assigned, then step 326 exits
the flowchart 300.
[0020] By the method described above, the optimum pin placement for
each pin of a hard macro may be found that minimizes net length and
recognizes all pin constraints.
[0021] While the invention herein disclosed has been described by
means of specific embodiments and applications thereof, other
modifications, variations, and arrangements of the present
invention may be made in accordance with the above teachings other
than as specifically described to practice the invention within the
spirit and scope defined by the following claims.
* * * * *