Tetelbaum; Alexander

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tetelbaum; Alexander.The latest application filed is for "charge pump with matched currents".

Company Profile

2.49.36

Tetelbaum; Alexander - Beer Sheva IL
- Beer Sheva IL
Tetelbaum; Alexander - Hayward CA
Tetelbaum; Alexander - Walnut Creek CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Charge pump with matched currents Grant 9,413,363 - Bass , et al. August 9, 2	2016-08-09
Systems, circuitry, and methods for decoding pulse width modulated signal Grant 9,397,648 - Elran , et al. July 19, 2	2016-07-19
Charge Pump with Matched Currents App 20160043636 - Bass; Simon ; et al.	2016-02-11
Programmable slew rate power switch Grant 8,922,176 - Tetelbaum , et al. December 30, 2	2014-12-30
Programmable slew rate power switch Grant 08922176 -	2014-12-30
Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer Grant 8,775,995 - Molina , et al. July 8, 2	2014-07-08
Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same Grant 8,694,937 - Tetelbaum , et al. April 8, 2	2014-04-08
Circuit Timing Analysis Incorporating the Effects of Temperature Inversion App 20140089881 - Tetelbaum; Alexander	2014-03-27
Circuit timing analysis incorporating the effects of temperature inversion Grant 8,645,888 - Tetelbaum February 4, 2	2014-02-04
System and method for designing integrated circuits that employ adaptive voltage scaling optimization Grant 8,539,424 - Tetelbaum September 17, 2	2013-09-17
System And Method For Taking Inter-clock Correlation Into Account In On-chip Timing Derating App 20130239079 - Tetelbaum; Alexander	2013-09-12
Programmable Slew Rate Power Switch App 20130229166 - TETELBAUM; Alexander ; et al.	2013-09-05
Timing signoff system and method that takes static and dynamic voltage drop into account Grant 8,516,424 - Tetelbaum , et al. August 20, 2	2013-08-20
Timing error sampling generator and a method of timing testing Grant 8,473,890 - Tetelbaum , et al. June 25, 2	2013-06-25
System And Method For Reducing Integrated Circuit Timing Derating App 20130152034 - Tetelbaum; Alexander	2013-06-13
Implementing And Checking Electronic Circuits With Flexible Ramptime Limits And Tools For Performing The Same App 20130080988 - Tetelbaum; Alexander ; et al.	2013-03-28
Timing Signoff System And Method That Takes Static And Dynamic Voltage Drop Into Account App 20130080986 - Tetelbaum; Alexander ; et al.	2013-03-28
Intelligent dummy metal fill process for integrated circuits Grant 8,397,196 - Tetelbaum March 12, 2	2013-03-12
Method And Apparatus Of Core Timing Prediction Of Core Logic In The Chip-level Implementation Process Through An Over-core Window On A Chip-level Routing Layer App 20130043602 - Molina; Rube Salvador ; et al.	2013-02-21
Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same Grant 8,332,792 - Tetelbaum , et al. December 11, 2	2012-12-11
Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer Grant 8,321,826 - Molina, Jr. , et al. November 27, 2	2012-11-27
Intelligent Dummy Metal Fill Process For Integrated Circuits App 20120284679 - Tetelbaum; Alexander	2012-11-08
Timing Error Sampling Generator And A Method Of Timing Testing App 20120278780 - Tetelbaum; Alexander ; et al.	2012-11-01
Circuit Timing Analysis Incorporating the Effects of Temperature Inversion App 20120210287 - Tetelbaum; Alexander	2012-08-16
Reducing path delay sensitivity to temperature variation in timing-critical paths Grant 8,225,257 - Tetelbaum July 17, 2	2012-07-17
Timing error sampling generator, critical path monitor for hold and setup violations of an integrated circuit and a method of timing testing Grant 8,191,029 - Tetelbaum , et al. May 29, 2	2012-05-29
Circuit timing analysis incorporating the effects of temperature inversion Grant 8,181,144 - Tetelbaum May 15, 2	2012-05-15
Implementing And Checking Electronic Circuits With Flexible Ramptime Limits And Tools For Performing The Same App 20120017190 - Tetelbaum; Alexander ; et al.	2012-01-19
Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuit Grant 8,010,935 - Tetelbaum , et al. August 30, 2	2011-08-30
Method And Apparatus Of Core Timing Prediction Of Core Logic In The Chip-level Implementation Process Through An Over-core Window On A Chip-level Routing Layer App 20100289112 - Molina, JR.; Ruben Salvador ; et al.	2010-11-18
Timing Error Sampling Generator, Critical Path Monitor For Hold And Setup Violations Of An Integrated Circuit And A Method Of Timing Testing App 20100153895 - Tetelbaum; Alexander ; et al.	2010-06-17
Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer Grant 7,739,639 - Molina, Jr. , et al. June 15, 2	2010-06-15
Reducing Path Delay Sensitivity to Temperature Variation in Timing-Critical Paths App 20100095260 - Tetelbaum; Alexander	2010-04-15
Circuit Timing Analysis Incorporating the Effects of Temperature Inversion App 20100095259 - Tetelbaum; Alexander	2010-04-15
Electronic Design Automation Tool And Method For Optimizing The Placement Of Process Monitors In An Integrated Circuit App 20090282381 - Tetelbaum; Alexander ; et al.	2009-11-12
Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction Grant 7,480,881 - Tetelbaum , et al. January 20, 2	2009-01-20
Method and computer program for detailed routing of an integrated circuit design with multiple routing rules and net constraints Grant 7,370,309 - Tetelbaum May 6, 2	2008-05-06
Method And Computer Program For Static Timing Analysis With Delay De-rating And Clock Conservatism Reduction App 20080046848 - Tetelbaum; Alexander ; et al.	2008-02-21
Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism Grant 7,213,223 - Tetelbaum May 1, 2	2007-05-01
Method and computer program for detailed routing of an integrated circuit design with multiple routing rules and net constraints App 20070079274 - Tetelbaum; Alexander	2007-04-05
Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design Grant 7,178,121 - Tetelbaum February 13, 2	2007-02-13
Method of floorplanning and cell placement for integrated circuit chip architecture with internal I/O ring Grant 7,174,524 - Tetelbaum , et al. February 6, 2	2007-02-06
Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design App 20060294482 - Tetelbaum; Alexander	2006-12-28
Method of finding critical nets in an integrated circuit design Grant 7,107,558 - Tetelbaum , et al. September 12, 2	2006-09-12
Minimal bends connection models for wire density calculation Grant 7,076,406 - Tetelbaum July 11, 2	2006-07-11
Method of automated repair of crosstalk violations and timing violations in an integrated circuit design Grant 7,062,737 - Tetelbaum , et al. June 13, 2	2006-06-13
Method of noise analysis and correction of noise violations for an integrated circuit design Grant 7,062,731 - Tetelbaum June 13, 2	2006-06-13
Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism App 20060112158 - Tetelbaum; Alexander	2006-05-25
Intelligent crosstalk delay estimator for integrated circuit design flow Grant 7,043,708 - Tetelbaum , et al. May 9, 2	2006-05-09
Method of clock driven cell placement and clock tree synthesis for integrated circuit design Grant 7,039,891 - Tetelbaum May 2, 2	2006-05-02
Method of floorplanning and cell placement for integrated circuit chip architecture with internal I/O ring App 20060064662 - Tetelbaum; Alexander ; et al.	2006-03-23
Method and apparatus for implementing a co-axial wire in a semiconductor chip Grant 7,015,569 - Tetelbaum March 21, 2	2006-03-21
Method And Apparatus For Implementing A Co-axial Wire In A Semiconductor Chip App 20060043541 - Tetelbaum; Alexander	2006-03-02
Method of automated repair of crosstalk violations and timing violations in an integrated circuit design App 20060026539 - Tetelbaum; Alexander ; et al.	2006-02-02
Intelligent engine for protection against injected crosstalk delay Grant 6,948,142 - Tetelbaum , et al. September 20, 2	2005-09-20
Integrated design system and method for reducing and avoiding crosstalk Grant 6,907,586 - Al-Dabagh , et al. June 14, 2	2005-06-14
Integrated circuit design system and method for reducing and avoiding crosstalk Grant 6,907,590 - Al-Dabagh , et al. June 14, 2	2005-06-14
Wire delay distributed model Grant 6,880,141 - Tetelbaum April 12, 2	2005-04-12
Method of noise analysis and correction of noise violations for an integrated circuit design App 20050060675 - Tetelbaum, Alexander	2005-03-17
Method of clock driven cell placement and clock tree synthesis for integrated circuit design App 20050050497 - Tetelbaum, Alexander	2005-03-03
Method of finding critical nets in an integrated circuit design App 20050022145 - Tetelbaum, Alexander ; et al.	2005-01-27
Global chip interconnect Grant 6,842,042 - Tetelbaum January 11, 2	2005-01-11
Intelligent crosstalk delay estimator for integrated circuit design flow App 20040250225 - Tetelbaum, Alexander ; et al.	2004-12-09
Intelligent engine for protection against injected crosstalk delay App 20040243956 - Tetelbaum, Alexander ; et al.	2004-12-02
Integrated circuit design flow with capacitive margin Grant 6,810,505 - Tetelbaum , et al. October 26, 2	2004-10-26
Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit Grant 6,725,389 - Tetelbaum , et al. April 20, 2	2004-04-20
Global chip interconnect App 20040046588 - Tetelbaum, Alexander	2004-03-11
Integrated circuit design flow with capacitive margin App 20040010761 - Tetelbaum, Alexander ; et al.	2004-01-15
Method for estimating cell porosity of hardmacs Grant 6,611,951 - Tetelbaum , et al. August 26, 2	2003-08-26
Method of control cell placement to minimize connection length and cell delay Grant 6,609,238 - Tetelbaum August 19, 2	2003-08-19
Method for minimizing clock skew for an integrated circuit Grant 6,594,807 - Tetelbaum , et al. July 15, 2	2003-07-15
Integrated design system and method for reducing and avoiding crosstalk Grant 6,594,805 - Tetelbaum , et al. July 15, 2	2003-07-15
Elmore model enhancement Grant 6,543,038 - Tetelbaum April 1, 2	2003-04-01
Method for estimating porosity of hardmacs Grant 6,532,572 - Tetelbaum March 11, 2	2003-03-11
Pin placement method for integrated circuits Grant 6,449,760 - Tetelbaum , et al. September 10, 2	2002-09-10
Pin placement method for integrated circuits App 20020066066 - Tetelbaum, Alexander ; et al.	2002-05-30

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