U.S. patent application number 09/941221 was filed with the patent office on 2002-03-14 for implementing contacts for bodies of semiconductor-on-insulator transistors.
Invention is credited to Christensen, Todd Alan, Sheets, John Edward II.
Application Number | 20020030229 09/941221 |
Document ID | / |
Family ID | 23898283 |
Filed Date | 2002-03-14 |
United States Patent
Application |
20020030229 |
Kind Code |
A1 |
Christensen, Todd Alan ; et
al. |
March 14, 2002 |
Implementing contacts for bodies of semiconductor-on-insulator
transistors
Abstract
A method and semiconductor structure are provided for
implementing body contacts for semiconductor-on-insulator
transistors. A bulk semiconductor substrate is provided. A mask is
applied to the bulk semiconductor substrate to block an insulating
implant layer in selected regions. The selected regions provide for
body contact for transistors. Holes are formed extending into the
bulk semiconductor substrate. The holes are filled with an
electrically conductive material to create stud contacts to the
bulk semiconductor substrate. In the preferred embodiment, the
semiconductor-on-insulator is silicon on an oxide insulating layer
and the invention provides a body contact for SOI transistors.
Inventors: |
Christensen, Todd Alan;
(Rochester, MN) ; Sheets, John Edward II;
(Zumbrota, MN) |
Correspondence
Address: |
IBM Corporation
Intellectual Property Law, Dept. 917
3605 Highway 52 North
Rochester
MN
55901-7829
US
|
Family ID: |
23898283 |
Appl. No.: |
09/941221 |
Filed: |
August 28, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09941221 |
Aug 28, 2001 |
|
|
|
09478037 |
Jan 5, 2000 |
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Current U.S.
Class: |
257/347 ;
257/E21.339; 257/E21.346; 257/E21.538; 257/E21.563; 257/E21.703;
257/E27.112; 257/E29.021 |
Current CPC
Class: |
H01L 21/266 20130101;
Y10S 438/967 20130101; H01L 29/0653 20130101; H01L 21/76267
20130101; H01L 27/1203 20130101; H01L 21/84 20130101; H01L 21/76243
20130101; H01L 21/743 20130101; H01L 21/26533 20130101 |
Class at
Publication: |
257/347 |
International
Class: |
H01L 031/0392; H01L
027/12; H01L 027/01 |
Claims
What is claimed is:
1. A method for implementing body contacts for
semiconductor-on-insulator transistors comprising the steps of: (a)
providing a bulk semiconductor substrate; (b) applying a mask to
selected regions in said bulk semiconductor substrate, said
selected regions for body contacts for the transistors; (c)
implanting an insulator to create a buried insulating layer above
said bulk semiconductor substrate; said selected regions are masked
to block said implantation in said selected regions; (d) forming
holes extending into said buried insulating layer and said bulk
semiconductor substrate; and (e) filling said holes with an
electrically conductive material to create stud contacts to said
bulk semiconductor substrate:
2. A method for implementing for semiconductor-on-insulator
transistors as recited in claim 1 wherein the steps of applying
said mask to said selected regions and of implanting said insulator
creates a buried insulating layer with said masked regions to
create openings aligned with bodies of said transistors.
3. A method for implementing body contacts for
semiconductor-on-insulator transistors as recited in claim 1
wherein the step of forming holes into said bulk semiconductor
substrate and said insulating layer includes the step of etching
holes into said insulating layer and said bulk semiconductor
substrate.
4. A method for implementing body contacts for
semiconductor-on-insulator transistors as recited in claim 1
wherein said semiconductor is silicon, said insulator is oxygen,
said buried insulating layer is a buried oxide layer and the step
of filling said holes with an electrically conductive material to
create stud contacts to a bulk silicon substrate includes the step
of filling said holes with tungsten to create stud contacts to said
bulk silicon substrate.
5. A method for implementing body contacts for
semiconductor-on-insulator transistors as recited in claim 1
wherein said semiconductor is silicon, said insulator is oxygen;
said buried insulating layer is a buried oxide layer and the step
of filling said holes with an electrically conductive material to
create stud contacts to a bulk silicon substrate includes the step
of filling said holes with copper to create stud contacts to said
bulk silicon substrate.
6. A method for implementing body contacts for
semiconductor-on-insulator transistors as recited in claim 1
wherein said semiconductor is silicon, said insulator is oxygen,
and said buried insulating layer is a buried oxide layer and the
step of filling said holes with an electrically conductive material
to create stud contacts to a bulk silicon substrate includes the
step of filling said holes with aluminum to create stud contacts to
said bulk silicon substrate.
7. A method for implementing body contacts for
semiconductor-on-insulator (SOI) transistors as recited in claim 1
wherein said semiconductor is silicon, said insulator is oxygen,
and said buried insulating layer is a buried oxide layer, and the
step of filling said holes with an electrically conductive material
to create stud contacts to said bulk semiconductor substrate
includes the step of filling said holes with doped semiconductor to
create stud contacts to said bulk semiconductor substrate.
8. A method for implementing body contacts for silicon-on-insulator
(SOI) transistors comprising the steps of: (a) providing a bulk
silicon substrate; (b) applying a mask to selected regions of said
bulk silicon substrate; (c) implanting oxygen to said masked
silicon substrate to create a buried oxide insulating layer and
said masked selected regions to create openings aligned with bodies
of said transistors for body contact for the SOI transistors; (d)
etching holes extending into said insulating layer and said bulk
silicon substrate; and (e) filling said holes with an electrically
conductive material selected from the group consisting of tungsten,
copper, aluminum, gold, and doped semiconductor to create stud
contacts to said bulk semiconductor substrate.
9. An integrated circuit having a silicon-on-insulator device made
by the method of claim 8.
10. A semiconductor structure for implementing body contacts for
silicon-on-insulator (SOI) transistors comprising: (a) a bulk
silicon substrate; (b) SOI transistors formed on said bulk silicon
substrate; (c) a patterned oxygen implant layer, said oxygen
implant blocked in selected regions; said selected regions
providing body contact for the SOI transistors; and (d)
electrically conductive contacts extending into said bulk silicon
substrate.
11. A semiconductor structure for implementing body contacts for
silicon-on-insulator (SOI) transistors as recited in claim 10
further includes connections for a selected voltage potential
connected to said electrically conductive contacts extending into
said bulk silicon substrate.
Description
RELATED APPLICATION
[0001] A related U.S. patent application Ser. No. ______, entitled
"Method and Semiconductor Structure for Implementing Dual Plane
Body Contacts for Silicon-on-Insulator (SOI) Transistors," IBM
Docket No. RO999-179 by Todd Alan Christensen and John Edward
Sheets II which is owned by the assignee herein and which is being
filed on the same day as the present patent application, and which
is hereby incorporated by reference in its entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to a method to implement body
contacts of transistors on semiconductor-on-insulator, especially
silicon-on-insulator (SOI), semiconductor technology.
DESCRIPTION OF THE RELATED ART
[0003] Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
scaling on bulk silicon has been the primary focus of the
semiconductor and microelectronic industry for achieving
Complementary Metal Oxide Semiconductor (CMOS) chip performance and
density objectives. The shrinking of MOSFET dimensions for high
density, low power and enhanced performance requires reduced power
supply voltages. Because power consumption is a function of
capacitance, voltage, and transition frequency, the focus has been
on reducing both the capacitance and the voltage as the switching
frequency increases. As a result, dielectric thickness and channel
length are scaled with power supply voltage. Power supply reduction
continues to be the trend for future low voltage CMOS, however,
transistor performance is severely impacted by both junction
capacitance and the MOSFET body effect at lower voltages. As
technologies scale below 0.25 .mu.m channel lengths, to 0.15 .mu.m
and 0.1 .mu.m and shorter, short channel effects control, gate
resistance, channel profiling and other barriers become an issue
for advanced CMOS technologies. While significant success has been
achieved with successive scaling of bulk CMOS technology, the
manufacturing control issues and power consumption will become
increasingly difficult.
[0004] Silicon-on-insulator (SOI) technology is an enhanced silicon
technology in which an insulating layer is situated above the bulk
CMOS layer. SOI transistors are built in a thin layer of silicon on
top of a buried insulator, typically silicon oxide or glass, with
bulk silicon below the buried insulator. Using SOI technology
eliminates many of the concerns and obstacles of bulk silicon CMOS
at low power supply voltages. SOI has significant advantages over
bulk CMOS technology and will achieve the scaling objectives of low
power and high switching frequency for future technologies. SOI
provides low power consumption, low leakage current, low
capacitance diode structures, good subthreshold IN
(current/voltage) characteristics, a low soft error rate from both
alpha particles and cosmic rays, good SRAM access times, to name
only some of the technology benefits offered by SOI. Because of
these advantages, SOI technology is especially useful in portable
and wireless applications.
[0005] SOI technology allows for the mapping of standard advanced
technologies into an SOI technology without significant
modifications. SOI process techniques include epitaxial lateral
overgrowth, lateral solid-phase epitaxy and full isolation by
porous oxidized silicon. SOI networks can be constructed using the
semiconductor process of techniques of separation by implanted
oxygen and wafer-bonding and etch-back because they achieve low
defect density, thin film control, good minority carrier lifetimes
and good channel mobility characteristics. Structural features are
defined by shallow-trench isolation. Shallow trench isolation
eliminates planarity concerns and multidimensional oxidation
effects, thereby allowing technology migration and scaling to
sub-0.25 .mu.m technologies.
[0006] FIGS. 1 and 2 illustrate a conventional SOI transistor. FIG.
1 illustrates a cross section through the width of a traditional
SOI transistor. The SOI transistor has a polysilicon gate, a gate
oxide over a thin silicon layer with isolation oxide, over a buried
oxide, over the bulk silicon substrate. Performance of SOI
transistors is increased due to reduced diffusion capacitance and
due to floating body properties resulting in lower transistor
threshold voltages. Since the voltage of the floating body can vary
over time, the threshold voltage also varies. The floating body
effects were considered beneficial because of the increased speed
at which a transistor can switch. Performance, however, cannot be
predicted using transistors in which the bodies are allowed to
float. Floating body transistors, moreover, are extremely sensitive
to nonperfect input voltage on the gates and to noise. Because of
"history effects", moreover, floating body transistors are
difficult to match, in part because of this sensitivity described
above and in part because the voltage on the floating body is
dependent upon previous cycles and the time durations of the cyclic
input. For instance, a high signal immediately after two or three
other high signals might be output too fast in order to synchronize
with other signals. Similarly, a low signal immediately after two
or three high signals might be too slow.
[0007] In situations and circuits in which the effects associated
with floating bodies are undesirable, there are known structures
that can be used to connect the body of the SOI transistor to a
known voltage. However, the known structures add much capacitance
to the device, particularly gate capacitance, thus degrading the
performance of these transistors so that is worse than a
traditional bulk transistor. FIG. 2 illustrates a traditional body
contact of a SOI transistor. Increased polysilicon area is needed
to fabricate the traditional body contact. The increased
polysilicon results in a large increase in capacitance of the SOI
transistor, thus degrading performance.
[0008] In the past, electrically connecting the transistor body to
a fixed voltage typically increased the size of SOI devices and as
such it was considered undesirable. Other attempts have been made
to allow body contact with non-uniformly doped channel regions,
however, the use of non-uniformly doped channel regions may cause
the devices' threshold voltage to change. Other techniques to
contact the body of SOI transistors to a voltage are complex and
involve multiple process steps using multiple films. These
techniques, moreover, often exacerbate the problem that transistors
bodies have high electrical resistance which generates heat. When
switching transistors at high frequencies on the order of
gigahertz, or once every tens, rather than hundreds of picoseconds,
the resistance resulting from large contacts to the transistor
bodies causes delay in the transitions because of the
resistance-capacitive delay and it is difficult to keep the body at
a fixed voltage, especially at ground voltage.
[0009] Existing SOI transistors with body contacts require
significantly more physical area than their counterpart transistors
not having body contacts. Conventional body contacts involving a
large "T" or "L" shaped gate where the horizontal layout segment(s)
separate the active body region from the body contact region
increase the total transistor physical area on the order of fifty
percent. Given the same input signal on a non-body contacted
transistor and depending on transistor width, the added gate area
required by body contacts for SOI transistors typically doubles the
total gate capacitance requiring twice the input rise time. The
increased area and/or delay penalty render the body-contacted SOI
transistors less desirable.
[0010] And yet another undesirable result of traditional body
contacts in a SOI transistor is a large resistance between the
electrical connection between the desired power grid, typically
ground for a NFET body, and the actual body itself. Because the
connection is through thin lightly doped semiconductor levels,
resistances on the order of tens of thousands of ohms are
typical.
[0011] There is thus a need in the semiconductor-on-insulator
industry for a body contact that can operate at high frequencies
but does not have high capacitance nor high resistance,
SUMMARY OF THE INVENTION
[0012] A principal object of the present invention is to provide a
method and semiconductor structure fabricated using the method for
implementing body contacts for semiconductor-on-insulator
transistors. Other important objects of the present invention are
to provide such a method and semiconductor structure for
implementing body contacts for silicon-on-insulator (SOI)
transistors without substantial negative effect and that overcome
many of the disadvantages of prior art arrangements.
[0013] A method for implementing body contacts for
semiconductor-on-insula- tor transistors is disclosed which
comprises the steps of providing a bulk semiconductor substrate;
implanting an insulator to the bulk semiconductor substrate to
create a buried insulating layer while applying a mask to block the
implantation in selected regions; the selected regions used to form
body contacts for the transistors; forming holes extending into the
buried insulating layer and the bulk semiconductor substrate; and
filling the holes with an electrically conductive material to
create stud contacts to the bulk semiconductor substrate. The steps
of applying the mask to the selected regions and of implanting an
insulator creates the buried insulating layer with the masked
selected regions to create openings aligned with bodies of the
transistors. The step of forming holes into the buried insulating
layer and the bulk semiconductor substrate includes the step of
etching holes into the buried insulating layer and the bulk
semiconductor substrate.
[0014] In a preferred embodiment, the semiconductor is silicon, the
implanted insulator is oxygen and the buried insulating layer is a
buried oxide layer, and the step of filling the etched holes with
an electrically conductive material to create stud contacts to a
bulk silicon substrate includes the step of filling the holes with
tungsten to create stud contacts to the bulk silicon substrate. The
etched holes may also be filled with copper; or aluminum; gold; or
a doped semiconductor to create stud contacts to the bulk
semiconductor substrate.
[0015] The invention may also be realized by a method for
implementing body contacts for silicon-on-insulator (SOI)
transistors comprising the steps of providing a bulk silicon
substrate; applying a mask to selected regions of the bulk silicon
substrate; implanting oxygen to create a buried oxide layer above
the bulk silicon substrate; the masked selected regions to create
openings aligned with bodies of the transistors for body contacts
of the SOI transistors; etching holes extending into the buried
oxide insulator layer and the bulk silicon substrate; and filling
the holes with an electrically conductive material selected from
the group consisting of tungsten, copper, aluminum, gold, and doped
semiconductor to create stud contacts to the bulk semiconductor
substrate. The invention also extends to an integrated circuit
having a silicon-on-insulator device made by the method above.
[0016] The invention may also be considered a semiconductor
structure for implementing body contacts for silicon-on-insulator
(SOI) transistors comprising a bulk silicon substrate having SOI
transistors formed on the bulk silicon substrate; a pattered oxygen
implant layer in which the oxygen implant is blocked in selected
regions; the selected regions to provide body contact for the SOI
transistors; and electrically conductive contacts extending into
the bulk silicon substrate. The semiconductor structure also
includes connections for a selected voltage potential connected to
the electrically conductive contacts extending into the bulk
silicon substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The present invention together with the above and other
objects and advantages may best be understood from the following
detailed description of the preferred embodiments of the invention
illustrated in the drawings, wherein:
[0018] FIG. 1 illustrates a conventional SOI transistor;
[0019] FIG. 2 illustrates a conventional SOI transistor with a
conventional contact to the transistor body; and
[0020] FIGS. 3 through 6 are simplified diagrams of the process for
implementing body contacts for semiconductor-on-insulator
transistors in accordance with principles of the invention. It is
suggested that FIG. 6 be printed on the cover of the patent.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0021] Having reference now to the drawings, in FIGS. 3 through 6,
there are shown exemplary sequential steps for implementing body
contacts for transistors in a semiconductor-on-insulator
technology, preferably silicon-on-insulator (SOI) technology in
accordance with the preferred embodiment. A contact to the body of
the transistor is provided while maintaining performance advantage
and without requiring any additional silicon area.
[0022] In accordance with features of the invention, the body
contact of the preferred embodiment is provided from underneath the
transistor body through the buried insulating layer and the buried
bulk semiconductor. By patterning the buried insulating layer,
direct electrical connects from the bulk semiconductor up to the
regions that will become the bodies of the transistors are
provided.
[0023] Referring now to FIG. 3, in the preferred embodiment, a
blank P+/P-Epi doped silicon substrate including a bulk silicon 302
doped with P+, i.e., approximately 10.sup.20 to 10.sup.21 acceptor
atoms, such as boron, and a P-Epi layer 304 of approximately
10.sup.15 to 10.sup.16 acceptors atoms per cubic centimeter can be
used to create a structure of the invention. It should be
understood that any semiconductor-on-insulato- r technology having
a semiconductor insulator on the same or different semiconductor
stack is possible to incorporate the body contacts of the invention
herein. It will be appreciated, moreover, that if silicon
technology is used, a blank N+/N-Epi doped silicon substrate can
also be used to create a structure of the invention.
[0024] Referring to FIG. 4, the insulating oxide formation is
undesirable at the positions of the conductive body contacts 504 so
a patterned mask is applied to define a plurality of openings or
regions 504. The openings 504 become the body contacts in the bulk
silicon layer 302. An appropriate insulator, such as oxygen, is
implanted to create the buried insulating layer 502.
[0025] Referring to FIG. 5, next conventional processing to build,
e.g., a NFET SOI transistor is continued, including a device
isolation layer 602, preferably an oxide layer, a thin gate oxide
604, a polysilicon gate 606, and a body 608. Openings 504 in the
buried insulating layer are aligned with the bodies 608 of the
transistors.
[0026] Referring to FIG. 6, prior to applying a first metallization
layer at the level where ground connections are shown, deep holes
702 are simultaneously etched into the bulk silicon 302 through the
isolating layers 602 and the insulating layer 502. Next the holes
702 are filled with an electrically conductive material 704, such
as tungsten, copper, doped silicon, gold, or aluminum, thus
creating stud contacts to these layers 402 and 302 that can be
connected to voltage supplies or in some cases a varying voltage. A
body contact made according to principles of the invention would
have a body resistance on the order of one ohm per square or less
for a total resistance of approximately ten to twenty ohms or less,
as opposed to the prior art of FIG. 2 which body contact would
typically have a resistance of tens of thousands of ohm per square
for a total resistance of hundreds of thousands of ohms. Typically
the connection to the bulk silicon 302 would be tied to ground and
body contacts to NFETs would utilize this connection. If the bulk
silicon was N+bulk silicon, the bulk could be tied to a high
voltage supply V.sub.dd and PFETs could take advantage of the body
contacts of the invention.
[0027] While the present invention has been described with
reference to the details of the embodiments of the invention shown
in the drawing, these details are not intended to limit the scope
of the invention as claimed in the appended claims.
* * * * *