Sheets; John Edward II

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sheets; John Edward II.The latest application filed is for "semiconductor scheme for reduced circuit area in a simplified process".

Company Profile

0.0.23

Sheets; John Edward II - Zumbrota MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor Scheme for Reduced Circuit Area in a Simplified Process App 20080102627 - Christensen; Todd Alan ; et al.	2008-05-01
Semiconductor Scheme for Reduced Circuit Area in a Simplified Process App 20080093683 - Christensen; Todd Alan ; et al.	2008-04-24
FinFET Body Contact Structure App 20070202659 - Donze; Richard Lee ; et al.	2007-08-30
Polysilicon Conductor Width Measurement for 3-Dimensional FETs App 20070128740 - Donze; Richard Lee ; et al.	2007-06-07
Electrical Open/Short Contact Alignment Structure for Active Region vs. Gate Region App 20070102700 - Donze; Richard Lee ; et al.	2007-05-10
Electrical Open/Short Contact Alignment Structure for Active Region vs. Gate Region App 20070072385 - Donze; Richard Lee ; et al.	2007-03-29
Electrical Open/Short Contact Alignment Structure for Active Region vs. Gate Region App 20070068627 - Donze; Richard Lee ; et al.	2007-03-29
FinFET body contact structure App 20060091463 - Donze; Richard Lee ; et al.	2006-05-04
Semiconductor scheme for reduced circuit area in a simplified process App 20060060926 - Christensen; Todd Alan ; et al.	2006-03-23
Electrical open/short contact alignment structure for active region vs. gate region App 20060060844 - Donze; Richard Lee ; et al.	2006-03-23
Fin FET diode structures and methods for building App 20060063334 - Donze; Richard Lee ; et al.	2006-03-23
Polysilicon conductor width measurement for 3-dimensional FETs App 20060063317 - Donze; Richard Lee ; et al.	2006-03-23
Method and apparatus for improving performance margin in logic paths App 20050201188 - Donze, Richard Lee ; et al.	2005-09-15
Method and apparatus for implementing silicon wafer chip carrier passive devices App 20050192691 - Bartley, Gerald Keith ; et al.	2005-09-01
Method and apparatus to reduce bias temperature instability (BTI) effects App 20050134360 - Aipperspach, Anthony Gus ; et al.	2005-06-23
Ring Oscillator Circuit For Edram/dram Performance Monitoring App 20040100336 - Christensen, Todd Alan ; et al.	2004-05-27
Reduction of parasitic bipolar leakage current in silicon on insulator devices App 20030205759 - Christensen, Todd Alan ; et al.	2003-11-06
Silicon-on-insulator (soi) Semiconductor Structure For Implementing Transistor Source Connections Using Buried Dual Rail Distribution App 20030170936 - Christensen, Todd Alan ; et al.	2003-09-11
Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices App 20030094654 - Christensen, Todd Alan ; et al.	2003-05-22
Silicon-on-insulator SRAM cells with increased stability and yield App 20030058675 - Aipperspach, Anthony Gus ; et al.	2003-03-27
SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies App 20020145174 - Aipperspach, Anthony Gus ; et al.	2002-10-10
Implementing contacts for bodies of semiconductor-on-insulator transistors App 20020030229 - Christensen, Todd Alan ; et al.	2002-03-14
Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors App 20010026990 - Christensen, Todd Alan ; et al.	2001-10-04

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