U.S. patent application number 09/154027 was filed with the patent office on 2002-01-24 for configurable integrated circuit and method of testing the same.
Invention is credited to FUJII, HIROSHIGE, OHUCHI, KAZUNORI, OOWAKI, YUKIHITO, SEKINE, MASATOSHI, YOSHIDA, MASAKO.
Application Number | 20020010885 09/154027 |
Document ID | / |
Family ID | 26540731 |
Filed Date | 2002-01-24 |
United States Patent
Application |
20020010885 |
Kind Code |
A1 |
OHUCHI, KAZUNORI ; et
al. |
January 24, 2002 |
CONFIGURABLE INTEGRATED CIRCUIT AND METHOD OF TESTING THE SAME
Abstract
An integrated circuit has configurable logic blocks that are
reconfigurable, hard-wired logic blocks that carry out fixed
operations, and a memory. The memory stores configuration data for
configuring the configurable logic blocks, block-connection data
for determining connections between the configurable and hard-wired
logic blocks, and partial-circuit-connection data for determining
connections between partial circuits each of which consists of
logic blocks selected among the configurable and hard-wired logic
blocks. These pieces of data are shared by the logic blocks to
reduce the number of memories in the integrated circuit and improve
the packaging density of the integrated circuit.
Inventors: |
OHUCHI, KAZUNORI; (TOKYO,
JP) ; YOSHIDA, MASAKO; (TOKYO, JP) ; OOWAKI,
YUKIHITO; (TOKYO, JP) ; FUJII, HIROSHIGE;
(TOKYO, JP) ; SEKINE, MASATOSHI; (TOKYO,
JP) |
Correspondence
Address: |
OBLON SPIVAK MCCLELLAND MAIER & NEUSTADT PC
FOURTH FLOOR
1755 JEFFERSON DAVIS HIGHWAY
ARLINGTON
VA
22202
US
|
Family ID: |
26540731 |
Appl. No.: |
09/154027 |
Filed: |
September 16, 1998 |
Current U.S.
Class: |
714/724 |
Current CPC
Class: |
G01R 31/318516
20130101 |
Class at
Publication: |
714/724 |
International
Class: |
G01R 031/28 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 17, 1997 |
JP |
9-252473 |
Sep 17, 1997 |
JP |
9-252472 |
Claims
What is claimed is:
1. An integrated circuit comprising: configurable logic blocks that
are reconfigurable; and a configuration memory for holding
configuration data for configuring the configurable logic blocks,
the configurable logic blocks sharing the logic configuration data
stored in the configuration memory.
2. The integrated circuit of claim 1, further comprising:
hard-wired logic blocks for carrying out fixed operations.
3. An integrated circuit comprising: hard-wired logic blocks for
carrying out fixed operations; and a memory for storing
block-connection data for determining connections between the
hard-wired logic blocks, the connections between the hard-wired
logic blocks being reconfigurable according to the block-connection
data.
4. The integrated circuit of claim 3, wherein: logic-block sets are
formed each by connecting logic blocks selected among the
hard-wired logic blocks; and the logic-block sets share the
block-connection data.
5. The integrated circuit of claim 3, wherein: logic-block sets are
formed each by connecting logic blocks selected among the
hard-wired logic blocks; the logic-block sets are grouped to form
partial circuits; connections between the partial circuits are
determined according to partial-circuit-connection data stored in
the memory; and the connections between the partial circuits are
reconfigurable according to the partial-circuit-connection
data.
6. An integrated circuit comprising: configurable logic blocks that
are reconfigurable; hard-wired logic blocks for carrying out fixed
operations; and a memory for storing configuration data for
configuring the configurable logic blocks and block-connection data
for determining connections between the configurable logic blocks
and the hard-wired logic blocks, the configurable logic blocks
being reconfigurable according to the configuration data, the
connections between the configurable logic blocks and the
hard-wired logic blocks being reconfigurable according to the
block-connection data.
7. The integrated circuit of claim 6, wherein: logic-block sets are
formed each by connecting logic blocks selected among the
configurable and hard-wired logic blocks; and the logic-block sets
share the configuration data and block-connection data.
8. The integrated circuit of claim 6, wherein: logic-block sets are
formed each by connecting logic blocks selected among the
configurable and hard-wired logic blocks; the logic-block sets are
grouped to form partial circuits; connections between the partial
circuits are determined according to partial-circuit-connection
data stored in the memory; and the connections between the partial
circuits are reconfigurable according to the
partial-circuit-connection data.
9. An integrated circuit for encryption, having a key processing
circuit and an encryption processing circuit at least one of which
is made of the integrated circuit of claim 3.
10. An integrated circuit for encryption, having a key processing
circuit and an encryption processing circuit at least one of which
is made of the integrated circuit of claim 4.
11. An integrated circuit for encryption, having a key processing
circuit and an encryption processing circuit at least one of which
is made of the integrated circuit of claim 5.
12. An integrated circuit for encryption, having a key processing
circuit and an encryption processing circuit at least one of which
is made of the integrated circuit of claim 6.
13. An integrated circuit f or encryption, having a key processing
circuit and an encryption processing circuit at least one of which
is made of the integrated circuit of claim 7.
14. An integrated circuit for encryption, having a key processing
circuit and an encryption processing circuit at least one of which
is made of the integrated circuit of claim 8.
15. The integrated circuit of claim 1, wherein the configurable
logic blocks are symmetrical with respect to the configuration
memory.
16. A method of testing an integrated circuit having configurable
logic blocks that are reconfigurable, comprising the steps of:
providing the configurable logic blocks with the same configuration
data from a configuration memory that stores configuration data for
configuring the configurable logic blocks; providing the
configurable logic blocks with the same test data from a test data
input unit; comparing operation results provided by the
configurable logic blocks with one another by a comparator; and
determining that any one(s) of the configurable logic blocks is
defective if the operation results are not equal to one another.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to an integrated circuit and a
method of testing the same. In particular, the present invention
relates to an integrated circuit having configurable logic blocks
(CLBs) that are configurable according to external signals and a
method of testing such an integrated circuit.
[0003] 2. Description of the Related Art
[0004] Integrated circuits having CLBs that are configurable
according to external signals are flexible to use, and therefore,
their demand is increasing.
[0005] The integrated circuits having CLBs, however, involve low
packaging density and slow operation speed. Accordingly, they have
never been used in fields where high packaging density and high
operation speed are important.
[0006] FIG. 1A roughly shows a CLB 1 and a CLB memory 3 according
to a prior art. The CLB memory 3 stores data for configuring the
CLB 1. The prior art provides each CLB with a CLB memory. If many
CLBs each having a CLB memory are installed in an integrated
circuit, the CLB memories occupy a large area in the integrated
circuit.
[0007] FIGS. 2A and 2B show an example of the structure of a CLB
according to a prior art. The CLB consists of 2- or 4-input
multiplexers (MUXs) 21, 23, 25, 27, and 29. Each of the 2-input
multiplexers receives a selection signal to select one of two
inputs and outputs the selected one. Each of the 4-input
multiplexers receives two selection signals to select one of four
inputs and outputs the selected one.
[0008] The multiplexers are connected to one another, and the
selection signals are changed so that the multiplexers may realize
the function of a logic block such as an AND, NAND, OR, NOR, or
EXOR logic block.
[0009] The selection signals to the multiplexers and connection
lines between the multiplexers are programmable according to
configuration data stored in the CLB memory 3. Namely, the CLB
memory 3 must have all data necessary for selecting inputs to the
multiplexers 21 to 29 and determining connections between the
multiplexers. As a result, the CLB memory 3 needs a large area.
[0010] The integrated circuits having CLBs are optionally
configurable by a user, and therefore, are advantageous in
shortening a developing period of electronic devices that involves
trial and error and functional modifications. The integrated
circuits having CLBs are also applicable to electronic devices that
are manufactured in small quantities. Some integrated circuits
having CLBs allow a user to configure some CLBs without affecting
other CLBs that are operating.
[0011] In contrast with the CLBs that have the above-mentioned
problems of low packaging density and slow operation speed,
hard-wired logic blocks (HLBS) consisting of fixed elements and
wires achieve high packaging density. For example, an HLB serving
as a 2-input NAND gate is made of only four transistors. On the
other hand, a CLB serving as a 2-input NAND gate must have many
multiplexers and inverters as shown in FIG. 2A. In addition, the
CLB must have a CLB memory. It is said that the packaging density
of CLBs is one tenth or below of that of HLBs.
[0012] In connection with the operation speed, the HLB serving as a
2-input NAND gate involves a single gate stage to pass signals
therethrough. On the other hand, the CLB of FIG. 2 involves many
multiplexers and inverters to pass signals therethrough, to
elongate a signal transmission time. It is said that the operation
speed of CLBs is one tenth or below of that of HLBs.
[0013] Due to these problems, it is difficult to apply CLBs to
fields where packaging density and operation speed are
important.
[0014] Another problem of CLBs is difficulty in testing them
because they are configurable. FIG. 1B shows a method of testing a
CLB according to a prior art. The CLB is a reconfigurable function
unit (RFU) that is configured according to external data SO into,
for example, a parallel multiplier. Data X and Y for a
multiplication are supplied to the RFU, which provides a resultant
output Z. The output Z is examined by a tester to determine whether
or not the RFU is sound.
[0015] This testing method needs a large number of combinations of
input vectors X and Y and many output pins to verify each output Z.
When verifying the output Z, the tester must secure high-speed
operation corresponding to the internal operation frequencies of
the RFU. These factors complicate the testing of CLBs.
SUMMARY OF THE INVENTION
[0016] An object of the present invention is to improve the
packaging density and operation speed of an integrated circuit
having CLBs that are configurable according to external signals,
and make the testing of the integrated circuit easier.
[0017] In order to accomplish the objects, the present invention
provides an integrated circuit having CLBs that share configuration
data stored in a configuration memory, to reduce the number of
configuration memories and improve packaging density.
[0018] The present invention employs, if possible, HLBs to improve
the packaging density and operation speed of the integrated
circuit.
[0019] The present invention reconfigures connections among the
CLBs and HLBs according to block-connection data. The present
invention connects the CLBs and HLBs to form logic-block sets that
share block-connection data, thereby reducing the number of
memories necessary for storing block-connection data and improving
the packaging density.
[0020] The present invention may combine the logic-block sets into
partial circuits whose connections are reconfigurable.
[0021] The present invention symmetrically arranges CLBs with
respect to a CLB memory, to equalize the lengths of wires to the
CLBs.
[0022] The present invention provides CLBs with the same
configuration data and the same test data and compares operation
results provided by the CLBs with one another, to easily test the
CLBs.
[0023] Other and further objects and features of the present
invention will become obvious upon an understanding of the
illustrative embodiments about to be described in connection with
the accompanying drawings or will be indicated in the appended
claims, and various advantages not referred to herein will occur to
one skilled in the art upon employing the invention in
practice.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] FIG. 1A roughly shows a CLB and a CLB memory according to a
prior art;
[0025] FIG. 1B shows a method of testing a CLB according to a prior
art;
[0026] FIGS. 2A and 2B show the structure of a CLB according to a
prior art;
[0027] FIG. 3 shows an integrated circuit having CLBs according to
a first embodiment of the present invention;
[0028] FIG. 4 shows an integrated circuit having CLBs and HLBs
according to a second embodiment of the present invention;
[0029] FIG. 5 shows an integrated circuit having CLBs and HLBs
according to a third embodiment of the present invention;
[0030] FIG. 6 shows a function-fK unit in a key processing flow
realized in an integrated circuit according to a fourth embodiment
of the present invention;
[0031] FIG. 7 shows the key processing flow involving function-fK
units each being equivalent to the function-fK unit of FIG. 6, for
creating an expanded key from an encryption key;
[0032] FIG. 8 shows a function-f unit in an encryption processing
flow realized in the integrated circuit of the fourth
embodiment;
[0033] FIG. 9 shows the encryption processing flow involving
function-f units each being equivalent to the function-f unit of
FIG. 8, for converting a plain text into a cipher text and a cipher
text into a plain text with the use of the expanded keys;
[0034] FIG. 10 roughly shows an integrated circuit having CLBs
according to a fifth embodiment of the present invention;
[0035] FIGS. 11A and 11B roughly show integrated circuits having
CLBs according to a sixth embodiment of the present invention;
[0036] FIG. 12 explains a method of testing an integrated circuit
having CLBs according to a seventh embodiment of the present
invention; and
[0037] FIGS. 13A and 13B explain methods of testing an integrated
circuit according to an eighth embodiment of the present
invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0038] Integrated circuits and methods of testing an integrated
circuit according to the embodiments of the present invention will
be explained with reference to the accompanying drawings.
[0039] FIG. 3 shows an integrated circuit according to the first
embodiment of the present invention. The integrated circuit has
configurable logic blocks (CLBs) 611 to 6n8, an SRAM 31, and a
controller 37. The SRAM 31 holds configuration data for configuring
the CLBs 611 to 6n8. These CLBs share the configuration data stored
in the SRAM 31.
[0040] Under the control of the controller 37, the configuration
data stored in the SRAM 31 is supplied to the CLBs 611 to 6n8
through lines 3a1 to 3ai, 3b1 to 3bj, and 511 to 5n8.
[0041] CLBs that receive the same configuration data provide each
the same function. For example, the CLBs 611 to 618 receive the
same configuration data through the lines 3a3 and 511 to 518. If
the configuration data is to make a CLB an OR logic block, the CLBs
611 to 618 will be each an OR logic block.
[0042] Each CLB processes one-bit data. Namely, the CLBs 611 to 618
process 8-bit data. If there are 8-bit data A of bits a1 to a8 and
8-bit data B of bits b1 to b8 and if an operation of "A+B" is
carried out on the data, the bits al and b1 are successively
supplied to the CLB 611, to carry out an operation of "a1+b1."
Similarly, the bits a2 to a8 and b2 to b8 are supplied to the CLBs
612 to 618, to carry out operations of "a2+b2" to "a8+b8."
[0043] Similarly, the CLBs 621 to 628 serve each as the same logic
block, such as an exclusive OR (EXOR) logic block.
[0044] Unlike the prior art that stores identical configuration
data in each of separate memories provided for CLBs that carry out
the same operation, the first embodiment stores configuration data
in a single memory, to reduce the number of memories and improve
the packaging density of CLBs.
[0045] The first embodiment supplies the same configuration data
from the SRAM 31 to eight CLBs such as the CLBs 611 to 618. This
reduces the number of memories and an area occupied by memories to
one eighth of the prior art.
[0046] If the ratio of an area occupied by operational elements
such as multiplexers and inverters to an area occupied by an SRAM
in an integrated circuit is 50:50, the first embodiment reduces the
SRAM area to one eighth of the prior art and the total of the
element area and SRAM area to 56% of the prior art.
[0047] Although not shown, the integrated circuit of FIG. 3 has
registers for storing data to process and results of intermediate
operations and data lines for connecting the registers to the
operational elements.
[0048] FIG. 4 shows an integrated circuit according to the second
embodiment of the present invention. The integrated circuit has
configurable logic blocks (CLBs) 611 to 6k8, hard-wired logic
blocks (HLBs) 911 to 9f8, an SRAM 312, and a controller 372. The
SRAM 312 stores configuration data for configuring the CLBs and
block-connection data for determining connections among the CLBs
and HLBs.
[0049] The HLBs 911 to 9f8 have fixed functions. Unlike the CLBs,
the HLBs are unable to change their functions according to
configuration data. For example, an HLB to which an exclusive OR
function is assigned serves only as an exclusive OR logic
block.
[0050] It is possible, however, to change connections between the
HLBs, between the CLBs, and between the CLBs and the HLBs. For
example, the output of the HLB 911 is connected to an input of the
CLB 6k1, and the output of the CLB 6k1 to an input of the HLB 9f1.
Without using the CLB, it is possible to connect the output of the
HLB 911 to an input of the HLB 9f1.
[0051] Operations carried out by the CLBs may be taken over by
HLBs. If possible, all operations may be executed by HLBs. Namely,
the CLBs may partly or entirely be replaced with HLBs.
[0052] The size of HLB may be as small as AND circuit, as middle as
Adder circuit, or as large as Arithmetic and Logic Unit.
[0053] Although the HLBs 911 to 9f8 and the CLBs 611 to 6k8 have
the same size in FIG. 4, the HLBs are actually smaller than the
CLBs. Accordingly, partly or entirely replacing the CLBs with HLBs
improves the packaging density of the integrated circuit.
[0054] Since HLBs have higher processing speed than CLBs, partly or
entirely replacing the CLBs with HLBs improves the processing speed
of the integrated circuit.
[0055] The CLBs and HLBs may be connected to form logic-block sets
each to carry out a series of operations. For example, the HLBs 911
and 9f1 and the CLBs 611 and 6k1 are connected to form a
logic-block set. Similarly, the HLBs 918 and 9f8 and the CLBs 618
and 6k8 are connected to form another logic-block set. The
logic-block sets carry out the same series of operations. Namely,
the logic-block sets must have the same combination of logic blocks
that are connected in the same manner because the CLBs 611 to 618
receive the same configuration data, i.e., every eight CLBs share
the same configuration data stored in the SRAM 312. This
arrangement reduces the number of configuration data memories to
one eighth of the prior art. To make the logic-block sets execute
the same series of operations, the logic blocks must be connected
in the same manner in every logic-block set. This means that the
same block-connection data held in the SRAM 312 is shared by the
eight logic-block sets. This reduces the number of
block-connection-data memories to one eighth of the prior art,
thereby improving the packaging density of the integrated
circuit.
[0056] FIG. 5 shows an integrated circuit according to the third
embodiment of the present invention. The integrated circuit has
CLBs C1-611 to C8-6k8, HLBs C1-911 to C8-9f8, an SRAM 313, and a
controller 373. The SRAM 313 stores configuration data for
configuring the CLBs, and block-connection data for determining
connections among the CLBs and HLBs. The SRAM 313 or the controller
373 stores partial-circuit-connectio- n data for determining
connections between partial circuits consisting of logic
blocks.
[0057] Operations carried out by the CLBs may be taken over by
HLBs. If possible, all operations may be executed by HLBs. Namely,
the CLBs may partly or entirely be replaced with HLBs.
[0058] The size of HLB may be as small as AND circuit, as middle as
Adder circuit, or as large as Arithmetic and Logic Unit.
[0059] Under the control of the controller 373, the
block-connection data configures connections between the CLBs,
between the HLBs, and between the CLBs and the HLBs. For example, a
partial circuit C1 for carrying out a series of operations is
formed with an HLB for executing an exclusive OR operation as a
first step, an HLB for executing an add operation as a second step,
and a CLB for executing a cyclic shift operation as a third step.
Partial circuits C1 to C8 are formed to carry out operation series
that may be different from or same with one another.
[0060] Connections between the partial circuits C1 to C8 are
reconfigured according to the partial-circuit-connection data. For
example, the output of the partial circuit C1 is connected to an
input of the partial circuit C2, the output of the partial circuit
C2 to an input of the partial circuit C3, and the output of the
partial circuit C3 to an input of the partial circuit C5. In this
way, partial circuits that are not adjacent to each other may be
connected to each other. It is possible to connect the output of
the partial circuit Cl to an input of the same, to repeatedly use
the same partial circuit several times.
[0061] Under the control of the controller 373, 8-bit data is
supplied to, for example, the partial circuit C1, and the partial
circuit C1 carries out the predetermined series of operations on
the data. Resultant data from the partial circuit C1 is supplied to
an input of the partial circuit C2.
[0062] An integrated circuit according to the fourth embodiment of
the present invention will be explained. This integrated circuit
serves as an encryption processing circuit. There are many
encryption processing algorithms. One of them is FEAL-8 developed
by NTT Corporation, which is disclosed in Japanese Examined Patent
Publication No. 6-90597.
[0063] FIG. 6 shows a function-fK unit in a key processing flow
realized in the integrated circuit of the fourth embodiment. This
key processing flow creates an expanded key from a FEAL-8
encryption key. FIG. 7 shows the key processing flow involving
function-fK units each being equivalent to the function-fK unit of
FIG. 6. FIG. 8 shows a function-f unit in an encryption processing
flow realized in the integrated circuit of the fourth embodiment.
This encryption processing flow converts a plain text into a cipher
text and a cipher text into a plain text with the use of the
expanded keys. FIG. 9 shows the encryption processing flow
involving function-f units each being equivalent to the function-f
unit of FIG. 8.
[0064] The key processing flow and encryption processing flow
repeat the function-fK and function-f eight times each, to deepen
the randomness of data and enhance the security of encryption. The
number of times of repetition is equal to the number of stages.
[0065] In FIGS. 7 and 9, each unit divides 64-bit data into two
pieces of 32-bit data. In FIG. 6, the function-fK unit divides
32-bit data A (B) into 8-bit data .alpha.0, .alpha.1, .alpha.2, and
.alpha.3 (.beta.0, .beta.1, .beta.2, and .beta.3). In FIG. 8, the
function-f unit divides 32-bit data R (L) into 8-bit data r0, r1,
r2, and r3 (10, 11, 12, and 13). 16-bit data K is divided into
8-bit data k0 and k1. In this way, every data is divided into 8-bit
data on which further operations are carried out.
[0066] In FIGS. 6 and 8, a circled "+" indicates a bit-by-bit
exclusive OR operation carried out on two pieces of 8-bit data. If
8-bit data of bits d10 to d17 and 8-bit data of bits d20 to d27 are
received, an exclusive OR of the bits d10 and d20, an exclusive OR
of the bits d11 and d21, . . . , and an exclusive OR of the bits
d17 and d27 are executed. A function Si (i=1 or 0) adds two pieces
of 8-bit data to each other, adds i to the sum, and cyclically
shifts the resultant data to the left by two bits.
[0067] The details of FEAL-8 will not be explained. Any encryption
is exposed to deciphering attacks. Accordingly, the encryption
circuit should be reconfigured periodically or whenever an
encrypted text is transmitted, to change encryption processing and
enhance security.
[0068] The integrated circuit of the fourth embodiment is based on
the third embodiment to achieve the key processing flow and
encryption processing flow. The integrated circuit of the fourth
embodiment can be reconfigured by changing the configurations of
CLBs, connections among CLBs and HLBs, and connections among
partial circuits made of CLBs and HLBs. The wiring of the CLBs or
data connections among the CLBs and HLBs of the fourth embodiment
may partly or entirely be changed to change the encryption
processing and strengthen the security.
[0069] The first to eighth stages of FIGS. 7 and 9 may be realized
with separate circuits or by repeatedly using circuits each
involving a small number of stages, for example, one, two, or four
stages. This is possible because the eight stages carry out similar
operations. For example, a circuit involving a single stage may be
executed eight times, or a circuit involving two stages four times,
or a circuit involving four stages twice, to finish the eight-stage
operations. CLBs need larger space than HLBs. When many CLBs are
used, it is preferable to repeatedly use circuits each having a
small number of stages.
[0070] The controller 373 (FIG. 5) synchronizes operations carried
out by the HLBs and CLBs, controls the number of times of
repetition of the partial circuits C1 to C8, and selects expanded
keys K0 to K15 provided by the function-fK units for the function-f
units.
[0071] The fourth embodiment processes 8-bit data units. Namely,
the fourth embodiment divides input data into 8-bit groups and
carries out the same processes on the first to eighth bits of a
given group. To achieve this, the fourth embodiment provides given
eight CLBs with common configuration data from the SRAM 313, to
configure the eight CLBs to achieve the same function. This reduces
the number of configuration data memories to one eighth of the
prior art, thereby improving the packaging density of the
integrated circuit.
[0072] If possible, the CLBs will be replaced with HLBs to reduce
the area occupied by the logic blocks to one tenth or below of the
prior art, to further improve the packaging density.
[0073] The operation speed of HLBs is about 10 times faster than
that of CLBs. Accordingly, replacing the CLBs with HLBs will
improve the operation speed of the integrated circuit.
[0074] The improved packaging density enables the eight stages of
FIGS. 7 and 9 to be easily laid out in the integrated circuit.
[0075] One partial circuit corresponds to one stage of FIGS. 7 or
9. An integrated circuit having a single stage (a single partial
circuit) may be executed eight times to finish the eight-stage
operation.
[0076] Each of eight partial circuits (C1 to C8) may be executed
one time to finish the eight-stage operation. For example, C1 is
used for the first stage operation, C2 for the second stage
operation, . . . , and C8 for the eighth stage operation. Then,
while the second stage is processing data bits d0 to d7 that have
finished the first stage, the first stage may process the next data
bits d8 to d15. This improves processing performance eight times
higher than the integrated circuit having a single stage that must
be repeated eight times.
[0077] The configuration data memory (313 of FIG. 5) may be an
SRAM, an FRAM (ferroelectric random access memory), or any other
element capable of reading, writing, and storing data. Nonvolatile
memories such as FRAMs are capable of holding configuration data
even after a power source is cut, and therefore, are useful for
such applications that assume frequent power cuts.
[0078] FIG. 10 roughly shows an integrated circuit according to the
fifth embodiment of the present invention. Two CLBs 1a and 1b share
a memory 321 that stores configuration data.
[0079] The same configuration data, i.e., the same signal is
supplied from the memory 321 to the CLBs 1a and 1b. As a result, in
each of the CLBs 1a and 1b, multiplexers select identical signals
and are connected in the same manner. For example, the CLBs 1a and
1b serve each as a NAND logic block. The CLBs 1a and 1b that share
the memory 321 may receive different input data, or the output of
one of them may be supplied to an input of the other.
[0080] The CLBs 1a and 1b are symmetrical with respect to the
memory 321. This arrangement equalizes the wiring resistance and
lengths of the CLBs 1a and 1b, and therefore, is easy to lay out
when designing an integrated circuit.
[0081] FIGS. 11A and 11B roughly show integrated circuits according
to the sixth embodiment of the present invention.
[0082] In FIG. 11A, CLBs 1a and 1b, 1c and 1d, . . . , and 1m and
In are symmetrical with each other on the opposite sides of a
memory 322 that stores configuration data shared by the CLBs. The
number "n" of the CLBs is optional.
[0083] In FIG. 11B, CLBs 1a and 1b, 1c and 1d, . . . , and 1m and
1n are linearly arranged along a memory 323 and are symmetrical
with each other on the opposite sides of the memory 323. All of the
CLBs are in contact with the memory 323. The memory 323 stores
configuration data shared by the CLBs. The number "n" of the CLBs
is optional.
[0084] The same configuration data, i.e., the same signal is
supplied from the memory 322 (323) to the CLBs 1a to 1n.
Accordingly, in each of the CLBs, multiplexers select identical
signals and are connected in the same manner. As a result, all of
the CLBs provide the same function. For example, the CLBs 1a to 1n
serve each as a NAND logic block. The CLBs may receive different
input data, or the output of one of them may be connected to an
input of another.
[0085] Since the CLBs 1a to 1n are symmetrical with respect to the
memory 322 (323), the symmetrical CLBs, e.g., 1a and 1b have the
same wiring resistance and delay. This arrangement is easy to lay
out when designing an integrated circuit.
[0086] The sixth embodiment is capable of reducing the number of
memories used by CLBs to 1/n of the prior art.
[0087] FIG. 12 explains a method of testing an integrated circuit,
according to the seventh embodiment of the present invention. CLBs
1a and 1b are connected to a test data input unit 55 and a
comparator 77 for comparing operation results provided by the CLBs
1a and 1b with each other.
[0088] A memory 321 provides the CLBs 1a and 1b with the same
configuration data. The input unit 55 provides the CLBs 1a and 1b
with the same test data. The CLBs 1a and 1b process the test data
and provide results, which are compared with each other by the
comparator 77.
[0089] Since the CLBs 1a and 1b receive the same configuration
data, they serve each as the same logic block. Since they receive
the same test data, operation results provided by them must be
equal to each other. If the comparator 77 determines that the
operation results are different from each other, one of the CLBs 1a
and 1b is defective.
[0090] The seventh embodiment easily determines whether or not
tested CLBs are sound and greatly reduces testing work compared
with the prior art. The prior art must prepare an output data
pattern for an input data pattern, compare the output data pattern
with actual output data, and determine whether or not tested CLBs
are correct. This testing work is complicated. The seventh
embodiment simply determines whether or not the outputs of tested
CLBs that share a configuration memory are equal to each other, to
greatly simplify the testing work.
[0091] The test data input unit 55 may generate random numbers to
automatically prepare test data, which is commonly supplied to the
CLBs 1a and 1b. The comparator 77 compares operation results
provided by the CLBs 1a and 1b with each other, to determine
whether or not the results are equal to each other. This method
automatically prepares test data to be supplied to the CLBs 1a and
1b, to greatly simplify the testing work. a FIGS. 13A and 13B
explain methods of testing an integrated circuit according to the
eighth embodiment of the present invention. A test data input unit
551 (552) and a comparator 771 (772) for comparing operation
results with each other are connected to CLBs 1a to 1n.
[0092] A memory 322 (323) provides the CLBs 1a to 1n with the same
configuration data. The test data input unit 551 (552) provides the
CLBs 1a to 1n with the same test data. The CLBs 1a to 1n process
the test data and provide operation results. The comparator 771
(772) compares the results with one another and provides a
comparison result.
[0093] Since the same configuration data and the same test data are
supplied to the CLBs 1a to 1n, the operation results provided by
them must be equal to one another. If any one of the results is
different from the others, the corresponding CLB is abandoned or
disabled as defective so that it will not be used.
[0094] The eighth embodiment easily tests CLBs to greatly simplify
the testing work compared with the prior art. The prior art must
prepare an output data pattern for an input data pattern, compare
the output data pattern with actual output data, and determine
whether or not tested CLBs are correct. This testing work is
complicated. The eighth embodiment simply determines whether or not
the outputs of tested CLBs that share a configuration memory are
equal to one another, thereby greatly simplifying the testing
work.
[0095] Not only automatically determining whether or not operation
results of tested CLBs are correct, the eighth embodiment also
identifies defective CLBs and disables them so that they are not
used. As a result, an integrated circuit that contains some
defective CLBs can be used by disabling the defective CLBs, to
improve the yield of integrated circuits and reduce the costs
thereof.
[0096] The test data input unit 551 (552) may generate random
numbers to automatically prepare test data so that the test data
may commonly be supplied to the CLBs 1a to 1n. The comparator 771
(772) compares operation results provided by the CLBs 1a to 1n with
one another and determines whether or not the results are correct.
This method automatically prepares test data to be supplied to the
CLBs 1a to 1n, to eliminate a testing circuit and greatly simplify
the testing work.
[0097] Various modifications will become possible for those skilled
in the art after receiving the teachings of the present disclosure
without departing from the scope thereof.
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