U.S. patent application number 09/867254 was filed with the patent office on 2001-12-06 for method for testing a multiplicity of word lines of a semiconductor memory configuration.
Invention is credited to Brass, Eckhard, Schaffroth, Thilo, Schnabel, Joachim, Schneider, Helmut.
Application Number | 20010048621 09/867254 |
Document ID | / |
Family ID | 7643756 |
Filed Date | 2001-12-06 |
United States Patent
Application |
20010048621 |
Kind Code |
A1 |
Brass, Eckhard ; et
al. |
December 6, 2001 |
Method for testing a multiplicity of word lines of a semiconductor
memory configuration
Abstract
A method for testing a multiplicity of word lines of a
semiconductor memory configuration in a multiple word line wafer
test is described. To prevent a pulling-up of inactive word lines
which are at a negative voltage when the active word lines are
ramped down, the inactive word lines are decoupled from the
negative word line voltage and are connected to a high impedance
shortly before the active word lines are ramped down.
Inventors: |
Brass, Eckhard;
(Unterhaching, DE) ; Schaffroth, Thilo; (Rohrmoos,
DE) ; Schnabel, Joachim; (Munchen, DE) ;
Schneider, Helmut; (Munchen, DE) |
Correspondence
Address: |
LERNER AND GREENBERG, P.A.
Post Office Box 2480
Hollywood
FL
33022-2480
US
|
Family ID: |
7643756 |
Appl. No.: |
09/867254 |
Filed: |
May 29, 2001 |
Current U.S.
Class: |
365/200 |
Current CPC
Class: |
G11C 29/26 20130101 |
Class at
Publication: |
365/200 |
International
Class: |
G11C 029/00 |
Foreign Application Data
Date |
Code |
Application Number |
May 26, 2000 |
DE |
100 26 275.9 |
Claims
We claim:
1. A method for testing a multiplicity of word lines of a
semiconductor memory configuration in a multiple word line wafer
test, which comprises the steps of: inducing a high potential on
some of the word lines resulting in active word lines; floating
remaining ones of the word lines not induced by the high potential
at a negative word line potential with a high impedance, the
remaining ones of the word lines defining inactive word lines;
ramping down the active word lines to a low potential; and
subsequently reconnecting all of the word lines to the negative
word line potential.
2. The method according to claim 1, which comprises connecting the
inactive word lines to the negative word line potential before the
active word lines are ramped down.
3. The method according to claim 1, which comprises setting the
negative word line potential to approximately -0.3 V.
4. The method according to claim 1, which comprises applying the
negative word line potential to the word lines through a
transistor.
5. The method according to claim 1, which comprises setting the
high potential to be a voltage level of approximately 2.9
volts.
6. The method according to claim 1, which comprises setting the low
potential to be approximately 0 volts.
Description
BACKGROUND OF THE INVENTION
Field of the Invention
[0001] The present invention relates to a method for testing a
multiplicity of word lines of a semiconductor memory configuration
in a multiple word line (WL) wafer test in which a number of word
lines are initially ramped up to a high potential and are thus
enabled, and in which the active word lines thus ramped up are then
ramped down to a negative potential.
[0002] In more recent generations of semiconductor memory
configurations such as, for example, in the 0.14 .mu.m SDRAM
generation, inactive word lines, that is to say word lines which
are not activated for writing or reading a memory cell, are not
placed at ground potential, that is to say 0 V, as previously but
up to a slightly negative word line voltage of about -0.3 V. The
negative word line voltage is provided by a separate generator for
this purpose in the semi-conductor memory configuration.
[0003] Compared with the ground potential of 0 V, ramping down the
inactive word lines to a slightly negative voltage has a
significant advantage. The negative word line voltage reduces the
blocking voltage of the selection transistors of the individual
memory cells which allows these transistors to hold data for
longer. In other words, the negative word line voltage leads to an
improvement in the data retention time.
[0004] If semiconductor memory configurations are configured in
such a manner that the inactive word lines are at a slightly
negative word line voltage in order to improve the data retention
time, this leads to problems in the "multiple WL wafer test", in
which a number of the word lines are first ramped up to a high
potential and are thus enabled, and in which then the active word
lines thus ramped up are then brought down to a low potential. In
the multiple word line wafer test, considerably more word lines are
thus ramped up than in the normal operation of the semiconductor
memory configuration.
[0005] If then, after the ramping-up of a multiplicity of the word
lines into the active state, these are ramped down again, these
word lines, due to the very high capacitance of the many active
word lines, will pull up the potential of the voltage during
ramping-down so that it can assume 0 V or higher values. As a
result, the retention time of the inactive memory cells which are
not connected to ramped-up word lines is inevitably impaired
considerably so that it is impossible for memory cell contents to
be lost.
[0006] The problem indicated above does not appear in semiconductor
memory configurations in which the inactive word lines are at
ground potential which is attributable to the fact that the power
system which provides the ground potential is buffered by a much
lower impedance and a much greater capacitance than the power
system supplying the negative word line potential.
[0007] To overcome the problem indicated above it has previously
been thought of to ramp down the active word lines to the negative
word line potential not at once but slowly in two stages in the
multiple word line wafer test, namely to ground potential in a
first step and then to the negative word line potential in a second
step and it is true that, as a result, pulling-up of the negative
word line potential of the inactive word lines can be largely
prevented.
[0008] However, such a two-stage ramping-down of the active word
lines in the multiple word line wafer test is expensive and
requires considerably more time than ramping down in only one
stage.
SUMMARY OF THE INVENTION
[0009] It is accordingly an object of the invention to provide a
method for testing a multiplicity of word lines of a semiconductor
memory configuration that overcomes the above-mentioned
disadvantages of the prior art devices of this general type, which
allows the wafer test to be performed rapidly and without great
expenditure.
[0010] With the foregoing and other objects in view there is
provided, in accordance with the invention, a method for testing a
multiplicity of word lines of a semiconductor memory configuration
in a multiple word line wafer test. The method includes the steps
of: inducing a high potential on some of the word lines resulting
in active word lines; floating remaining ones of the word lines not
induced by the high potential at a negative word line potential
with a high impedance, the remaining ones of the word lines
defining inactive word lines; ramping down the active word lines to
a low potential; and subsequently reconnecting all of the word
lines to the negative word line potential.
[0011] According to the invention, the object is achieved in a
method of the type initially mentioned, in that the word lines not
ramped up and thus inactive are floating at the negative word line
potential with a high impedance before the active word lines are
ramped down, and in that, after the active word lines have been
ramped down, all the word lines are reconnected to the negative
word line potential.
[0012] In the method according to the invention, the inactive word
lines are thus not connected to the negative word line potential
shortly before the active word lines are ramped down in the
multiple word line wafer test. Instead, the inactive word lines are
floated on the negative word line potential at a high impedance. It
is only when active word lines have been ramped down that all the
word lines are also connected to the negative word line
potential.
[0013] Such a procedure is extremely advantageous since the word
lines ramped down can only pull down the inactive word lines
further due to the capacitive coupling between the word lines.
[0014] The method according to the invention can be implemented in
a simple manner without great changes in the existing semiconductor
memory configurations. It is only necessary to adapt the logic of
word line drives supplying the negative word line potential
appropriately to the above procedure or to make the generator
providing the negative word line potential stronger, but this
requires additional chip area.
[0015] It is thus of considerable importance in the method
according to the invention that the inactive word lines are
disconnected from the negative voltage and connected to a high
impedance shortly before the active word lines are ramped down in
the multiple word line wafer test.
[0016] Other features which are considered as characteristic for
the invention are set forth in the appended claims.
[0017] Although the invention is illustrated and described herein
as embodied in a method for testing a multiplicity of word lines of
a semiconductor memory configuration, it is nevertheless not
intended to be limited to the details shown, since various
modifications and structural changes may be made therein without
departing from the spirit of the invention and within the scope and
range of equivalents of the claims.
[0018] The construction and method of operation of the invention,
however, together with additional objects and advantages thereof
will be best understood from the following description of specific
embodiments when read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWING
[0019] The single FIGURE of the drawing is a circuit diagram of a
word line drive according to the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0020] Referring now to the single figure of the drawing in detail,
there is shown an illustrative embodiment of a diagrammatic circuit
of a word line drive for the 0.14 .mu.m SDRAM generation.
[0021] A word line WL is connected to a word line drive WLT formed
of complementary field effect transistors M1, M2 which are
connected in series between a ground potential GND and a word line
drive voltage WLDV of 0 V or 2.9 V, respectively, and are driven
via a precharging voltage bPRCH of also 0 V and 2.9 V respectively.
A field effect transistor M3 is connected between the word line WL
and a negative potential VNWL of -0.3 V and can be driven via a
word line reset signal WLRST of 0 V and 2 V respectively.
[0022] In the multiple word line wafer test, the word line WL is
ramped up to 2.9 V via the word line drive WLT, the transistor M3
being switch off, and is then ramped down again to 0 V.
[0023] If the word line WL shown is an inactive word line and other
word lines, not shown, of the memory cell array are activated, the
inactive word line WL is initially at the negative word line
potential of -0.3 V with the field effect transistor M3 switched
on. Shortly before the active word lines are ramped down, the
inactive word line WL is floated at the negative word line
potential at a high impedance. For this purpose, a corresponding
WLRST signal is applied to the transistor M3 to switch it off. When
the word line drive WLT is also switched off, the inactive word
line WL then floats at the negative word line potential of -0.3 V
with a high impedance.
[0024] Once all the word lines WL of the memory cell array of the
semiconductor memory configuration have been ramped down, all the
word lines WL are reconnected to the negative word line potential
VNWL, for which purpose a corresponding WLRST signal is applied to
the transistor M3.
* * * * *