U.S. patent application number 09/735120 was filed with the patent office on 2001-07-26 for margin-range apparatus for a sense amp's voltage-pulling transistor.
Invention is credited to Beigel, Kurt D., Bruce, Jeffrey D., Cutter, Douglas J., Habersetzer, Daryl L., Ma, Manny K., Miller, James E., Roberts, Gordon D., Stubbs, Eric T..
Application Number | 20010009522 09/735120 |
Document ID | / |
Family ID | 25321559 |
Filed Date | 2001-07-26 |
United States Patent
Application |
20010009522 |
Kind Code |
A1 |
Beigel, Kurt D. ; et
al. |
July 26, 2001 |
Margin-range apparatus for a sense amp's voltage-pulling
transistor
Abstract
As part of a memory array, a circuit is provided for altering
the drive applied to an access transistor that regulates electrical
communication within the memory array. In one embodiment, the
circuit is used to alter the drive applied to a sense amp's
voltage-pulling transistor, thereby allowing modification of the
voltage-pulling rate for components of the sense amp. A sample of
test data is written to the memory array and read several times at
varying drive rates in order to determine the sense amp's ability
to accommodate external circuitry. In another embodiment, the
circuit is used to alter the drive applied to a bleeder device that
regulates communication between the digit lines of the memory array
and its cell plate. Slowing said communication allows defects
within the memory array to have a more pronounced effect and hence
increases the chances of finding such defects during testing. The
circuit is configured to accept and apply a plurality of voltages,
either through a contact pad or from a series of discrete voltage
sources coupled to the circuit.
Inventors: |
Beigel, Kurt D.; (Boise,
ID) ; Cutter, Douglas J.; (Fort. Collins, CO)
; Ma, Manny K.; (Boise, ID) ; Roberts, Gordon
D.; (Meridian, ID) ; Miller, James E.; (Boise,
ID) ; Habersetzer, Daryl L.; (Boise, ID) ;
Bruce, Jeffrey D.; (Meridian, ID) ; Stubbs, Eric
T.; (Boise, ID) |
Correspondence
Address: |
Charles Brantley
Micron Technology, Inc.
Mail Stop 525
8000 S. Federal Way
Boise
ID
83716
US
|
Family ID: |
25321559 |
Appl. No.: |
09/735120 |
Filed: |
December 11, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09735120 |
Dec 11, 2000 |
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09483549 |
Jan 14, 2000 |
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6181617 |
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09483549 |
Jan 14, 2000 |
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09260232 |
Mar 1, 1999 |
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6028799 |
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09260232 |
Mar 1, 1999 |
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08855555 |
May 13, 1997 |
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5877993 |
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Current U.S.
Class: |
365/201 |
Current CPC
Class: |
G11C 29/028 20130101;
G11C 2029/5004 20130101; G11C 29/56 20130101; G11C 29/02 20130101;
G11C 29/026 20130101; G11C 29/12 20130101; G11C 29/50 20130101;
G11C 29/50012 20130101; G11C 29/025 20130101; G11C 29/44 20130101;
G11C 11/401 20130101; G11C 29/48 20130101 |
Class at
Publication: |
365/201 |
International
Class: |
G11C 007/00 |
Claims
What is claimed is:
1. A test mode drive-modifying device for a memory array having at
least one sense amp coupled to a voltage-pulling mechanism,
comprising: a test voltage alteration mechanism, wherein: said test
voltage alteration mechanism is coupled to said voltage-pulling
mechanism; and said test voltage alteration mechanism is configured
to receive a plurality of voltages.
2. The test mode drive-modifying device in claim 1, wherein said
sense amp is a pulldown sense amp.
3. The test mode drive-modifying device in claim 2, wherein said
voltage-pulling mechanism is a transistor.
4. The test mode drive-modifying device in claim 3, wherein said
voltage-pulling mechanism is an n-channel transistor.
5. A test mode driver circuit for a voltage-pulling transistor of a
sense amp, comprising: a conductive path coupled to a gate of said
voltage-pulling transistor; and an apparatus configured to receive
a range of voltages coupled to said conductive path.
6. The test mode driver circuit in claim 5, wherein said apparatus
is a contact pad.
7. A voltage-pulling circuit for a sense amp, comprising: a main
conductive path coupled to said sense amp; and a plurality of
secondary conductive paths selectively coupled to said main
conductive path, wherein each of said plurality of secondary
conductive paths is configured to receive a generally discrete
voltage.
8. The voltage-pulling circuit in claim 7, wherein said sense amp
is a pullup sense amp.
9. A driving circuit for a voltage-pulling transistor of a sense
amp, comprising: a selective coupling apparatus coupled to and
electrically interposed between: a test conduit configured to
accept a plurality of voltage signals; and an output node
configured to couple to a gate of said voltage-pulling transistor;
wherein said selective coupling apparatus has a first mode of
operation and is configured to receive a signal that has a first
value during said first mode of operation, and wherein said
selective coupling apparatus is further configured to allow
electrical communication between said test conduit and said output
node in response to said first value.
10. The circuit in claim 9, further comprising a main conduit
coupled to said selective coupling apparatus and configured to
receive a voltage source, and wherein: said selective coupling
apparatus has a second mode of operation; said signal has a second
value during said second mode of operation; and said selective
coupling apparatus is configured to allow electrical communication
between said main conduit and said output node in response to said
second value.
11. The circuit in claim 10, wherein said selective coupling
apparatus is configured to prevent electrical communication between
said test conduit and said output node in response to said second
value.
12. The circuit in claim 11, wherein said selective coupling
apparatus is configured to prevent electrical communication between
said main conduit and said output node in response to said first
value.
13. The circuit in claim 12, wherein said second value is inverse
to said first value.
14. A voltage regulator for a voltage-pulling transistor of a sense
amp, wherein said voltage-pulling transistor is driven by an
inverter circuit having a p-channel transistor and an n-channel
transistor, comprising: a common node configured to couple to said
inverter circuit; a first electrical connection device electrically
interposed between said common node and a first pathway, wherein:
said first pathway is configured to accept a first voltage, and
said first electrical connection device is configured to accept a
first vector and to electrically connect said first pathway with
said common node in response to said first vector; and a second
electrical connection device electrically interposed between said
common node and a second pathway, wherein: said second pathway is
configured to accept a second voltage, and said second electrical
connection device is configured to accept a second vector and
electrically connect said second pathway with said common node in
response to said second vector.
15. The voltage regulator in claim 14, wherein said voltage
regulator is configured to accept one of said first and second
vectors at a time.
16. The voltage regulator of claim 15, wherein said voltage
regulator is a package part of an integrated circuit.
17. The voltage regulator in claim 16, wherein said common node is
coupled to said p-channel transistor.
18. The voltage regulator of claim 15, further comprising a latch
device connected to said second electrical connection device,
wherein: said latch device is configured to receive a test vector;
and said latch device is further configured to transmit said second
vector to said second electrical connection device in response to
said test vector.
19. The voltage regulator of claim 18, wherein said latch device
further comprises: an inverter connected to said second electrical
connection device, wherein: said inverter is configured to receive
said test vector, and said inverter is further configured to
transmit said second vector to said second electrical connection
device in response to said test vector; and an activated transistor
electrically interposed between said second electrical connection
device and said inverter.
20. The voltage regulator of claim 19, further comprising a
replenish device coupled to said second electrical connection
device and to said common node, wherein said replenish device is
configured to substantially maintain a potential at said second
electrical connection device.
21. The voltage regulator of claim 20, wherein said replenish
device is a capacitor;
22. The voltage regulator of claim 21, wherein: said replenish
device comprises a second n-channel transistor having a gate, a
drain and a source; said drain and said source are coupled together
at a capacitance node; said capacitance node is coupled to said
common node; and said gate is coupled to said second electrical
connection device.
23. A margin-range apparatus for a sense amp's voltage-pulling
transistor driven by an inverter circuit having a p-channel
transistor coupled to an n-channel transistor, comprising: a
voltage reception device, wherein: said voltage reception device is
configured to couple to said inverter circuit, and said voltage
reception device is selectively coupled to a first test voltage
path and a second test voltage path.
24. The apparatus in claim 23, wherein said voltage reception
device is selectively coupled to a ground path.
25. The apparatus in claim 24, wherein said voltage reception
device is coupled to said n-channel transistor.
26. A current saturation test device for a sense amp having a
pullup transistor gated by an inverter comprising a p-channel
transistor and an n-channel transistor, wherein said device
comprises: a first terminal configured to couple to said inverter
and adapted to receive a generally constant potential; and a second
terminal configured to couple to said inverter and adapted to
receive a plurality of voltage potentials.
27. The device in claim 26, wherein said second terminal is coupled
to: a first test path adapted to receive a first test voltage; a
second test path adapted to receive a second test voltage; and a
non-test path coupled to a potential node.
28. The device in claim 27, further comprising: a first selection
device coupled to said first test path and electrically interposed
between said second terminal and said first test voltage, wherein
said first selection device is configured to activate in response
to a first test signal; a second selection device coupled to said
second test path and electrically interposed between said second
terminal and said second test voltage, wherein said second
selection device is configured to activate in response to a second
test signal; and a third selection device coupled to said non-test
path, electrically interposed between said second terminal and said
potential node, and configured to activate in response to a
non-test signal.
29. The device in claim 28, further comprising a logic unit having
said first test signal as a first input, said second test signal as
a second input, and having a non-test signal output coupled to said
third selection device.
30. The device in claim 29, where said device is configured to
avoid simultaneous activation of said first selection device and
said second selection device.
31. The device in claim 30, wherein: said first terminal is coupled
to said p-channel transistor; said second terminal is coupled to
said n-channel transistor; said potential node of said non-test
path is configured to couple to ground; and said logic unit is a
NOR gate.
32. The device in claim 30, wherein: said first terminal is coupled
to said n-channel transistor; said second terminal is coupled to
said p-channel transistor; said potential node of said non-test
path is configured to couple to a non-test voltage source; and said
logic unit is a NAND gate.
33. A driver circuit for a voltage-pulling device comprising: a
first plurality of potential nodes; a signaling circuit configured
to couple to said voltage-pulling device and selectively
communicative with one of said first plurality of potential nodes;
and a second plurality of potential nodes selectively communicative
with said signaling circuit.
34. The driver circuit in claim 33, wherein: said signaling circuit
comprises an inverter having a p-channel transistor coupled to an
n-channel transistor; said p-channel transistor is selectively
coupled to said first plurality of potential nodes; and said second
plurality of potential nodes is selectively coupled to said
n-channel transistor.
35. A test circuit for a sense amp, comprising: a driver circuit;
and a coupler circuit connected to said driver circuit and
configured to selectively receive a first voltage source and a
second voltage source, wherein said first voltage source is
electrically discrete from said second voltage source.
36. A method for testing a semiconductor memory device having at
least one sense amp, comprising: writing original data to said
memory device; driving said sense amp with a first voltage; reading
a first sample of stored data from said memory device; driving said
sense amp with a different voltage; reading an additional sample of
stored data from said memory device; and comparing said first
sample of stored data and said additional sample of stored data
with said original data.
37. A method for determining the range of margins that a
voltage-pulling sense amp transistor of a memory array is capable
of accommodating, comprising: entering an input test pattern into
said memory array; reading at least two output test patterns using
at least two voltage levels driving said voltage-pulling sense amp
transistor; and comparing said input test pattern with said output
test patterns.
38. A method for determining a lowest reliable level of a supply
voltage capable of driving a sense amp in a memory array,
comprising: writing initial test data to said memory array;
initiating a test mode; taking a plurality of test readings from
said memory array; decreasing said supply voltage driving said
sense amp for each of said plurality of test readings; and
repeating taking test readings and decreasing said supply
voltage.
39. The method in claim 38, wherein said repeating further
comprises repeating taking test readings and decreasing said supply
voltage until current saturation occurs.
40. The method in claim 39, wherein initiating a test mode
comprises providing electrical communication between a test pathway
and said sense amp.
41. The method in claim 40, wherein initiating a test mode further
comprises preventing electrical communication between a non-test
operation pathway and said sense amp.
42. The method in claim 41, wherein decreasing said supply voltage
comprises decreasing said supply voltage through a range of
voltages.
43. A method for determining a highest reliable level of a supply
voltage that can drive a sense amp in a memory array, comprising:
writing initial test data to said memory array; taking a plurality
of test readings from said memory array; increasing said supply
voltage driving said sense amp for each of said plurality of test
readings; and repeating taking test readings and increasing said
supply voltage until capacitive coupling occurs.
44. The method in claim 43, wherein increasing said supply voltage
comprises increasing said supply voltage through a series of
discrete values.
45. A method of test driving a sense amp voltage puller for at
least one memory cell, comprising: entering an input value to said
memory cell; providing a plurality of driving pathways to said
sense amp voltage puller; configuring each driving pathway of said
plurality of driving pathways to accept at least a respective
plurality of voltage sources; associating said plurality of driving
pathways with a plurality of test vectors; transmitting a test
vector corresponding to one driving pathway of said plurality of
driving pathways; enabling electrical communication between said
sense amp voltage puller and said driving pathway corresponding to
said test vector; reading a first sample of output data;
transmitting a different test vector corresponding to a different
driving pathway; enabling electrical communication between said
sense amp voltage puller and said different driving pathway; and
reading a second sample of output data.
46. The method in claim 45, wherein enabling electrical
communication comprises enabling electrical communication through
one of said driving pathways at a time.
47. A method of determining the margin that a voltage-pulling
transistor of a memory array is capable of accommodating,
comprising: entering an input data pattern to said memory array;
repeatedly reading an output data pattern from said memory array;
changing a voltage level driving said voltage-pulling transistor
for each reading; and tracking any differences between said output
data pattern and said input data pattern.
48. A method for determining operable drive levels for a pulldown
sense amp accommodating an operations circuit, wherein said
pulldown sense amp has a first portion at a first voltage level and
a second portion at a second voltage level, comprising: setting an
initial drive level for said pulldown sense amp; pulling down said
first voltage level for a first time; establishing a new drive
level for said pulldown sense amp; pulling down said first voltage
level for a second time; and selectively comparing one time span
required to pull down said first voltage level with a time span for
accessing one of said first and second portions by said operations
circuit.
49. The method in claim 48, further comprising equilibrating said
first voltage level and said second voltage level before each
pulling.
50. A method for determining the capabilities of a pullup
transistor serving external circuitry, wherein said pullup
transistor is coupled to at least one sense amp, comprising:
initiating a test drive voltage for said pullup transistor; pulling
up a digit-line voltage of a component of said sense amp associated
with said pullup transistor; comparing a length of time needed to
pull up said digit-line voltage with a length of time required to
drive said external circuitry; altering said test drive voltage;
and repeating said pulling and comparing.
51. The method in claim 50, further comprising altering said test
drive voltage before every repetition of said pulling.
52. The method in claim 51 further comprising establishing a
non-test drive voltage within a range capable of pulling up said
digit-line voltage within said length of time required to drive
said external circuitry.
53. The method in claim 52, wherein said non-test drive voltage is
generally constant.
54. A method of changing the capability of a sense amp driver
during a test mode, comprising: providing a first potential node
for said sense amp driver, wherein said first potential node is at
a first voltage; providing a second potential node for said sense
amp driver, wherein said second potential node is at a second
voltage; and changing said first voltage of said first potential
node.
55. The method in claim 54, further comprising changing said second
voltage of said second potential node.
56. A method of regulating a control device within a semiconductor
device, comprising: driving said control device with a first
voltage; performing a first operation on said semiconductor device;
driving said control device with a second voltage; and performing a
second operation on said semiconductor device.
57. A method of testing a memory device, comprising: performing a
plurality of readings on said memory device; and initiating a
voltage change within said memory device between each reading of
said plurality of readings.
58. A voltage regulator for a semiconductor device, comprising: a
terminal configured to receive a first voltage potential and a
second voltage potential; an access transistor coupled to said
terminal and configured to activate in response to receiving a test
mode signal; and a connection node coupled to said access
transistor and configured to couple to said semiconductor
device.
59. The voltage regulator in claim 58, wherein: said semiconductor
device is configured to operate based on a source voltage V.sub.CC
signal; said access transistor has a gate; said test mode signal
has a potential generally equal to said V.sub.CC signal having
undergone a charge pumping process, and wherein said test mode
signal is configured to drive said gate of said access transistor;
and said voltage regulator further comprises a bootstrap device
coupled to said gate of said access transistor and to said
connection node, wherein said bootstrap device is configured to
prevent said gate of said access transistor from substantially
discharging during a transmission of said test mode signal.
60. The voltage regulator in claim 59, wherein: said semiconductor
device includes a cell plate; and said access transistor is
configured to couple to said cell plate.
61. The voltage regulator in claim 60, wherein: said semiconductor
device includes a digit line; and said access transistor is
configured to couple to said digit line.
62. A voltage variance test circuit for a semiconductor device
having a connection node, comprising: a first terminal configured
to receive a first voltage potential and coupled to a first
exclusively operable access device, wherein said first exclusively
operable access device is coupled to said connection node; and a
second terminal configured to receive a second voltage potential
and coupled to a second exclusively operable access device, wherein
said second exclusively operable access device is coupled to said
connection node.
63. The voltage variance test circuit in claim 62, wherein: said
first exclusively operable access device comprises a first
transistor configured to activate in response to a reception of a
first test signal; said second exclusively operable access device
comprises a second transistor configured to activate in response to
a reception of a second test signal; and at most one of said first
test signal and said second test signal are received at any
time.
64. The voltage variance test circuit in claim 63, wherein said
semiconductor device has a voltage pulling sense amp transistor,
and said connection node is coupled to said voltage pulling sense
amp transistor.
65. A regulator for an equilibration circuit, comprising: a first
potential node configured to receive a first voltage source; a
second potential node configured to receive a second voltage
source; a common node selectively coupled to said first potential
node and to said second potential node; and an output node coupled
to said common node and configured to couple to said equilibration
circuit.
66. The regulator in claim 65, wherein said equilibration circuit
has a test mode and a non-test mode, and wherein: said common node
is coupled to said first potential node during said non-test mode;
and said common node is selectively coupled to said first potential
node and to said second potential node during said test mode.
67. A test driver for a bleeder device joining a cell plate signal
generator to a memory array, comprising: a plurality of conductive
paths configured to receive a plurality of voltage sources; a
plurality of communication devices respectively coupled to said
plurality of conductive paths, wherein each communication device of
said plurality of communication devices is configured to activate
to the exclusion of all other communication devices of said
plurality of communication devices; and an output terminal coupled
to said plurality of communication devices and configured to couple
to said bleeder device.
68. A charge rate regulator for a cell plate generator coupled to a
digit line pair of a memory array, comprising: a main transmission
device electrically interposed between said cell plate generator
and said digit line pair; and a drive device coupled to said main
transmission device and configured to selectively receive a
plurality of voltage sources.
69. The charge rate regulator in claim 68, wherein said drive
device further comprises: a plurality of secondary transmission
devices, wherein each secondary transmission device of said
plurality of secondary transmission devices has a first end and a
second end, wherein: said first end of each secondary transmission
device is coupled to said main transmission device, and said second
end of each secondary transmission device is configured to receive
a respective voltage source from said plurality of voltage sources;
and a selective communication circuit coupled to said plurality of
secondary transmission devices and electrically interposed between
said plurality of secondary transmission devices and said plurality
of voltage sources.
70. The charge rate regulator in claim 69, wherein said selective
communication circuit is configured to activate one secondary
transmission device of said plurality of secondary transmission
devices at a time.
71. A test mode driver circuit for a regulator device of a cell
plate signal, comprising: a conductive path coupled to said
regulator device; and a voltage range receiver coupled to said
conductive path.
72. The test mode driver circuit in claim 71, wherein said voltage
range receiver is a contact pad.
73. A voltage regulator for a memory circuit including an
equilibration device, a digit line pair, and a memory cell,
comprising: a voltage reception device, wherein: said voltage
reception device is configured to couple to said memory circuit;
and said voltage reception device is selectively electrically
communicative with a first test voltage path and a second test
voltage path.
74. The voltage regulator in claim 73, wherein said voltage
reception device is configured to electrically interpose between
said equilibration device and said digit line pair.
75. A defect testing device for a memory array having a cell plate
signal device, comprising: a first terminal configured to couple to
said cell plate signal device and configured to receive a voltage
potential; and a second terminal configured to couple to said cell
plate signal device and configured to receive a plurality of
voltage potentials.
76. The device in claim 75, wherein said second terminal is coupled
to: a first test path configured to receive a first test voltage;
and a second test path configured to receive a second test
voltage.
77. The device in claim 76, further comprising: a first isolation
device electrically interposed between said first test path and
said second terminal, wherein said first isolation device has an
active mode and an inactive mode; and a second isolation device
electrically interposed between said second test path and said
second terminal, wherein: said second isolation device has an
active mode complementary to said active mode of said first
isolation device, and said second isolation device has an inactive
mode complementary to said inactive mode of said first isolation
device.
78. The device in claim 77, further comprising a third isolation
device electrically interposed between said first terminal and said
cell plate signal device, wherein all but one of said first,
second, and third isolation devices are configured to operate
simultaneously.
79. A voltage regulator for a cell plate signal of a memory array,
wherein said cell plate signal is transmitted through a conductive
path, and a control device is coupled to said conductive path,
comprising: a first voltage node having a generally constant
potential; a first latching device coupled to said first voltage
node and to said control device; a second voltage node having a
variable potential; and a second latching device coupled to said
second voltage node and configured to couple to said control
device, wherein said first latching device and said second latching
device are selectively operable.
80. The voltage regulator in claim 79, wherein said second voltage
node is coupled to a contact pad.
81. The voltage regulator in claim 80, wherein said first latching
device comprises a transistor.
82. The voltage regulator in claim 81, wherein said second latching
device comprises: a test signal path coupled to said control
device; a switching device coupled to said test signal path and to
said second voltage node and configured to allow electrical
communication between said second voltage node and said test signal
path in response to a reception of a driving signal; a driving
device coupled to said switching device and configured to receive a
test signal and transmit said driving signal in response to a
reception of said test signal; and a driving signal maintenance
device coupled to said switching device and to said test signal
path.
83. The voltage regulator in claim 82, wherein said driving device
further comprises: a test initiator configured to receive said test
signal and transmit said driving signal in response to a reception
of said test signal; and an output device coupled to said test
initiator and said switching device, wherein said output device is
configured to receive and output said driving signal.
84. The voltage regulator in claim 83, wherein: said memory array
is configured to accommodate an external circuit operating on a
source voltage V.sub.CC; and said test initiator and said output
device are driven by a voltage V.sub.CCP, wherein said voltage
V.sub.CCP is greater than said source voltage V.sub.CC.
85. The voltage regulator in claim 84, wherein: said control device
is a transistor; said switching device is a transistor; said
driving signal maintenance device is a capacitor; said test
initiator is an inverter; and said output device is a
transistor.
86. An equilibration regulator coupled to a semiconductor device
having a cell plate generator circuit and a digit line pair,
comprising: a selective voltage circuit coupled to said cell plate
generator circuit and said digit line pair, wherein said selective
voltage circuit is configured to receive a plurality of driving
voltages, and wherein: a selection of at least one driving voltage
from said plurality of driving voltages is a test voltage; one of
said plurality of driving voltages is a defect compensation
voltage; and said defect compensation voltage is a non-test
voltage.
87. The equilibration regulator of claim 86, wherein said
semiconductor device is generally driven by a voltage V.sub.CC, and
wherein: said defect compensation voltage has a potential greater
than V.sub.CC and is configured to counteract a defect in said
semiconductor device.
88. The equilibration regulator of claim 87, wherein: said digit
line pair comprises: a first digit line having a voltage potential,
a second digit line having a complementary voltage potential; said
digit line pair has a configured equilibrate voltage generally
between said voltage potential and said complementary voltage
potential; said defect has a biasing effect on said first digit
line, wherein said digit line pair approaches a deviant equilibrate
voltage in response to said biasing effect of said defect; and said
defect compensation voltage has a counter-bias effect on said digit
line pair, wherein said digit line pair approaches said configured
equilibrate voltage in response to said counter-bias effect.
89. The equilibration regulator of claim 88, wherein: said test
voltage has a potential greater than V.sub.CC and less than said
potential of said defect compensation voltage; and said test
voltage has an alternate counter-bias effect on said digit line
pair, wherein said alternate counter-bias effect is less than said
counter-bias effect of said defect compensation voltage.
90. The equilibration regulator of claim 89, wherein said defect
compensation voltage is another test voltage.
91. The equilibration regulator of claim 90, wherein said defect is
a conductive path coupling said cell plate generator circuit to
said digit line pair.
92. A method of testing a memory array storing a test data pattern,
comprising: allowing a defect to hinder an ability to accurately
read said test data pattern; and preventing said memory array from
restoring said ability to accurately read said test data pattern;
reading said test data pattern; and checking said test data pattern
for changes.
93. The method in claim 92, wherein preventing further comprises
preventing said memory array from fully restoring said ability to
accurately read said test data pattern.
94. The method in claim 93, further comprising: changing said test
data pattern; writing said test data pattern to said memory array;
and repeating said allowing, preventing, reading, and checking.
95. A method of detecting any short from a digit line pair to
ground, comprising: initiating an equilibration charge of said
digit line pair at a charge rate; allowing any short to discharge
said digit line pair toward ground at a discharge rate; and
decreasing said charge rate.
96. The method in claim 95 further comprising: writing an input
data bit to a cell corresponding to said digit line pair; reading
an output data bit from said cell; and comparing said input data
bit with said output data bit.
97. The method in claim 96, wherein: writing is performed before
initiating; and reading is performed after decreasing.
98. The method in claim 97, wherein writing further comprises
writing a logic 0 to said cell.
99. The method in claim 98 wherein: initiating further comprises
providing electrical communication between a cell plate generator
and said digit line pair; and decreasing further comprises:
regulating said electrical communication using a control device,
and decreasing a driving signal of said control device.
100. A method of detecting a short from a digit line to a cell
plate, comprising: charging said digit line to a first potential,
wherein said first potential represents a logic value; charging a
complementary digit line to a second potential representing a
complementary logic value; allowing said short to urge said digit
line to a third potential; providing electrical communication
between said digit line and said complementary digit line; allowing
said digit line and said complementary digit line to establish an
initial common voltage generally between said second potential and
said third potential; equilibrating said digit line and said
complementary digit line toward a final common voltage generally
between said first potential and said second potential, wherein
said equilibrating occurs at an equilibration rate; and limiting
said equilibration rate.
101. The method in claim 100, wherein charging a digit line further
comprises writing said logic value to a cell.
102. The method in claim 101, further comprising receiving a first
signal, and wherein allowing said short to urge said digit line to
a third potential is performed in response to receiving said first
signal.
103. The method in claim 102, further comprising receiving a second
signal, and wherein providing electrical communication is performed
in response to receiving said second signal.
104. The method in claim 103, wherein: said first signal has a
first voltage level; said second signal has a second voltage level;
and said second voltage level is higher than said first voltage
level.
105. The method in claim 104, wherein: said first signal has a test
duration and a non-test duration; and said test duration is longer
than said non-test duration.
106. The method in claim 105, wherein said first signal and said
second signal are RAS signals.
107. A method of preparing to test a storage capacitor of a memory
cell, wherein said memory cell also includes an access transistor
and a potential node providing an initial DVC.sub.2 voltage signal
to said storage capacitor, and wherein said method comprises:
turning off said access transistor; providing a forced voltage
signal to said storage capacitor, wherein said forced voltage
signal has a potential greater than a potential of said initial
DVC.sub.2 voltage signal; and preventing said forced voltage signal
from substantially affecting any digit line associated with said
memory cell.
108. The method in claim 107, wherein providing a forced voltage
signal further comprises providing said forced voltage signal
through said potential node.
109. The method in claim 108, further comprising: providing a main
digit line for said memory cell; providing a complementary digit
line for said main digit line; and equilibrating said main digit
line and said complementary digit line to an equilibration
potential generally equal to said potential of said initial
DVC.sub.2 voltage signal.
110. The method in claim 109, wherein said preventing further
comprises restricting electrical communication of said forced
voltage signal to said main digit line and said complementary digit
line.
111. A method of detecting a leak within a storage capacitor of a
memory cell affiliated with a digit line, wherein a cell plate
generator is coupled to said storage capacitor and to said digit
line, and said cell plate generator is further configured to
generate a voltage, comprising: charging said storage capacitor
with an input potential corresponding to a logic 0 value;
initiating a static refresh pause; increasing said voltage
generated by said cell plate generator; limiting electrical
communication between said cell plate generator and said digit
line; discharging an output potential of said storage capacitor to
said digit line; and comparing said input potential with said
output potential.
112. The method in claim 111, wherein initiating a static refresh
pause further comprises preventing electrical communication between
said digit line and said storage capacitor.
113. The method in claim 112, wherein initiating a static refresh
pause further comprises allowing electrical communication between
said digit line and said cell plate generator.
114. The method in claim 113, further comprising allowing said leak
to change said input potential to said output potential, wherein
said allowing occurs during said static refresh pause.
115. The method in claim 114, further comprising ending said static
refresh pause before discharging.
116. A method of altering a margin between a potential of a charge
stored in a memory cell and a common potential of a digit line
pair, wherein said memory cell and said digit line pair are
configured to receive an equilibrate signal, comprising: allowing a
defect to change said common potential of said digit line pair; and
substantially isolating said digit line pair from said equilibrate
signal.
117. The method in claim 116, wherein said defect is a short from
said digit line pair to ground.
118. A method of altering a margin between a potential of a charge
stored in a memory cell and a potential of a shorted digit line
pair, wherein said digit line pair is configured to receive an
equilibrate signal, and wherein said digit line pair comprises a
first digit line having a first initial potential and a second
digit line having a second initial potential, comprising: allowing
a defect to change said first initial potential of said first digit
line; shorting said first digit line to said second digit line; and
substantially isolating said digit line pair from said equilibrate
signal.
119. The method in claim 118, wherein: said defect is a short
between an equilibrate signal node and said first digit line; and
said equilibrate signal node is configured to transmit said
equilibrate signal.
120. A method of altering a margin between a potential of a charge
stored in a memory cell and a potential of a digit line, wherein
said memory cell and said digit line are configured to receive an
equilibrate signal having a voltage, comprising: changing said
voltage of said equilibrate signal; allowing said potential of said
charge in said memory cell to change due to a defect and said
equilibrate signal; and substantially isolating said digit line
from said equilibrate signal.
121. The method in claim 120, wherein said defect is a short within
a storage capacitor of said memory cell.
122. The method in claim 121, wherein said defect is a defect of a
dielectric layer between two cell plates of said storage
capacitor.
123. The method in claim 122, wherein said defect is a nitride
defect.
124. A method of generally identifying a defect within a memory
circuit, wherein said memory circuit is connected to a cell plate,
comprising: writing an input bit to said memory circuit; subjecting
said memory circuit to at least one test stage; associating said
defect with said test stage; associating an isolation of said cell
plate with said test stage; initiating said isolation of said cell
plate in relation to said test stage; reading an output bit from
said memory circuit; and comparing said input bit with said output
bit.
125. The method in claim 124, wherein: said test stage comprises a
precharge cycle; and initiating further comprises initiating said
isolation of said cell plate during said precharge cycle.
126. The method in claim 124, wherein: said test stage comprises a
long RAS low period; and initiating further comprises initiating
said isolation of said cell plate after said long RAS low
period.
127. The method in claim 124, wherein: said test stage comprises a
static refresh pause; and initiating further comprises initiating
said isolation of said cell plate during said static refresh
pause.
128. A method of altering the drive of a cell plate to digit line
bleeder device, comprising: entering a test mode; providing a
plurality of drive voltage sources for said bleeder device; and
applying said plurality of drive voltage sources to said bleeder
device.
129. The method in claim 128, wherein said providing further
comprises providing a plurality of discrete drive voltage sources
for said bleeder device.
130. The method in claim 128, wherein said providing further
comprises providing a range of drive voltage sources for said
bleeder device.
131. A method of stressing a memory device having a digit line
configured to selectively charge to a high potential a mid-level
potential, and a low potential, comprising: allowing a defect to
alter said mid-level potential; and slowing a restoration of said
mid-level potential.
132. A method of testing a memory cell having an equilibrate
voltage, a logic voltage corresponding to a logic value, and a
margin representing the difference between said equilibrate voltage
and said logic voltage, comprising: enabling any defect of said
memory cell to alter said margin; and reading data from said memory
cell.
133. The method in claim 132, further comprising exacerbating any
margin alteration from said defect.
134. A method of compensating for a defect within a semiconductor
device having a digit line configured to receive a cell plate
signal from a signal node, comprising: providing a signal regulator
between said signal node and said digit line; applying a
defect-countering driving voltage to said signal regulator.
135. The method in claim 134, wherein: said defect comprises an
unregulated electrical communication of said cell plate signal to
said digit line; and said defect-countering driving voltage is
higher than a generally standard driving voltage for said signal
regulator.
136. The method in claim 135, further comprising: testing for said
defect, wherein said testing further comprises: providing said
signal regulator with a plurality of driving voltages; and
selectively applying said plurality of driving voltages.
137. The method in claim 136, wherein said applying further
comprises applying said defect-countering driving voltage in
response to finding said defect.
138. The method in claim 137, wherein: said method further
comprises initiating a non-test mode after testing for said defect;
and said applying further comprises applying said defect-countering
driving voltage during said non-test mode.
Description
TECHNICAL FIELD
[0001] The present invention relates generally to semiconductor
circuit devices and, more specifically, to a circuit for changing
the voltage applied to selective portions of a memory array. Such
portions include digit line pairs as well as the gate of a
transistor used to regulate sense amplifiers.
BACKGROUND OF THE INVENTION
[0002] In the operation of certain semiconductor circuit devices,
pullup and pulldown sense amplifiers (sense amps) detect and
amplify a small charge stored within a memory cell. In general, two
complementary digit lines are attached to a pullup sense amp and a
pull down sense amp. At the beginning of a reading operation, both
lines are at an equilibrate voltage Veq, which is generally between
the potential of a voltage source used to operate the semiconductor
device (V.sub.CC) and ground potential (0 volts). While Veq is
changeable either intentionally or inadvertently through a defect,
Veq is ideally equal to V.sub.CC/2 during non-test operations. This
midpoint voltage is defined as DVC.sub.2.
[0003] One of the digit lines is coupled to a memory cell. The
reading process involves a discharge from the memory cell to the
corresponding digit line, which creates a slight difference in
voltage between the two digit lines. This difference is then
amplified by the sense amps: the digit line with the slightly lower
voltage has its voltage further decreased by the pulldown sense
amp, and the voltage of the other digit line is increased by the
pullup sense amp. Once the voltage difference has been amplified,
the digit lines can then be used to operate less sensitive
circuitry.
[0004] Between reading cycles, it is necessary to return the
complementary digit lines to Veq. This occurs during what is known
as a precharge cycle, wherein equilibration transistors short the
complementary digit lines together. Further, a signal having a
potential of DVC.sub.2 is communicated from a DVC.sub.2 voltage
generator to the shorted digit lines through a bleeder device.
[0005] Concerning the operation of the sense amps, it should be
noted that pulling down the voltage of a digit line involves
coupling the line to ground through a pulldown transistor. Because
an entire row of digit line pairs often connects to the same
pulldown transistor through a common node, the pulldown transistor
will most likely have to draw current from one line of each of
several pairs. In doing so, there is a risk that the transistor
will become saturated with current and therefore become slower in
pulling down the voltage of additional digit lines. This may lead
to errors in reading, especially if an entire row of memory cells
is storing logic 1's except for one cell storing a logic 0; for
once the logic 0 is discharged, a slow pulldown may result in an
improper reading of that logic 0 value.
[0006] One known way to solve this problem is to include an
optional active area in the gate of the pulldown transistor. The
increased size of the gate raises the threshold at which the
pulldown transistor becomes saturated. However, one of ordinary
skill in the art will appreciate that this solution requires a
costly metal mask change. Further, any attempt to speed up the
slowed pulldown raises other problems in reading, as disclosed in
U.S. Pat. No. 5,042,011, by Casper, et al. The Casper '011
reference discloses that pulling down the common node too quickly
may result in capacitive coupling between the sources and drains of
the sense amp's transistors. During capacitive coupling, both digit
lines in one sense amp are pulled down before the common node is
pulled down low enough to turn on one of the sense amp transistors.
When the sense amp finally turns on, it shorts out the capacitive
coupling, bouncing the digit lines and, in the process, creates
line noise that will interfere with the ability to read the data
properly.
[0007] Early saturation and capacitive coupling could be avoided if
one knew the margin-- the difference in voltage between a logic 0
signal and a logic 1 signal--that the pulldown transistor was
capable of accommodating. The only way to do so, as taught by the
prior art, is to separate the pulldown transistor with a laser and
probe the gate.
[0008] As an alternative to determining the sense amp's margin, one
could simply test the sense amp's ability to operate at the given
source voltage used in non-test operations. Prior art suggests
entering a series of test data patterns into memory. Logic 1's are
written to the cells of each memory array, with the exception of
one column of logic 0's. As a result, each row contains only one
cell storing a logic 0, thereby creating the most likely
circumstance for an error in reading the data. The data in the
array is then read and checked for errors. Once the first group of
test data has been processed, a second sample of test data is
entered with the logic 0's written to the next column. This process
repeats until a logic 0 has been written to and read from every
cell in any given row in the memory array. The results will
indicate the pulldown transistor's ability to read data accurately.
The problem with this process, however, is that it is time
consuming to enter multiple samples of test data.
[0009] Thus, there is a need in the art for a quicker circuit and
method for testing the capabilities of a sense amp. Further benefit
would be derived if this test could indicate the margin of the
sense amp's pulldown transistor.
[0010] In addition to inadequate pulldown transistors, other
problems, such as defects arising during the processing of
semiconductor devices, may contribute to reading errors. Various
techniques involving equilibration of the complementary digit lines
can be used during testing to detect these problems. For example,
occasionally a digit line will inadvertently have a short to
ground. As a result, the potential of that digit line will leak
towards 0 volts. To detect this problem, prior art teaches
extending the time for the precharge cycle during a test mode. If
the short has a low enough resistance, the short will overcome the
charging ability of the DVC.sub.2 voltage generator, which remains
coupled to the digit lines, and Veq of the digit lines will
decrease. Thus, a longer precharge cycle allows Veq to lower even
further. As a result, line noise is more likely to register as a
logic 0 discharge on the digit line when in fact the storage cell
contains a logic 1 and has not yet discharged. Alternatively,
assuming that a logic 1 is properly discharged and sensed, a
reading error is still likely: Veq may be so low due to the short
that the pullup sense amp may not be able to pull up the digit
line's voltage in time to register as a logic 1 for purposes of
driving external circuitry. Increasing the likelihood of error is
desirable in the test mode, as it helps to identify errors that
would affect non-test operations. Further, a reading error
occurring after this extended precharge cycle will indicate the
nature of the defect--in this case a short in at least one of the
digit lines. However, this testing process can be time consuming.
As an example, a 64 meg DRAM having a 16 meg.times.4 configuration
requires approximately 170 seconds to carry out this test. It would
be a benefit to the art to have a faster way to test for this
problem.
[0011] A second problem that could be detected by altering the
equilibration rate of the digit lines involves a short between the
cell plate and the digit line. The typical technique for
discovering this problem is to initiate a long RAS (Row Address
Strobe) low signal. During the low RAS, the digit lines are not
equilibrated. Rather, they are charged to their complementary
voltage levels. Ideally, once the low RAS ends and the lines are
shorted, both digit lines should approach a Veq level of DVC.sub.2.
However, a short between one of the digit lines and the cell plate
will allow the DVC.sub.2 generator 68 to change that digit line's
voltage during the RAS low period. Thus, once the lines are
shorted, their respective voltages will meet at a different Veq
level. This will affect the margin between Veq and the voltage
corresponding to one of the logic values and thereby increase the
likelihood of a reading error. Eventually, the signal from the
DVC.sub.2 voltage generator will restore the proper equilibrate
voltage once the RAS low signal ends.
[0012] Nevertheless, for purposes of detecting this problem before
non-test operations begin, it would be desirable to slow the
restoration of the proper Veq level.
[0013] A third example concerns a defect that could exist within
the memory cell's storage capacitor, such as a defect in a nitride
layer acting as a dielectric between the memory cell's conductive
plates. Such a defect could cause a short within the storage
capacitor. Because the storage capacitors are coupled to the
DVC.sub.2 voltage generator, a defective capacitor "storing" a 0
volt charge, representing a logic 0, will slowly charge to the
DVC.sub.2 level. The closer the storage capacitor approaches a
DVC.sub.2 charge, the more likely that a logic 1 value may be
misread during the next reading. One way to detect this problem in
the prior art is to initiate a static refresh pause, wherein the
memory cell's access transistor remains deactivated for a longer
time than usual--generally 100 milliseconds. As a result, the
capacitor, which should be storing a logic 0, has a longer time to
charge to a higher voltage, thereby making an error in the next
reading cycle more likely.
[0014] Once again, a speedier test is desired. The defect might be
detected earlier if the problem were exacerbated to the point where
the leaked charge for the stored logic 0 exceeded the equilibrate
charge of the digit lines. As a result, a logic 1 would be read
from the cell even though it was known that a logic 0 had been
written. One could speed up the leakage into the storage capacitor
by forcing DVC.sub.2 to a higher voltage. However, the equilibrate
voltage of the digit lines would also increase accordingly and
remain higher than the voltage of the charge in the storage
capacitor. Thus, forcing DVC.sub.2 would not appreciably increase
the ability to detect an error unless the equilibration of the
digit lines could be slowed. The only way to do this in the prior
art is through the use of a costly metal option to change the gate
voltage of the bleeder device.
SUMMARY OF THE INVENTION
[0015] Given the need for regulating the drive of a sense amp, as
well as the need for regulating the equilibration signal from a
DVC.sub.2 voltage generator, a test circuit is provided for varying
the voltage of a signal used to drive a connection device that
allows electrical communication within a semiconductor circuit. One
preferred circuit embodiment includes a contact pad for carrying a
range of test voltage signals to said connection device. In another
preferred circuit embodiment, a regulator circuit enables a series
of discrete voltages to drive the connection device.
[0016] In one set of applications involving the regulation of a
sense amp, the connection device comprises a sense amp's voltage
pulling transistor. Any circuit embodiment covered by the present
invention can be used to test drive the transistor. In a preferred
method of use, a test data pattern is entered and the data is read
several times, with a different voltage driving the sense amp's
pulldown transistor each time. One advantage of this preferred
method is that it reduces the need for entering several elaborate
test data patterns and, therefore, allows for quicker testing of
memory arrays. A second advantage is that the embodied method and
devices allow a determination of the lowest supply voltage that can
be used during normal operation without errors in reading data. Yet
another advantage is the ability to determine the highest supply
voltage, and therefore the fastest reading speed, that can be used
during normal operations without causing capacitive coupling. In
doing so, the preferred circuit embodiments and method increase the
sense amp's ability to distinguish between a logic 0 voltage and a
logic 1 voltage without physically altering the sense amp. Further,
in the process of determining the lowest and highest voltages at
which the sense amp is capable of functioning, the preferred
embodiments and method also provide a way to ascertain the margin
without dissecting components of the sense amp.
[0017] Concerning the specific errors that may be detected in
relation to equilibrating the digit lines, the connection device
comprises an isolation bleeder device coupled between the DVC.sub.2
voltage generator and a digit line pair. The circuit embodiments
provide a test mode apparatus for driving the bleeder device in
order to slow or quicken the equilibration of the digit line pair.
Applying these embodiments provides the advantage of a quicker
detection of defects such as a short from a digit line to ground, a
short from a digit line to a cell plate, and a short within the
storage capacitor of a memory cell. The embodiments also provide an
alternative advantage of overcoming the influence of these defects
during non-test modes.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 depicts a row of n-channel pulldown sense amps with
associated D, D*, and WL lines; a pullup sense amp; and a series of
memory cells, as found in the prior art. FIG. 1 also shows a digit
line equilibration circuit as found in the prior art.
[0019] FIG. 2 is a graph indicating the voltage of the conductive
paths D and D* over time in the event that a memory cell storing a
logic 0 discharges to D. FIG. 2 also demonstrates the resulting
amplification of the difference in voltage.
[0020] FIG. 3 is a graph demonstrating the relationship between
drive current (I.sub.DV) and the gate-source voltage of a pulldown
transistor (V.sub.GS) at various levels of voltage applied to the
gate (V.sub.GATE).
[0021] FIG. 4 details one exemplary circuit embodiment in
accordance with the present invention as used with a sense amp.
[0022] FIG. 5 illustrates a second exemplary circuit embodiment in
accordance with the present invention as used with a sense amp.
[0023] FIG. 6 shows a third exemplary circuit embodiment in
accordance with the present invention as used with a sense amp.
[0024] FIG. 7a is a schematic of a portion of a memory array
depicting an embodiment of the current invention as used in the
digit line/cell plate region of a memory array. FIG. 7a further
depicts a first type of possible defect within said memory
array.
[0025] FIG. 7b is a graph illustrating the effect of the first
defect and a first embodied method of the current invention.
[0026] FIG. 7c is another graph illustrating the effect of the
first defect and the first embodied method of the current
invention.
[0027] FIG. 8a depicts a cross-section of a portion of a memory
array including a second type of defect.
[0028] FIG. 8b demonstrates the effect on a memory array of the
second type of defect as well as the effect of a second embodied
method of the current invention.
[0029] FIG. 8c further demonstrates the effect on a memory array of
the second type of defect as well as the effect of a third embodied
method of the current invention.
[0030] FIG. 8d depicts the effect of a fourth embodied method of
the current invention as it relates to the second type of
defect.
[0031] FIG. 9a is a schematic of a portion of a memory array
depicting a third type of defect in said memory array.
[0032] FIG. 9b is a graph indicating the effect of the third type
of defect.
[0033] FIG. 9c is a graph illustrating a method in the prior art
for detecting the third type of defect.
[0034] FIG. 9d is a graph illustrating the effect of a fifth
embodied method of the current invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0035] FIG. 1 illustrates the general configuration of sense amps
in a memory array. A pulldown sense amp 20 includes cross coupled
n-channel transistors Q1 and Q2, as well as a pulldown transistor
Q3, which is an n-channel transistor driven by a signal designated
as LENSA. These elements play a part in sensing and amplifying a
voltage difference between D and D* caused by shorting a memory
cell 22 to D by way of access transistor Q4. The sources of Q1 and
Q2 are connected to a common pulldown node 24, and the gate of each
is connected to the other's drain. The gate of Q1 also connects to
the line D*, whereas the gate of Q2 connects to the line D.
[0036] As discussed above, each line D and its corresponding line
D* are initially at the same voltage DVC.sub.2. For purposes of
explanation, DVC.sub.2 is assumed to be 1.65 volts, or one half of
the source voltage V.sub.CC, which is 3.3 volts. Lines D and D*
connect to opposite sides of each sense amp 20. Common pulldown
nodes 24 found in the sense amp arrays will also be at DVC.sub.2. A
signal sent through the path WL will cause a storage capacitor 150
of particular memory cell 22 to discharge to a line D, thereby
slightly changing D's voltage while the voltage of D* remains at
DVC.sub.2. Again, for purposes of explanation, a memory cell
discharge will be assumed to cause a 0.2 volt difference in D. The
pulldown sense amp 20 will then turn on when the common pulldown
node 24 is one transistor threshold voltage below D or D*,
whichever is highest. For instance, if a memory cell 22 is storing
a logic 1, a discharge to D will increase D's voltage to 1.85
volts. As a result, the pulldown sense amp transistor gated by D
(Q2) turns on faster than the one gated by D* (Q1). With transistor
Q2 on, D*'s voltage is pulled down from 1.65 volts towards ground
as the common pulldown node 24 is pulled down as well. Further, the
lowering voltage of D* serves to turn on the pullup sense amp
transistor gated by D* (Q14) before the other pullup sense amp
transistor turns on. The voltage supply V.sub.CC then charges line
D.
[0037] On the other hand, if the memory cell 22 had been storing a
logic 0, then a discharge to D would slightly lower D's voltage to
1.45 volts. The pulldown sense amp transistor gated by D* (Q1)
would turn on first and D's voltage would be further decreased
toward ground by the pulldown sense amp, thereby allowing the
pullup sense amp to increase D*'s voltage toward V.sub.CC. In this
way, a small voltage difference between D and D* is sensed and
amplified. Once the voltage difference has been amplified, D and D*
can drive less sensitive circuitry not shown in FIG. 1. It should
be noted that, if a logic 0 is transmitted to D, then the pulldown
sense amp need only pull down D from 1.45 volts. If a logic 1 is
transmitted to D, then the pulldown sense amp must pull D* from the
higher DVC.sub.2 level--1.65 volts.
[0038] Therefore, if many logic 1's in a memory array row are read,
the extra voltage that must be pulled contributes to saturating the
pulldown transistor Q3 with drive current, thereby slowing any
further pulldown. The problem created by slow pulldown is
illustrated in FIG. 2, where slope X denotes the initial discharge
to D from a memory cell 22 storing a logic 0. FIG. 2 further
illustrates the amplification of the difference in voltage between
D and D*. Slope Y denotes the time required for D to drop in
voltage given a situation where a row of cells contains a roughly
equal number of logic 1's and logic 0's. Should there be many logic
1's read amongst a single logic 0, then the outcome changes: as the
logic 0 is read, the pulldown transistor Q3, having approached
saturation, takes much longer to pull down D's voltage. This result
is illustrated by slope Z. Other circuitry elements (not shown)
that are driven by D may read D before its transition to a lower
voltage has been completed. As a result, a logic 0 value may be
misread as a logic 1.
[0039] As illustrated in FIG. 3, increasing the voltage to the gate
of the pulldown transistor allows the transistor to pulldown more
current before saturation. One preferred embodiment of the current
invention that uses this principal is detailed in FIG. 4, where the
pulldown transistor Q3 is driven by a test circuit 26 through an
inverter 27. In this embodiment, the inverter 27 comprises a
p-channel transistor Q6 and an n-channel transistor Q8. The coupled
gates of inverter transistors Q6 and Q8 form an input node 28 for
receiving a signal ENSA*, which may be V.sub.CC, ground, or a
signal from another driver. The coupled drains of the inverter
transistors Q6 and Q8 output the LENSA signal that drives the
pulldown transistor Q3. The source of Q8 is coupled to ground. The
source of Q6 is coupled to a source node 30 that branches into a
first conducting path 32 and a second conducting path 34. The first
conducting path 32 is coupled to an n-channel transistor Q10, which
has a channel width-to-length ratio of around 500/2. The drain of
transistor Q10 is coupled to a contact pad 36. It should be
understood that the term "contact pad" includes any conductive
surface configured to permit electrical communication with a
circuit or a node. The gate of transistor Q10 is coupled to an
inverter 60 through another n-channel transistor Q36. Together,
inverter 60 and transistor Q36 comprise a latch device, and both
are coupled to V.sub.CCP. Further, inverter 60 receives a TEST*
signal as an input. In addition, the gate of transistor Q10 is also
coupled to a feedback capacitor 62. This feedback capacitor 62
comprises an n-channel transistor having a size of approximately
100/100, wherein the drain and source are shorted and coupled to
the first conductive path 32. The second conducting path 34 is
coupled to a p-channel transistor Q12, driven by a signal TEST,
which is understood to be the complement of TEST*. The transistor
Q12 is also coupled to V.sub.CC, although no voltage source is
considered to be a part of the invention.
[0040] During testing, TEST* transmits a low voltage signal which
is received by the inverter 60. In response, the inverter 60
initiates a V.sub.CCP signal, sending it through transistor Q36
which outputs the V.sub.CCP signal to the gate of transistor Q10,
thereby switching on Q10. The feedback capacitor 62 serves to
maintain and replenish this V.sub.CCP signal in the event of
leakage. Capacitive coupling between the gate and drain of
transistor Q10 allows Q10 to carry signals having a range of
voltages for modifying the drive of the pulldown transistor Q3.
Simultaneously, the TEST signal, applying a high voltage to
transistor Q12, isolates V.sub.CC. A test data pattern is entered
into the memory cells 22 and read with varying voltages driving the
pulldown transistor Q3. The data read at various alternate voltages
sent through bond pad 36 can be compared with the data as
originally written. This series of readings indicates the range of
voltages through which the pulldown transistor Q3 is capable of
allowing accurate data readings. Once testing has ended, TEST*
sends a high voltage signal and TEST becomes low, thereby isolating
the bond pad and allowing the V.sub.CC signal to transmit to the
pulldown transistor Q3.
[0041] The embodiment illustrated in FIG. 5 is a package part of
the semiconductor circuit device and receives a plurality of
voltage sources with different magnitudes. The test circuit 26
allows selection among these sources for driving the gate of the
pulldown transistor Q3. The inverter 27 is the same as in FIG. 4.
In this exemplary embodiment, however, source node 30 is coupled to
three discrete voltage sources. First, source node 30 is coupled to
V.sub.CCP through a p-channel transistor Q20 that is driven by a
low signal A*. Source node 30 is also coupled to DVC.sub.2 through
another p-channel transistor Q22 that is driven by a low signal B*.
Finally, source node 30 is coupled to V.sub.CC by way of a
p-channel transistor Q24. This p-channel transistor Q24 is gated by
the output of a logic unit, such as a NAND gate 46, which will
drive transistor Q24 in response to receiving a high signal A as a
first input and a high signal B as a second input. Given the input
vector scheme of this embodiment, one of the transistors Q20, Q22,
or Q24 will be operable to the exclusion of the other two.
[0042] Thus, a low signal A* will drive the p-channel transistor
Q20, thereby allowing V.sub.CCP to drive the pulldown transistor
Q3. Simultaneously, signal B will be high, turning off p-channel
transistor Q22. Further, the NAND gate output will also be high and
turn off p-channel transistor Q24. If, on the other hand, signal B
is low and signal A is high, then only p-channel transistor Q22
will be on, allowing DVC.sub.2 to transmit to the pulldown
transistor Q3. Only when both signals A and B are high does the
NAND gate 46 output a low signal and allow V.sub.CC drive the
pulldown transistor Q3. The data read at these three voltage levels
can then be compared with the data as originally written. It should
be noted that this configuration does not require the die space
needed for the contact pad 36.
[0043] Another embodiment concerns varying the voltage applied to a
pullup sense amp 40. As seen in FIG. 1, the pullup sense amp 40
includes cross coupled p-channel transistors Q14 and Q16 as well as
a pullup transistor Q18. As one of ordinary skill in the art
understands, there is generally a pullup sense amp 40 corresponding
to every pulldown sense amp. Nevertheless, for purposes of clarity,
only one pullup sense amp 40 is shown. The sources of Q14 and Q16
are connected to a common pullup node 42, and the gate of each is
connected to the other's drain. Further, the gate of Q14 connects
to line D*, and the gate of Q16 connects to line D. Common pullup
node 42 is coupled with pullup transistor Q18, which is another
p-channel transistor. Pullup transistor Q18 is also coupled to the
voltage source V.sub.CC. The pullup transistor Q18 is driven by a
signal LEPSA*. FIG. 6 illustrates that the voltage driving pullup
transistor Q18 may also be varied through the use of a test circuit
26 analogous to that used with the pulldown transistor Q3 in FIG.
5. FIG. 6 depicts an inverter 27 comprising a p-channel transistor
Q26 and an n-channel transistor Q28. The coupled gates of inverter
transistors Q26 and Q28 form an input pathway 48 for a control
signal designated EPSA. The coupled drains transmit the inverted
output signal EPSA* which, in turn, is received by a prior art
device 50 that outputs the LEPSA* signal used to drive the pullup
transistor Q18. The source of Q26 is coupled to V.sub.CC, whereas
the source of Q28 is coupled to the test circuit 26 which, in this
embodiment, includes three conductive paths. The first path 52
leads to DVC.sub.2 by way of an n-channel transistor Q30, which is
driven by a signal C. The second path 54 is coupled to a voltage
source V.sub.BB through an n-channel transistor Q32, as driven by a
signal D. The third path 56 leads to ground by way of n-channel
transistor Q34. The gate of n-channel transistor Q34 is coupled to
the output of a NOR gate 58. The NOR gate 58 accepts signal C as a
first input and signal D as a second input and will activate
transistor Q34 only when both signals are low. Further, this
embodiment is configured in a manner analogous to the embodiment in
FIG. 5, in that signals C and D will never simultaneously activate
their respective transistors Q30 and Q32.
[0044] The three n-channel transistors Q30, Q32, and Q34 will turn
on if a high, or logic 1, signal is transmitted to their respective
gates. As with the embodiment shown in FIG. 5 for the pulldown
sense amp, the signals and transistors are configured to allow only
selective communication between one voltage source and the pullup
transistor Q18. As a result, if signal C is high, it will latch the
n-channel transistor Q30 and provide electrical communication
between DVC.sub.2 and the pullup transistor Q18. At the same time,
the low signal from D turns off n-channel transistor Q32. Under
these circumstances, the signals C and D also result in a low
signal output from the NOR gate 58, thereby turning off n-channel
transistor Q34. Thus, all of the other voltage sources are
isolated. Similarly, if signal D is high, then only n-channel
transistor Q32 is turned on and V.sub.BB electrically communicates
with pullup transistor Q18. When both signals are low, the NOR gate
58 outputs a high signal, thereby grounding the source of the
n-channel inverter transistor Q28. This embodiment has benefits
similar to the embodiment in FIG. 5.
[0045] Returning to FIG. 1, a prior art equilibration circuit can
be seen as part of the memory device. For purposes of explaining
the following embodiments of this invention, V.sub.CC is now
presumed to be 5 volts. A transistor Q101 is coupled between digit
line D and its complementary digit line D*. The transistor is
driven by an equilibration signal EQ. It should be noted that the
signal EQ results from a logic function and is distinguishable from
the equilibrate voltage Veq, which represents the common mid-range
voltage level of the complementary digit lines before a reading
operation.
[0046] The signal EQ also drives two additional transistors Q102
and Q103, which are connected together in series at a node 120.
These connected transistors Q102 and Q103 are also coupled between
lines D and D*. Moreover, node 120 is coupled to a cell plate 138
and a DVC.sub.2 voltage generator 68 through a bleeder device 122.
The DVC.sub.2 voltage generator 68 transmits a cell plate signal CP
of voltage DVC.sub.2 to the node 120. For purposes of explaining
the following embodiments of this invention, DVC.sub.2 is now 2.5
volts. The bleeder device 122 is driven by a signal of voltage
V.sub.CCP, wherein V.sub.CCP results from having pumped V.sub.CC to
an even higher potential.
[0047] At the beginning of a precharge cycle, digit line D and its
complementary digit line D* are at different voltages as a result
of a discharge of the memory cell 22 during the reading cycle. One
line will have a charge equal to the V.sub.CC value of 5 volts,
while the other line will have a 0 volt charge. The equilibrate
signal EQ is then sent, activating transistor Q101, which shorts D
and D* together. Moreover, the signal EQ activates transistors Q102
and Q103, which not only provide another short between D and D* but
also allow the CP signal to be communicated to those lines. As a
result, the lines D and D* equilibrate, both gaining a charge of
potential DVC.sub.2 (2.5 volts), which is the desired equilibrate
voltage Veq in this example. Once the lines are equilibrated, they
are ready for further testing.
[0048] For various reasons, a particular portion of the memory
array may be defective. Hopefully, testing processes will identify
those defects. As discussed above and illustrated in FIG. 7a, a
first defect 124 that may exist as a short to ground of the digit
line D. FIG. 7b illustrates the effect of the first defect 124.
During the precharge cycle, the CP signal is trying to charge the
digit lines D and D* to the 2.5 volt DVC.sub.2 level and maintain
that level. However, if the resistance of the short is not too
great, the first defect 124 may cause the digit lines to discharge
toward ground faster than CP can charge them to 2.5 volts. As a
result, once the precharge process has ended at time t.sub.1, the
digit lines may be equilibrated at a potential lower than 2.5
volts, such as 1.7 volts. Having a Veq at a level other than
DVC.sub.2 makes the memory array susceptible to reading errors. For
example, in the present situation illustrated in FIG. 7b, where Veq
is too low, line noise on D occurring at time t.sub.2 is more
likely to register as a logic 0 discharge when in fact the storage
cell 150 contains a logic 1 and has not yet discharged.
Alternatively, assuming that a logic 1 is properly discharged and
sensed at time t.sub.2', a reading error is still likely: as seen
in FIG. 7c, Veq may be so low due to the short that the pullup
sense amp may not be able to sufficiently pull up the digit line's
voltage by the time t.sub.3, when external circuitry accesses line
D. In order to find such a reading error, prior art requires an
extended precharge time, up to time t.sub.1, in order to allow the
discharge from the first defect 124 to overtake the charge from
CP.
[0049] The current invention, however, provides an alternative to
requiring a long precharge time. FIG. 7a illustrates that the
V.sub.CCP signal driving the bleeder device has been replaced with
the test circuit 26 that applies a different voltage V.sub.REG to
regulate the bleeder device. In the case of the first defect 124,
the test circuit 26 transmits a signal having a voltage lower than
V.sub.CCP to drive the bleeder device 122. This causes a slower
charge rate and allows the discharge from the first defect 124 to
quickly overtake the charging from CP, as seen by the dashed lines
in FIGS. 7b and 7c. With the resulting increased disparity between
the charge rate and the discharge rate, the precharge period need
only endure until time t.sub.1' in order to increase the likelihood
of detecting an error.
[0050] The design of test circuit 26 can be the same as those used
in FIGS. 4 and 5, wherein a source node 30 has access to at least
one test voltage, either through a bond pad 36 or from a discrete
voltage source. In this application, however, the source node 30 is
coupled to the bleeder device 122. Furthermore, V.sub.CCP is the
voltage used in non-test operations to drive the bleeder device,
and V.sub.CC and DVC.sub.2 are used to slow the charge rate. It
should be further understood that the number of voltage options
could be increased. Alternatively, the number of voltage options
could be decreased to offer only one test voltage and one non-test
voltage.
[0051] These circuit embodiments, as well as others falling under
the scope of the invention, have uses in detecting other defects.
FIG. 8a illustrates another defect 136 that might occur within a
memory array. The cross-sectional view in FIG. 8a shows the cell
plate 138 coupled to a first n-region 140 of access transistor Q4.
Ideally, the only way for the DVC.sub.2 voltage generator 68 to
charge the digit line D through the cell plate 138 is to drive the
gate 142 of transistor Q4 so that the charge may pass from the
first n-region 140 to a second n-region 144. From there, the charge
travels through a tungsten plug 146, which serves as a contact
between the second n-region 144 and the digit line D. Occasionally,
however, a second defect 136 in the memory array may occur in the
form of a short between the cell plate 138 and the tungsten plug
146. As discussed above, a long RAS low signal is used to detect
this second defect 136. Assuming line D is charged to 0 volts, FIG.
8b shows that the long RAS signal allows line D to be charged to a
higher voltage. Thus, when the low RAS signal ends at time t.sub.1
and the digit lines are shorted to begin equilibration, the digit
lines will no longer have an initial tendency to reach an average
potential between 5 and 0 volts (2.5 volts). Rather, because line D
is now higher than 0 volts, the shorted lines will settle at a
higher midpoint, such as 3.5 volts. At this point, the margin
between the new equilibrate voltage and the voltage representing a
logic 1 has decreased. Thus, an erroneous reading is more likely,
as discussed above.
[0052] Conversely, if line D is initially charged to V.sub.CC (FIG.
8c), the short to the cell plate will cause D's voltage to lower
during a long RAS low period. The resulting equilibrate voltage of
lines D and D* could be lower than the preferred 2.5 volts. The
lower equilibrate would again make an error in reading more likely.
In either case, the CP signal will restore the equilibrate voltage
to 2.5 volts by time t.sub.2. However, by decreasing the drive to
the bleeder device 122, any of the embodiments of the current
invention will serve to slow down the restoration of Veq to
DVC.sub.2. With restoration time extended to time t.sub.2', any
circuit embodiment of the current invention increases the
likelihood of detecting errors that would suggest the existence of
the second defect 136. Alternatively, FIG. 8d shows that a circuit
embodiment of the current invention could be used during a non-test
mode to compensate for the second defect 136 by driving the
isolation device 122 at a higher-than-normal level. As discussed
above, the bleeder device 122 is normally driven at V.sub.CCP, a
voltage level representing one or two V.sub.t's above V.sub.CC. The
potential V.sub.t, in turn, is the threshold voltage of the bleeder
device 122. A further increase in the potential of V.sub.CCP would
allow the bleeder device 122 to quickly restore Veq to 2.5 volts by
time t.sub.2". The shorter restoration period reduces the chances
of an erroneous reading.
[0053] FIG. 9a demonstrates yet another instance wherein the
current invention could shorten test time. This instance concerns a
third defect 148 comprising a short that may be caused by a nitride
defect within the storage capacitor 150 of a memory cell 22. It
should also be noted that one of the plates of the storage
capacitor 150 is in fact the cell plate 138 and is therefore
connected to the DVC.sub.2 generator. Given this third defect 148,
FIG. 9b indicates that the CP signal, having a potential of
DVC.sub.2, will charge the storage capacitor 150 toward that
potential even though a logic 0 has been written to that cell for
test purposes. During a static refresh pause, the word line WL
leading to the memory cell 22 will continuously transmit a low
signal, which turns off access transistor Q4 of the memory cell 22
and allows the storage capacitor 150 to take on a greater charge.
With the stored charge having a higher voltage, such as 2 volts, it
is more likely that the logic 0 will be misread at line D as a
logic 1. In order to speed up the leakage into the storage
capacitor 150, DVC.sub.2is forced to a voltage higher than the
normal 2.5 volts. Unfortunately, this would not result in much
benefit under the prior art, as demonstrated by FIG. 9c: because
the CP signal has a voltage of DVC.sub.2 and is in communication
with D and D* during the static refresh pause, the CP signal would
also charge lines D and D* to a higher voltage. With the circuit
embodiments of the present invention, however, a lower voltage
could be used to drive the bleeder device 122 and thereby slow the
charging of the digit lines, as illustrated in FIG. 9d. Thus, while
D and D* are regulated to substantially remain at 2.5 volts despite
the forced DVC.sub.2 voltage, the storage capacitor may be quickly
charged to a higher potential, such as 2.7 volts, which exceeds the
equilibrate voltage and makes it very likely that a logic 1 will be
mistakenly recognized.
[0054] One of ordinary skill can appreciate that, although specific
embodiments of this invention have been described for purposes of
illustration, various modifications can be made without departing
from the spirit and scope of the invention. Concerning the
invention as used with a sense amp, for example, a test circuit for
the pullup sense amp could be configured to transmit an entire
range of voltages through a contact pad, as done with the pulldown
sense amp depicted in FIG. 4. In addition, the test circuit 26 in
FIG. 6 could be used with a pulldown sense amp. Conversely, the
test circuit 26 in FIG. 5 could be used with a pullup sense amp.
Moreover, both of these test circuits could be coupled to the same
inverter and used to test drive either type of sense amp.
[0055] Further, regarding the embodiments use with a cell plate, it
should be noted that the embodiments may be applied for other
testing. Any circuit embodiment, for instance, may be used during
the precharge cycle discussed above in order to detect a short
between a row line and a column line. Moreover, a circuit
embodiment of the current invention could also be used during a
non-test mode to overcome other defects in addition to the short
between a digit line and cell plate, as described above.
[0056] It should also be noted that, given a particular voltage
source used in an embodiment, that source can be independent of
V.sub.CC rather than a mere alteration of V.sub.CC, such as
V.sub.CCP or DVC.sub.2. Accordingly, the invention is not limited
except as stated in the claims.
* * * * *