U.S. patent application number 09/760231 was filed with the patent office on 2001-06-14 for techniques for programming programmable logic array devices.
This patent application is currently assigned to Altera Corporation. Invention is credited to Bielby, Robert Richard N., Cliff, Richard G., Papaliolios, Andreas, Raman, Rina, Reddy, Sriniyas T., Sung, Chiakang, Terrill, Richard S., Veenstra, Kerry.
Application Number | 20010003844 09/760231 |
Document ID | / |
Family ID | 27418002 |
Filed Date | 2001-06-14 |
United States Patent
Application |
20010003844 |
Kind Code |
A1 |
Cliff, Richard G. ; et
al. |
June 14, 2001 |
Techniques for programming programmable logic array devices
Abstract
Programmable logic array devices are programmed from programming
devices in networks that facilitate programming any number of such
logic devices with programs of any size or complexity. The source
of programming data and control may be a microprocessor or one or
more serial EPROMs, one EPROM being equipped with a clock circuit.
Several parallel data streams may be used to speed up the
programming operation. A clock circuit with a programmably variable
speed may be provided to facilitate programming logic devices with
different speed characteristics. The programming protocol may
include an acknowledgment from the logic device(s) to the
programming data source after each programming data transmission so
that the source can automatically transmit programming data at the
speed at which the logic device is able to accept that data.
Inventors: |
Cliff, Richard G.;
(Milpitas, CA) ; Reddy, Sriniyas T.; (Fremont,
CA) ; Veenstra, Kerry; (San Jose, CA) ;
Papaliolios, Andreas; (Sunnyvale, CA) ; Sung,
Chiakang; (Milpitas, CA) ; Terrill, Richard S.;
(Santa Clara, CA) ; Raman, Rina; (Los Altos,
CA) ; Bielby, Robert Richard N.; (Pleasanton,
CA) |
Correspondence
Address: |
FISH & NEAVE
1251 AVENUE OF THE AMERICAS
50TH FLOOR
NEW YORK
NY
10020-1105
US
|
Assignee: |
Altera Corporation
2610 Orchard Parkway
San Jose
CA
|
Family ID: |
27418002 |
Appl. No.: |
09/760231 |
Filed: |
January 12, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09760231 |
Jan 12, 2001 |
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08851250 |
May 5, 1997 |
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6191608 |
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08851250 |
May 5, 1997 |
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08747194 |
Nov 12, 1996 |
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5680061 |
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08747194 |
Nov 12, 1996 |
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08658537 |
Jun 5, 1996 |
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Current U.S.
Class: |
326/38 ;
716/117 |
Current CPC
Class: |
G06F 30/34 20200101;
H03K 19/17758 20200101; H03K 19/17744 20130101; H03K 19/1774
20130101; H03K 19/17748 20130101 |
Class at
Publication: |
716/16 ;
716/17 |
International
Class: |
G06F 017/50 |
Claims
The invention claimed is:
1. An apparatus to program a plurality of programmable logic
devices (PLDS) located on respective integrated circuits,
comprising: a source configured to generate programming data, said
source being external to said integrated circuits; a second source
to generate a clock signal, said second source being external to
said integrated circuits; a first PLD device configured to receive
said programming data and said clock signal, said first PLD device
further configured to use said clock signal to clock said
programming data to program said first PLD device to a first logic
state, said first PLD device further including a done circuit which
is configured to generate a done signal when said first PLD device
is programmed to said first logic state; and a second PLD device
configured to receive said done signal, and in response thereto, is
further configured to receive said clock signal and said
programming data to program said second PLD device to a second
logic state.
2. The apparatus of claim 1, wherein said source configured to
generate said programming data and said second source configured to
generate said clock signal are a ROM device.
3. The apparatus of claim 1, wherein said programming data and said
clock signal are synchronized.
4. The apparatus of claim 1, further comprising a data bus coupled
between said programming data source and said first PLD device.
5. The apparatus of claim 4, wherein said data bus is further
coupled between said programming data source and said second PLD
device.
6. The apparatus of claim 1, wherein said first PLD device further
includes a program enable input that is configured to be tied to a
first input level to assure that said first PLD device is
configured to be programmed.
7. The apparatus of claim 1, wherein said first PLD device is
responsive to a configuration signal by preparing itself to be
re-programmed by said source configured to generate programming
data.
8. The method of programming a programmable logic integrated
circuit device from separate programming circuitry which includes
programming data memory and a single clock signal circuit that is
programmable to produce a clock signal having any of a plurality of
frequencies, each frequency being suitable for use as a programming
clock signal frequency by different ones of said programmable logic
integrated circuit device, said method comprising: determining a
one of said frequencies that is suitable for use as a programming
clock signal frequency by said programmable logic integrated
circuit device; programming said single clock signal circuit to
produce said clock signal with said one of said frequencies; and
applying programming data from said programming data memory to said
programmable logic integrated circuit device in synchronism with
said clock signal produced by said clock signal circuit at said one
of said frequencies.
9. The method defined in claim 8 wherein said applying comprises:
using said clock signal produced by said single clock signal
circuit to retrieve programming data from said programming data
memory at said one of said frequencies.
10. The method defined in claim 8 wherein said applying comprises:
applying said clock signal produced by said single clock signal
circuit to said programmable logic integrated circuit device as a
programming clock signal.
11. The method defined in claim 8 wherein said applying comprises:
applying said clock signal produced by said single clock signal
circuit to said programmable logic integrated circuit in parallel
with said programming data.
12. The method defined in claim 8 wherein said single clock signal
circuit includes a plurality of delay elements connected in series
and a plurality of programmable shunt circuits, each of which is
capable of effectively removing an associated subset of said delay
elements from said series by shunting said delay elements in said
associated subset, said frequency of said clock signal being
determined by the number of said delay elements that are
effectively present in said series, and wherein said programming
comprises: programming said shunt circuits to effectively remove
from said series a number of said delay elements appropriate to
cause said clock signal to have said one of said frequencies.
13. Programmable logic device apparatus comprising: a programmable
logic integrated circuit device configured to be programmed by
successive programming data signals applied to said device in
synchronism with a programming clock signal having one of a
plurality of different frequencies at which different such
programmable logic integrated circuit devices can be similarly
programmed by said same programming data; and programming circuitry
separate from said device and including a programming data memory
and a single clock circuit, said single clock circuit being
programmable to produce a programming clock signal having any one
of said plurality of different frequencies, said single clock
circuit being configured to apply programming data from said
programming data memory to said device as programming data signals
synchronized with said programming clock signal produced by said
single clock circuit with said one of said frequencies.
14. The apparatus defined in claim 13 wherein said single clock
circuit is further configured to retrieve programming data from
said memory at said one of said frequencies.
15. The apparatus defined in claim 13 further comprising: a first
connection between said programming circuitry and said device
configured to apply said programming clock signal produced by said
single clock circuit to said device.
16. The apparatus defined in claim 15 further comprising: a second
connection between said programming circuit and said device
configured to apply said programming data signals to said device in
parallel with said programming clock signal applied to said device
via said first connection.
17. The apparatus defined in claim 13 wherein said single clock
circuit comprises: a plurality of delay elements connected in
series; a plurality of programmable shunt circuits, each of which
is capable of effectively removing an associated subset of said
delay elements from said series by shunting said delay elements in
said associated subset, said frequency of said programming clock
signal being determined by the number of delay elements that are
selectively present in said series.
Description
[0001] This is a continuation of application Ser. No. 08/851,250,
filed May 5, 1997, which is a continuation application Ser. No.
08/747,194 filed Nov. 12, 1996, now is U.S. Pat. No. 5,680,061,
which is a continuation of application Ser. No. 08/658,537, filed
Jun. 5, 1996, now abandoned.
BACKGROUND OF THE INVENTION
[0002] This invention relates to programmable logic array devices,
and more particularly to techniques for programming such
devices.
[0003] Illustrative programmable logic array devices requiring
programming are shown in Cliff U.S. Pat. No. 5,237,219 and Cliff et
al. U.S. Pat. No. 5,434,514. Typically, such devices are
"programmed" in order to set them up to thereafter perform desired
logic functions. In other words, the programming determines what
logic functions the device will perform. The present invention is
particularly of interest in connection with programming
programmable logic array devices whose programming memory elements
are volatile and reprogrammable. For example, such devices
typically require reprogramming each time their power supplies are
turned on (from having been off). Such devices may also require
reprogramming whenever it is desired to change the logic functions
they perform, which may occur during certain normal uses of the
devices. Because such programming (or reprogramming) may have to be
performed relatively frequently, and because the logic devices are
generally not usable during programming, it is important to have
rapid and efficient programming techniques.
[0004] Programmable logic array devices are often designed to be
"general purpose" devices. In other words, the programmable logic
device is made without any particular end use in mind. It is
intended that the customer will use the number of such devices that
is appropriate to the customer's application, and that the customer
will program those devices in the manner required to enable them to
perform the logic required in the customer's application. Because
the size and complexity of various customer applications may vary
considerably, it would be desirable to have programming techniques
that are modular and lend themselves to programming different
numbers of devices with programs of different sizes.
[0005] In view of the foregoing, it is an object of this invention
to provide improved techniques for programming programmable logic
array devices.
[0006] It is another object of this invention to provide more rapid
techniques for programming programmable logic array devices.
[0007] It is still another object of this invention to provide
programmable logic array device programming techniques which lend
themselves to programming any number of such devices with programs
of any size or complexity.
SUMMARY OF THE INVENTION
[0008] These and other objects of the invention are accomplished in
accordance with the principles of the invention by providing
programmable logic array devices which can be programmed one after
another in any number from programming devices such as serial
erasable programmable read only memories ("serial EPROMs"). Any
number of such programming devices can be connected to operate
serially. Thus any number of logic devices can be programmed from
any number of programming devices, making the programming technique
highly modular and capable of performing programming tasks of any
size and complexity. The logic devices may be equipped with
programming register configurations that allow the logic device to
receive several programming data streams in parallel, thereby
speeding up the transfer of programming data from the programming
device(s) to the logic device(s). A programming device may be
equipped with a clock signal generating circuit whose operating
speed is programmably variable, thereby enabling the programming
device(s) to be used to program logic device(s) having different
clock rate requirements. Various communications protocols may be
used between the programming devices and the logic devices.
[0009] Further features of the invention, its nature and various
advantages will be more apparent from the accompanying drawings and
the following detailed description of the preferred
embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 is a simplified schematic block diagram of portions
of an illustrative programmable logic array device requiring
programming in accordance with this invention.
[0011] FIG. 2 is a simplified schematic block diagram of a network
of logic devices (each of which can be of the type shown in FIG. 1)
and programming data and control source devices in accordance with
a first illustrative embodiment of this invention.
[0012] FIG. 3 is a simplified block diagram of portions of an
alternative programmable logic device in accordance with this
invention.
[0013] FIG. 4 shows how the network of FIG. 2 can be modified in
accordance with this invention to program devices of the type shown
in FIG. 3.
[0014] FIG. 5 shows illustrative signals in networks of the types
shown in FIGS. 2 and 4.
[0015] FIG. 6 shows other illustrative signals in networks of the
types shown in FIGS. 2 and 4.
[0016] FIG. 7 shows more illustrative signals in networks of the
types shown in FIGS. 2 and 4.
[0017] FIG. 8 shows still more illustrative signals in networks of
the types shown in FIGS. 2 and 4.
[0018] FIG. 9 is a simplified schematic block diagram of a circuit
which can be used on one of the programming devices in FIG. 2 or
FIG. 4 in accordance with this invention.
[0019] FIG. 10 is a simplified schematic block diagram similar to
FIG. 2 or FIG. 4 showing an alternate signalling scheme for
programming data in accordance with this invention.
[0020] FIG. 11 shows illustrative signals in networks of the type
shown in FIG. 10.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0021] Although the invention is equally applicable to programming
other types of programmable logic array devices, the invention will
be fully understood from the following explanation of its
application to programming programmable logic array devices of the
general type shown in FIG. 1 (which depicts a structure like that
shown in Cliff U.S. Pat. No. 5,237,219 and Cliff et al. U.S. Pat.
No. 5,434,514, both of which are incorporated by reference herein).
Programmable logic array device 10, which is preferably a single
integrated circuit, includes a shift register 20 having a plurality
of serially connected shift register stages 20A-20m. (The letter
"m" is used in FIG. 1 as a general index limit which can have any
desired value.) Programming data supplied to device 10 via lead
DATA from an external programming data source is shifted into shift
register 20 from left to right as viewed in FIG. 1 by clock pulses
applied to lead DCLK. In accordance with the present invention, the
DCLK pulses also come from a source external to device 10. When
register 20 is fully loaded, a signal supplied to the BCLK lead
loads all the stages 30A-30m of register 30 in parallel from
register 20. The BCLK signal may be generated by device 10 itself
based on counting the DCLK pulses and producing a BCLK pulse after
each m DCLK pulses have been received. A count of m DCLK pulses
indicates that register 20 is full and ready to be dumped to
register 30. Dumping register 20 to register 30 makes it possible
for register 20 to immediately begin shifting in more programming
data, while the data in register 30 is going in parallel into the
programmable registers 40 of device 10 as will now be
described.
[0022] Each stage of register 30 feeds data to an associated chain
of programmable registers 40. For example, register stage 30A feeds
the chain of registers that includes stages 40Ala through 40And
(where again the letters "d" and "n" are used as index limits which
can have any desired values). These register chains may be
so-called "first-in-first-out" or "FIFO" chains which progressively
fill with data from the bottom (e.g., stage 40And) to the top
(e.g., stage 40Ala). In other words, the first programming data bit
supplied to a chain from register 30 passes down through all the
stages of the chain to be stored in the bottom-most stage. Device
10 then cuts off the bottom-most stage so that the next programming
data bit supplied to the chain from register 30 is stored in the
next to bottom-most stage of the chain, which is then cut off from
the stages above. This process continues until all the stages of
registers 40 have been programmed. More detail regarding this type
of FIFO chain programming will be found in above-mentioned Cliff
U.S. Pat. No. 5,237,219.
[0023] Each stage of each register 40 controls some aspect of the
programmable logic 50 of device 10. For example, register stages
40Ala-40Ald control various portions of the programmable logic in
logic array block 50A1, while register stages 40A2a-40A2d control
various portions of the programmable logic in logic array block
50A2. It will be understood that each of logic array blocks 50 is
capable of performing any of several logic functions, depending in
part on how it is controlled by the programming signals stored in
the associated register 40 stages.
[0024] In addition to the elements described above, device 10
typically includes a network of conductors (not shown) for
interconnecting logic array blocks 50 with one another and with
input and output pins (also not shown) of device 10. An
illustrative arrangement of such other elements is shown in Cliff
et al. U.S. Pat. No. 5,260,611, which is also hereby incorporated
by reference herein.
[0025] An illustrative network in accordance with this invention
for applying programming data to one or more programmable logic
array devices 10a, 10b, etc. (each of which can be like device 10
in FIG. 1) is shown in FIG. 2. Each of devices 10a, 10b, etc. is
typically a separate integrated circuit. Each of devices 100a,
100b, etc. is also typically a separate integrated circuit. For
example, each of devices 100 may be a serial erasable programmable
read only memory ("serial EPROM"). Device 100a is the main device
of this kind. Device 100b is an auxiliary device which is included
only if device 100a does not have enough capacity to store all the
programming data needed to program all of the connected devices 10.
As suggested by the dots on the left, additional auxiliary devices
100 may be included if needed to provide still more programming
data storage capacity.
[0026] When power is first applied to devices 10 and 100, each of
those devices pulls down on node N1 via its nSTATUS or nERR
terminal until it is ready to operate. When each of devices 100 is
no longer pulling down on node N1, each of those devices monitors
(via its nERR terminal) the level of the signal at node N1. When
all of the devices connected to node N1 are ready to operate and no
device is pulling down on that node, the electrical potential of
that node rises to VCC. This indicates to devices 100 that
programming of devices 10 can begin.
[0027] Each of devices 10 also pulls down on node N2 via its
CONDONE terminal until that device is fully programmed. As long as
node N2 is low, device 100a is enabled to operate via its nCE input
terminal. Each of devices 10 can detect when it is fully
programmed, for example, by counting the number of DCLK pulses it
has received since it was enabled via its nCE input terminal.
[0028] The nCONFIG signal is a reset type signal which can be used
to initiate a re-programming of devices 10. For example, if
programming of devices 10 were controlled by a microprocessor with
the ability to select different programming data at different times
(e.g., to change the logic functions performed by devices 10), the
microprocessor could apply an appropriate nCONFIG signal to devices
10 whenever re-programming is desired. Among the effects of an
nCONFIG request for re-programming of devices 10 is that each of
devices 10 again pulls down on node N2 via its CONDONE terminal.
This can be used to signal the programming data source that devices
10 are ready to begin receiving new programming data. Other effects
of an nCONFIG request for re-programming are (1) readying each
device 10 to again begin counting DCLK pulses from a reset starting
value, and (2) restoring the nCEO output signal of each device 10
to its initial unprogrammed value.
[0029] Device 10a is enabled to accept programming data at all
times because its nCE input terminal is tied to ground. Until each
device 10 is fully programmed, that device applies to the nCE input
terminal of the next device in the series of devices 10 an input
signal that prevents the next device from accepting programming
data. Devices 10 are therefore programmed one after another in
order, beginning with device 10a.
[0030] When device 100a is enabled by node N1 being high while node
N2 is low, device 100a begins issuing clock signals on its DCLK
output lead, as well as issuing programming data bits (synchronized
with the DCLK pulses) on its DATA output lead. These data and clock
signals are respectively applied to the DATA and DCLK input
terminals of all of devices 10. At first, however, only device 10a
responds to these signals because only device 10a has a chip
enabling signal applied to its nCE input terminal. Thus only device
10a operates as described above in connection with FIG. 1 to take
in the programming data and make use of that data for programming
itself.
[0031] Once device 10a is fully programmed, it cannot respond to
any more programming data even though more such data and DCLK
pulses may be applied to it. As soon as device 10a is fully
programmed, it applies a chip enabling signal to the nCE input
terminal of device 10b. This enables device 10b to begin to take in
the programming data applied to its DATA input terminal at the DCLK
rate. This begins the programming of device 10b. When device 10b is
fully programmed, it produces an nCEO output signal suitable for
enabling the next device 10 to begin accepting programming data.
(The possible presence of such further devices 10 is indicated by
the dots extending to the right in FIG. 2.) The process of
successively programming devices 10 continues until all of those
devices have been fully programmed. Node N2 then rises to VCC,
thereby disabling device 100a and any other devices 100 in the
network. For example, when thus disabled, device 100a stops issuing
DCLK signals and otherwise goes into a state in which it consumes
little or no power. (Via the nCEO-nCE connection chain between
devices 100, any other device(s) 100 in the network are similarly
placed in a low or no power state when node N2 rises to VCC.)
[0032] It should be noted that all of devices 10 also monitor (via
their CONDONE terminals) the level of the node N2 signal. When node
N2 rises to VCC, each of devices 10 responds by preparing to begin
normal operation as a logic device. This may include such
conventional operations as resetting various clocks and counters,
releasing the reset on various registers, and enabling output
drivers.
[0033] If more data is required to program devices 10 than can be
produced by one device 100, then device 100a is supplemented by
additional devices such as 100b. As long as device 100a is applying
data to the data bus of the network, device 10a applies to the nCE
input terminal of device 100b a high signal which disables device
100b. (Each device 100 also applies such a high signal to the
adjacent device 100 as long as the signal applied to its nCE input
terminal is high.) Device 100b also receives the DCLK output signal
of device 100a, but device 100b cannot and does not respond to that
signal until it is enabled by a chip enabling signal applied to its
nCE input terminal.
[0034] When device 10a has applied the last of its data to its DATA
output terminal, it changes the state of the signal applied to the
nCE terminal of device 100b. This enables device 100b to begin
responding to the applied DCLK signal, which device 100a continues
to produce at the same rate. Device 100b then begins to output its
data via its DATA output terminal at the DCLK rate. The data from
device 100b therefore becomes a continuation of the data stream
from device 100a and programming of devices 10 accordingly
continues on the basis of that data.
[0035] If even more programming data is required than can be held
by devices 100a and 100b, the series of devices 100 can be extended
to as many as are required to hold all the necessary data. Device
100b applies a chip enabling signal to the nCE terminal of the next
device 100 after it has output all of its data. The next device 100
is thereby enabled to respond to continued DCLK pulses from device
100a and to begin outputting its data via its DATA output
terminal.
[0036] It will be apparent from the foregoing that there is no
required correlation between the relative sizes of devices 10 and
devices 100, although it is preferred for each transition from one
device 100 to the next to occur at the end of a "frame" of data. (A
"frame" of data is the data required to fill register 20. There may
be a small delay in the start-up of each successive device 100. To
cope with this, each device 100 initially outputs a few dummy data
values (e.g., a series of binary ones) which are ignored by the
device 10 being programmed. To facilitate ignoring such dummy data
it preferably occurs between frames of data rather than in the
midst of a frame of data. Thus it is preferred that transitions
between devices 100 occur between frames of real programming data.)
Except for the possible minor constraint explained in the
immediately preceding parenthetical, the transitions between
deriving programming data from successive devices 100 can occur at
any times relative to the transitions between programming
successive devices 10. For example, programming data may stop
coming from device 100a and start coming from device 100b at the
end of a frame of data halfway through the programming of device
10b. The programming networks of this invention are therefore
highly modular and flexible with regard to device sizes. Devices 10
of any size(s) can be used with devices 100 of any size(s), again
bearing in mind the preference for transitions from one device 100
to the next device 100 at the end of a frame of date.
[0037] FIG. 3 shows an alternative embodiment 10' of programmable
logic array device 10 which can be programmed more rapidly than
device 10. In device 10' shift register 20' has several data input
terminals D0 through DN spaced equally along its length. For
example, if shift register 20' has 100 stages (from stage 0 at the
left to stage 99 at the right), and if N=9, then data input
terminal D0 is at stage 0, terminal D1 is at stage 10, terminal D2
is at stage 20, and so on through input terminal D9 at stage 90.
Register 20' receives data in parallel at its several data input
terminals and shifts that data to the right at the DCLK rate. (Data
is not shifted from the left into shift register stages having
inputs D0-DN. Thus shift register 20' may alternatively be N+1
separate shift registers, each having a respective one of inputs
D0-DN.) Accordingly, the time required to fill register 20' from
its several data input terminals is only 1/(N+1) the time required
to fill register 20 in FIG. 1 from its single data input terminal.
In other respects device 10' can be identical to device 10. Thus
each time device 10' detects (e.g., by counting DCLK pulses that
have been received) that register 20' contains data that is all new
since the last BCLK pulse, device 10' applies a BCLK pulse to
register 30. As in device 10, this causes register 30 to accept in
parallel all the data contained in register 20'. Register 20' is
thereby freed to begin accepting new data via its D0-DN input
terminals, while the data in register 30 is used to program the
main portion 40/50 of device 10' as described above in connection
with FIG. 1.
[0038] FIG. 4 shows how the network of FIG. 2 can be modified for
programmable logic array devices 10' of the type shown in FIG. 3.
Instead of one data input terminal as in FIG. 2, each device 10a',
10b', etc. in FIG. 4 has N+1 data input terminals. Similarly, each
device 100a', 100b', etc. in FIG. 4 has N+1 data output terminals
rather than one such terminal as in FIG. 2. (Alternatively, each of
devices 100' could be N+1 serial devices arranged in parallel.)
Thus one of devices 100' outputs N+1 programming data bits in
parallel during each DCLK pulse interval, and one of devices 10'
inputs those data bits during that interval. The data bus in FIG. 4
is therefore N+1 conductors wide, rather than being a single
conductor as in FIG. 2. In all other respects the network of FIG. 4
may be constructed and may operate exactly as described above in
connection with FIG. 2.
[0039] A typical signal sequence in FIG. 2 or FIG. 4 when only one
device 100a or 100a'is needed to program device(s) 10 or 10' is
shown in FIG. 5. (The nCE and nCEO signals shown in FIG. 5 are
those associated with device 100a or 100a'.) At 120 all of devices
10 and 100a or 10' and 100a' have signalled that they are ready to
begin the programming process. The level of the signal at node N1
therefore rises to VCC. Device 100a or 100a' responds by beginning
to produce synchronized DCLK and DATA output signals. Each DATA
signal pulse in FIG. 1 represents either a bit of data (in the case
of networks of the type shown in FIG. 2) or a word of data (in the
case of networks of the type shown in FIG. 4).
[0040] Assuming that n bits or words of data are required to fully
program device(s) 10 or 10', when device 100a or 100a' outputs the
last bit or word, device(s) 10 or 10' detect that they are filled
and allow the signal at node N2 to rise to VCC as shown at 122 in
FIG. 5. Device 100a or 100a' then produces a few more (e.g., 16)
DCLK pulses. If no error conditions are detected during those
further DCLK pulses, the programming process has been completed
successfully and device 100a or 100a' switches to the low or no
power mode described above. (Examples of error conditions are
discussed below in connection with FIGS. 7 and 8.)
[0041] FIG. 6 illustrates a typical signalling sequence in FIG. 2
or FIG. 4 when two or more devices 100 or 100' are required to
produce the data needed to program the device(s) 10 or 10' in the
network. In FIG. 6 the upper signals nCE, DCLK, DATA, and nCEO are
associated with device 100a or 100a', while the lower signals nCE,
DCLK, DATA, and nCEO are associated with device 100b or 100b'. FIG.
6 assumes that all of the devices 100 or 100' in a network are
constructed identically, for example, with the capability of
producing a DCLK signal. As described above, however, only the main
device 100a or 100a' actually produces the DCLK signal.
[0042] Considering FIG. 6 now in more detail, transition 120 is
identical to transition 120 in FIG. 5. Immediately after transition
120, each device 100 or 100' detects whether it is the main device
of that type or an auxiliary device of that type. This
determination can be made on the basis of the level of the applied
nCE signal when transition 120 occurs. The device 100 or 100' with
the low nCE signal at transition 120 is the main device 100a or
100a'. Devices 100 or 100' with a high nCE signal at transition 120
are auxiliary devices like 100b or 100b'. Thus in FIG. 6 the device
100a or 100a' associated with the upper signals nCE, DCLK, DATA,
and nCEO determines that it is the master device and begins
producing synchronized DCLK and DATA pulses shortly after
transition 120 as described above in connection with FIG. 5.
[0043] When device 100a or 100a' is about to produce its last bit
(FIG. 2) or word (FIG. 4) of data m, device 100a or 100a' causes
its nCEO output signal to transition from high to low as shown at
130. This causes a similar transition 132 in the nCE input signal
of first auxiliary device 100b or 100b'. Device 100a or 100a' then
produces its final data output m and thereafter stops producing
data. However, device 100a or 100a' continues to produce DCLK
output pulses, and device 100b or 100b' begins to respond to those
pulses by producing DATA signals m+1, m+2, etc. in synchronism with
the DCLK pulses from device 100a or 100a'.
[0044] After device 100b or 100b' has produced its last data n, the
device(s) 10 or 10' in the network signal a full condition by
allowing the nCE signal applied to device 100a or 100a' to rise to
VCC as shown at 122. This causes device 100a or 100a' to raise its
nCEO output signal to VCC as shown at 134, which similarly raises
the nCE input signal of device 100b or 100b' to VCC as shown at
136. Device 100b or 100b' is thereby placed in a low or no power
mode, and after a predetermined number of further clock pulses from
device 100a or 100a', that device also enters a low or no power
mode.
[0045] If desired, the apparatus shown in FIGS. 1-4 may include
various types of programming error detection signalling. For
example, FIG. 7 shows any of devices 10 or 10' using the level of
the signal at node N1 to indicate that it has detected a
programming error. Devices 100 or 100' respond to such an
indication by stopping and restarting the programming
operation.
[0046] With more detailed reference to FIG. 7, at 150 (similar to
120 in FIG. 5 or FIG. 6) the signal at node N1 (FIG. 2 or FIG. 4)
goes high, indicating that all of devices 10 and 100 or 10' and
100' are ready for programming to begin. The nCE signal is also
low, indicating that devices 10 or 10' are as yet unprogrammed.
Shortly after transition 150, device 100 or 100' begins to output
synchronized DCLK and DATA signals. The successive bits (FIG. 2) or
words (FIG. 4) of DATA are numbered 1, 2, 3, . . . n, n+1, etc. in
FIG. 7. At time 152 one of devices 10 or 10' detects that it has
not received correct programming data or that something else has
gone wrong with the programming process. That device 10 or 10'
therefore uses its nSTATUS terminal to lower the level of the
signal at node N1. This is detected by devices 100 or 100' via
their nERR terminals. Devices 100 or 100' therefore shortly
thereafter cease outputting DCLK and DATA signals and reset
themselves to prepare to restart the programming process. All of
devices 10 or 10' also detect that the level of the signal at node
N1 has been pulled down. Devices 10 or 10' therefore also all reset
themselves to prepare for the restarting of the programming
process.
[0047] After a suitable time-out interval, the device 10 or 10'
that detected the programming error and caused transition 152
allows the nSTATUS/nERR signal to again rise to VCC as shown at
154. Transition 154 is like transition 150, and so shortly
thereafter device 100 or 100' again begins outputting synchronized
DCLK and DATA signals, beginning again with the programming data at
the start of the programming data sequence.
[0048] Another example of programming error detection signalling
that may be used in systems of the type shown in FIGS. 2 or 4 is
illustrated by FIG. 8. The first portion of FIG. 8 is identical to
FIG. 7, except that FIG. 8 additionally shows a counter which is
preferably located on device 100a or 100a' for counting the number
of data bits (FIG. 2) or words (FIG. 4) that have been output by
devices 100 or 100'. Assuming that the entire program consists of n
bits or words, when that amount of data has been output, the
counter reaches a count of n and devices 100 or 100' stop
outputting data. Device 100a or 100a' then waits a predetermined
number of DCLK cycles for the signal at node N2 to rise to VCC. As
described above, devices 10 or 10' should allow this to happen when
each of those devices recognizes that it is fully programmed.
However, if for any reason one of devices 10 or 10' has not been
fully programmed, it does not allow the level of the signal at node
N2 to rise to VCC. If the above-mentioned predetermined number of
DCLK cycles passes without the signal at node N2 rising to VCC,
this is detected by device 100a or 100a' via that device's nCE
terminal. Device 100a or 100a' then knows that one of devices 10 or
10' was not fully programmed and that the programming process
should be repeated. Device 100a or 100a' therefore pulls down the
signal at node N1 as shown at 160. This resets all of devices 10
and 100 or 10' and 100''. After a predetermined time-out interval,
device 100a or 100a' allows the signal to transition back to VCC as
shown at 162, which restarts the programming process as at
transition 150.
[0049] In order to facilitate programming of programmable logic
array devices 10 or 10' having different speed capabilities, device
100a or 100a' may include a DCLK circuit having a programmably
adjustable clock rate. An illustrative embodiment 200 of such a
circuit is shown in FIG. 9. A signal pulse propagates repeatedly
around the closed loop made up of inverters 210a-210w, although it
will be understood that the number of inverters in this loop is
arbitrary and that some of the inverters may sometimes be switched
out of use as will be more fully explained below. The loop of
inverters 210 is tapped at one location by inverters 220 to produce
the DCLK output signal. The clock rate of the DCLK signal is
determined by the time required for a signal to propagate all the
way around the inverter loop.
[0050] In order to adjust the DCLK rate, several groups of
inverters 210 can be short-circuited to effectively remove them
from the inverter loop. For example, inverters 210a-210d can be
short-circuited by closing switch 230a. Switch 230b is opened
whenever switch 230a is closed to avoid having more than one path
around the inverter loop at any one time. Similarly, inverters 210e
and 210f can be short-circuited by closing switch 230c and opening
switch 230d. Inverters 210r and 210s can be short-circuited by
closing switch 230e and opening switch 230f. Inverters 210t-210w
can be short-circuited by closing switch 230g and opening switch
230h. A programmable register 240 on device 100a or 10a' controls
the status of switches 230. Stage R1 of register 240 controls the
status of switches 230a and 230b in complementary fashion. Stage R2
of register 240 similarly controls the status of switches 230c and
230d. Stage R3 of register 240 controls the status of switches 230e
and 230f. And stage R4 of register 240 controls the status of
switches 230g and 230h.
[0051] From the foregoing, it will be apparent that the clock rate
of the DCLK signal can be adjusted by appropriately programming
register 240. For example, if the "normal" clock rate is the result
of having inverters 210a-210f in the circuit, but having inverters
210r-210w short-circuited, the following table indicates how the
clock rate can be increased (fewer inverter delays) or decreased
(more inverter delays) from the normal rate:
1 TABLE I Clock Rate (Number of Inverter Delays Open Closed
Register Minus or Plus Switches Switches 240 from Normal) 230 230
Data -6 (faster clock b,d,f,h a,c,e,g 0011 rate) -4 b,c,f,h a,d,e,g
0111 -2 a,d,f,h b,c,e,g 1011 normal a,c,f,h b,d,e,g 1111 +2 a,c,e,h
b,d,f,g 1101 +4 a,c,f,g b,d,e,h 1110 +6 (slower clock a,c,e,g
b,d,f,h 1100 rate)
[0052] Device 100a or 100a' can be programmed via register 240 to
produce a slower DCLK rate when the programmable logic array
devices 10 or 10' being programmed are relatively slow. Device 100a
or 100a' can be programmed to produce a faster DCLK rate when the
programmable logic array devices 10 or 10' being programmed are
relatively fast. This facilitates providing one type of device 100a
or 100a' that is suitable for programming a wide range of devices
10 or 10'.
[0053] FIGS. 10 and 11 show another type of programming signalling
that can be used in accordance with this invention if desired. In
FIG. 10 each of devices 310a, 310b, etc., can be similar to a
device 10 in FIG. 2 or a device 10' in FIG. 4. Device 400 can be
similar to device 100a in FIG. 2 or device 100a' in FIG. 4. Instead
of producing a DCLK signal, however, device 400 produces a data
available ("DAV") signal transition 420a short time after each
possible transition 410 in the programming DATA signal. The DAV
output signal of device 400 is applied to the DAV input terminal of
each of devices 310. A short time after receiving each DAV signal
transition 420, the device 310 currently being programmed shifts in
the DATA signal currently being applied to its DATA input terminal.
Then the device 310 currently being programmed produces a data
acknowledge ("DACK") signal transition 430 to acknowledge that it
has received the DATA signal. The DACK signal is applied to device
400. After receiving each DACK signal transition 430, device 400
causes the DAV signal to transition (as at 422) back to its
original condition. The device 310 currently being programmed
detects each DAV signal transition 422 and responds shortly
thereafter by causing the DACK signal to transition (as at 432)
back to its original condition. Device 400 detects each DACK signal
transition 432 and shortly thereafter (at 410) begins to output the
next DATA signal pulse. This begins the next sequence of DAV and
DACK signal transitions 420, 430, 422, and 432.
[0054] An advantage of the signalling scheme illustrated by FIGS.
10 and 11 is that the programming data source device 400
automatically adjusts to whatever speed the device currently being
programmed is capable of receiving programming data at. Without
this type of signalling scheme, programming device 400 must be set
to send out data no faster than the slowest device 310 that may
need to be programmed. If, as is often the case, different devices
310 may be able to accept programming data at different speeds,
this will mean that device 400 will have to be set to operate more
slowly than many devices 310 are capable of having it operate. The
result will be slower average programming time. By using the
signalling technique illustrated by FIGS. 10 and 11, each device
310 is automatically programmed at whatever speed it can accept
data. This will shorten programming time for many devices 310.
[0055] Except as described above, the apparatus of FIG. 10 may be
constructed and operate as previously described in connection with
FIG. 2 or FIG. 4. Thus the DATA bus in FIG. 10 may be either a
single lead (as in FIG. 2) or several parallel leads (as in FIG.
4).
[0056] It will be understood that the foregoing is only
illustrative of the principles of this invention, and that various
modifications can be made by those skilled in the art without
departing from the scope and spirit of the invention. For example,
logic devices 10 and 10' can have other, conventional, internal
organizations of their programming and logic circuitry (e.g.,
elements 40 and 50 in FIG. 1). As another example of modifications
within the scope of the invention, a microprocessor can be used in
place of devices 100 or 100' in networks of the type shown in FIGS.
2 and 4.
* * * * *