Shu; Jiehui

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shu; Jiehui.The latest application filed is for "gate structures".

Company Profile

96.77.77

Shu; Jiehui - Dalian CN
Shu; Jiehui - Clifton Park NY
Shu; Jiehui - Ballston Lake NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Asymmetric source drain structures Grant 11,362,178 - Shu , et al. June 14, 2	2022-06-14
Electrical fuse formation during a multiple patterning process Grant 11,348,870 - Shu , et al. May 31, 2	2022-05-31
Methods of forming transistor devices comprising a single semiconductor structure and the resulting devices Grant 11,349,030 - Shu , et al. May 31, 2	2022-05-31
Semiconductor device with gate cut structure Grant 11,349,028 - Shu May 31, 2	2022-05-31
Fin-type field effect transistor with reduced fin bulge and method Grant 11,264,382 - Shu , et al. March 1, 2	2022-03-01
Limiting lateral epitaxy growth at N-P boundary using inner spacer, and related structure Grant 11,217,584 - Holt , et al. January 4, 2	2022-01-04
Gate Structures App 20210376106 - SHU; Jiehui ; et al.	2021-12-02
Transistors with a hybrid source or drain Grant 11,177,385 - Wang , et al. November 16, 2	2021-11-16
Middle of line gate structures Grant 11,171,237 - Shen , et al. November 9, 2	2021-11-09
Semiconductor devices with low resistance gate structures Grant 11,145,716 - Lee , et al. October 12, 2	2021-10-12
Gate structures Grant 11,127,834 - Shu , et al. September 21, 2	2021-09-21
FinFET device comprising a single diffusion break with an upper surface that is substantially coplanar with an upper surface of a fin Grant 11,121,023 - Shu , et al. September 14, 2	2021-09-14
IC products formed on a substrate having localized regions of high resistivity and methods of making such IC products Grant 11,114,466 - Gu , et al. September 7, 2	2021-09-07
Multiple threshold voltage devices Grant 11,094,598 - Krishnan , et al. August 17, 2	2021-08-17
Transistors With Separately-formed Source And Drain App 20210249508 - Shu; Jiehui ; et al.	2021-08-12
Transistors With A Hybrid Source Or Drain App 20210242344 - Wang; Haiting ; et al.	2021-08-05
Self-aligned Contact App 20210242317 - GU; Sipeng ; et al.	2021-08-05
Ic Products Formed On A Substrate Having Localized Regions Of High Resistivity And Methods Of Making Such Ic Products App 20210233934 - Gu; Sipeng ; et al.	2021-07-29
LDMOS integrated circuit product Grant 11,075,298 - Shu , et al. July 27, 2	2021-07-27
Transistors with separately-formed source and drain Grant 11,075,268 - Shu , et al. July 27, 2	2021-07-27
Methods Of Forming Transistor Devices Comprising A Single Semiconductor Structure And The Resulting Devices App 20210217887 - Shu; Jiehui ; et al.	2021-07-15
Semiconductor structures in a wide gate pitch region of semiconductor devices Grant 11,043,566 - Shu , et al. June 22, 2	2021-06-22
Gate Cut Isolation Including Air Gap, Integrated Circuit Including Same And Related Method App 20210183997 - Yu; Hong ; et al.	2021-06-17
Semiconductor structures over active region and methods of forming the structures Grant 11,031,389 - Shu , et al. June 8, 2	2021-06-08
Asymmetric Source Drain Structures App 20210143254 - SHU; Jiehui ; et al.	2021-05-13
Mask-free methods of forming structures in a semiconductor device Grant 11,004,953 - Lee , et al. May 11, 2	2021-05-11
Semiconductor devices with wide gate-to-gate spacing Grant 11,004,748 - Gu , et al. May 11, 2	2021-05-11
Limiting Lateral Epitaxy Growth At N-p Boundary Using Inner Spacer, And Related Structure App 20210125984 - Holt; Judson R. ; et al.	2021-04-29
Gate Structures App 20210111264 - SHU; Jiehui ; et al.	2021-04-15
Semiconductor Structures In A Wide Gate Pitch Region Of Semiconductor Devices App 20210111261 - SHU; JIEHUI ; et al.	2021-04-15
Gate cut isolation including air gap, integrated circuit including same and related method Grant 10,971,583 - Yu , et al. April 6, 2	2021-04-06
Multi-step insulator formation in trenches to avoid seams in insulators Grant 10,964,599 - Sirman , et al. March 30, 2	2021-03-30
Semiconductor Device With Gate Cut Structure App 20210074842 - SHU; JIEHUI	2021-03-11
Etch stop member in buried insulator of SOI substrate to reduce contact edge punch through Grant 10,943,814 - Sporer , et al. March 9, 2	2021-03-09
Diffusion break structures in semiconductor devices Grant 10,937,685 - Gu , et al. March 2, 2	2021-03-02
Etch Stop Member In Buried Insulator Of Soi Substrate To Reduce Contact Edge Punch Through App 20210057271 - Sporer; Ryan W. ; et al.	2021-02-25
Transistors With Separately-formed Source And Drain App 20210050419 - Shu; Jiehui ; et al.	2021-02-18
Semiconductor Device With Reduced Parasitic Capacitance App 20210050425 - PANDEY; SHESH MANI ; et al.	2021-02-18
Vertical resistor adjacent inactive gate over trench isolation Grant 10,923,469 - Zang , et al. February 16, 2	2021-02-16
Structure With Counter Doping Region Between N And P Wells Under Gate Structure App 20210043766 - Zhu; Baofu ; et al.	2021-02-11
Mask-free methods of forming structures in a semiconductor device Grant 10,896,853 - Shu , et al. January 19, 2	2021-01-19
Multiple Threshold Voltage Devices App 20210013109 - KRISHNAN; Bharat V. ; et al.	2021-01-14
Fin-type Field Effect Transistor With Reduced Fin Bulge And Method App 20210005601 - Shu; Jiehui ; et al.	2021-01-07
Mask-free Methods Of Forming Structures In A Semiconductor Device App 20200411664 - LEE; RINUS TEK PO ; et al.	2020-12-31
Methods Of Forming An Ldmos Device And The Resulting Integrated Circuit Product App 20200411684 - Shu; Jiehui ; et al.	2020-12-31
Diffusion Break Structures In Semiconductor Devices And Methods Of Forming The Same App 20200402838 - GU; SIPENG ; et al.	2020-12-24
Semiconductor Structures Over Active Region And Methods Of Forming The Structures App 20200395356 - SHU; JIEHUI ; et al.	2020-12-17
Semiconductor Devices With Wide Gate-to-gate Spacing App 20200388540 - GU; SIPENG ; et al.	2020-12-10
Contact Structures Over An Active Region Of A Semiconductor Device App 20200373410 - LEE; TUNG-HSING ; et al.	2020-11-26
Semiconductor device with reduced parasitic capacitance Grant 10,840,245 - Pandey , et al. November 17, 2	2020-11-17
Spacer structures on transistor devices Grant 10,833,171 - Shen , et al. November 10, 2	2020-11-10
Metal resistor structure in at least one cavity in dielectric over TS contact and gate structure Grant 10,833,067 - Wang , et al. November 10, 2	2020-11-10
Metal resistors with a non-planar configuration Grant 10,832,839 - Beasor , et al. November 10, 2	2020-11-10
Mask-free Methods Of Forming Structures In A Semiconductor Device App 20200343142 - SHU; JIEHUI ; et al.	2020-10-29
Electrical Fuse Formation During A Multiple Patterning Process App 20200335435 - Shu; Jiehui ; et al.	2020-10-22
Spacer Structures On Transistor Devices App 20200335600 - Shen; Yanping ; et al.	2020-10-22
Middle Of Line Gate Structures App 20200335619 - SHEN; Yanping ; et al.	2020-10-22
Method of manufacturing FinFET with reduced parasitic capacitance and FinFET structure formed thereby Grant 10,811,409 - Shu , et al. October 20, 2	2020-10-20
Fin-type field effect transistor with reduced fin bulge and method Grant 10,811,411 - Shu , et al. October 20, 2	2020-10-20
Resistor structure for integrated circuit, and related methods Grant 10,797,046 - Shu , et al. October 6, 2	2020-10-06
Resistor Structure For Integrated Circuit, And Related Methods App 20200312947 - Shu; Jiehui ; et al.	2020-10-01
Semiconductor Structures With A Protective Liner And Methods Of Forming The Same App 20200303247 - SHU; JIEHUI ; et al.	2020-09-24
Forming Two Portion Spacer After Metal Gate And Contact Formation, And Related Ic Structure App 20200303261 - Shen; Yanping ; et al.	2020-09-24
Electrical fuse formation during a multiple patterning process Grant 10,784,195 - Shu , et al. Sept	2020-09-22
Integrated circuit product with a multi-layer single diffusion break and methods of making such products Grant 10,777,637 - Yu , et al. Sept	2020-09-15
Integrated Circuit Product With A Multi-layer Single Diffusion Break And Methods Of Making Such Products App 20200243643 - Yu; Hong ; et al.	2020-07-30
Vertical Resistor Adjacent Inactive Gate Over Trench Isolation App 20200227404 - Zang; Hui ; et al.	2020-07-16
Method of forming semiconductor material in trenches having different widths, and related structures Grant 10,714,376 - Chang , et al.	2020-07-14
Anti-fuse with self aligned via patterning Grant 10,714,422 - Zhang , et al.	2020-07-14
Semiconductor Structure With Shaped Trench And Methods Of Forming The Same App 20200211903 - SHU; JIEHUI ; et al.	2020-07-02
Late gate cut using selective dielectric deposition Grant 10,699,957 - Zang , et al.	2020-06-30
Interconnects with variable space mandrel cuts formed by block patterning Grant 10,692,812 - Srivastava , et al.	2020-06-23
Gate structures Grant 10,685,840 - Shu , et al.	2020-06-16
Late Gate Cut Using Selective Dielectric Deposition App 20200168509 - Zang; Hui ; et al.	2020-05-28
Gate Structures App 20200161136 - SHU; Jiehui ; et al.	2020-05-21
Gate Cut Isolation Including Air Gap, Integrated Circuit Including Same And Related Method App 20200152736 - Yu; Hong ; et al.	2020-05-14
FinFET structure with bulbous upper insulative cap portion to protect gate height, and related method Grant 10,629,707 - Zang , et al.	2020-04-21
Method Of Manufacturing Finfet With Reduced Parasitic Capacitance And Finfet Structure Formed Thereby App 20200119001 - Shu; Jiehui ; et al.	2020-04-16
Anti-fuse With Self Aligned Via Patterning App 20200118927 - Zhang; Xiaoqiang ; et al.	2020-04-16
Methods Of Forming Stress Liners Using Atomic Layer Deposition To Form Gapfill Seams App 20200111704 - Kozarksy; Eric S. ; et al.	2020-04-09
Integrated circuits having converted self-aligned epitaxial etch stop Grant 10,593,757 - Shu , et al.	2020-03-17
Oxide Spacer In A Contact Over Active Gate Finfet And Method Of Production Thereof App 20200083363 - ZANG; Hui ; et al.	2020-03-12
Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process Grant 10,586,860 - Shu , et al.	2020-03-10
Oxide spacer in a contact over active gate finFET and method of production thereof Grant 10,573,753 - Zang , et al. Feb	2020-02-25
Gate structures of FinFET semiconductor devices Grant 10,566,202 - Shu , et al. Feb	2020-02-18
Multiple patterning with variable space mandrel cuts Grant 10,566,195 - Shu , et al. Feb	2020-02-18
Methods, Apparatus, And System To Control Gate Height And Cap Thickness Across Multiple Gates App 20200052106 - Economikos; Laertis ; et al.	2020-02-13
Using Source/drain Contact Cap During Gate Cut App 20200020687 - Wang; Haiting ; et al.	2020-01-16
Isolated Deposition Zones For Atomic Layer Deposition App 20200002813 - Shu; Jiehui ; et al.	2020-01-02
Using source/drain contact cap during gate cut Grant 10,522,538 - Wang , et al. Dec	2019-12-31
Method Of Forming Semiconductor Material In Trenches Having Different Widths, And Related Structures App 20190393077 - Chang; Chih-Chiang ; et al.	2019-12-26
Contact structures Grant 10,510,613 - Shu , et al. Dec	2019-12-17
Finfet Device Comprising A Single Diffusion Break With An Upper Surface That Is Substantially Coplanar With An Upper Surface Of App 20190378751 - Shu; Jiehui ; et al.	2019-12-12
Transistor Fins With Different Thickness Gate Dielectric App 20190371796 - Zang; Hui ; et al.	2019-12-05
Transistors Having Double Spacers At Tops Of Gate Conductors App 20190363174 - Zang; Hui ; et al.	2019-11-28
Finfet Structure With Bulbous Upper Insulative Cap Portion To Protect Gate Height, And Related Method App 20190363180 - Zang; Hui ; et al.	2019-11-28
Methods, Apparatus, And System For A Semiconductor Device Comprising Gates With Short Heights App 20190355615 - Shu; Jiehui ; et al.	2019-11-21
Multi-step Insulator Formation In Trenches To Avoid Seams In Insulators App 20190355624 - Sirman; Asli ; et al.	2019-11-21
Interconnects With Variable Space Mandrel Cuts Formed By Block Patterning App 20190355658 - Srivastava; Ravi Prakash ; et al.	2019-11-21
Ic Product Comprising An Insulating Gate Separation Structure Positioned Between End Surfaces Of Adjacent Gate Structures App 20190355832 - Shu; Jiehui ; et al.	2019-11-21
Transistor fins with different thickness gate dielectric Grant 10,475,791 - Zang , et al. Nov	2019-11-12
Method for forming single diffusion breaks between finFET devices and the resulting devices Grant 10,475,693 - Shu , et al. Nov	2019-11-12
A Method Of Manufacturing Finfet Devices Using Narrow And Wide Gate Cut Openings In Conjuction With A Replacement Metal Gate Pro App 20190341475 - Shu; Jiehui ; et al.	2019-11-07
Integrated Circuits Having Converted Self-aligned Epitaxial Etch Stop App 20190333993 - Shu; Jiehui ; et al.	2019-10-31
Material Combinations For Polish Stops And Gate Caps App 20190326416 - Huang; Haigou ; et al.	2019-10-24
Electrical Fuse Formation During A Multiple Patterning Process App 20190326209 - Shu; Jiehui ; et al.	2019-10-24
Methods of forming replacement gate structures on transistor devices Grant 10,453,936 - Shu , et al. Oc	2019-10-22
Self-aligned Multiple Patterning Processes With Layered Mandrels App 20190318931 - Shu; Jiehui ; et al.	2019-10-17
Self-aligned multiple patterning processes with layered mandrels Grant 10,446,395 - Shu , et al. Oc	2019-10-15
Multi-step Insulator Formation In Trenches To Avoid Seams In Insulators App 20190304843 - Sirman; Asli ; et al.	2019-10-03
Multi-step insulator formation in trenches to avoid seams in insulators Grant 10,431,500 - Sirman , et al. O	2019-10-01
Methods, apparatus, and system for a semiconductor device comprising gates with short heights Grant 10,418,272 - Shu , et al. Sept	2019-09-17
Field-effect Transistors With Fins Formed By A Damascene-like Process App 20190273148 - Zhao; Wei ; et al.	2019-09-05
Field-effect transistors with fins formed by a damascene-like process Grant 10,403,742 - Zhao , et al. Sep	2019-09-03
Contact Structures App 20190229019 - Shu; Jiehui ; et al.	2019-07-25
Active gate contacts and method of fabrication thereof Grant 10,347,541 - Shu , et al. July 9, 2	2019-07-09
Cobalt Plated Via Integration Scheme App 20190206729 - FANG; Qiang ; et al.	2019-07-04
Methods, apparatus and system for self-aligned metal hard masks Grant 10,340,142 - Gao , et al.	2019-07-02
Cobalt plated via integration scheme Grant 10,340,183 - Fang , et al.	2019-07-02
Methods Of Forming Replacement Gate Structures On Transistor Devices App 20190131429 - Shu; Jiehui ; et al.	2019-05-02
Methods for forming fins Grant 10,276,374 - Shu , et al.	2019-04-30
Narrowed feature formation during a double patterning process Grant 10,249,496 - Shu , et al.	2019-04-02
Field-effect Transistors With Fins Formed By A Damascene-like Process App 20190097019 - Zhao; Wei ; et al.	2019-03-28
Methods For Forming Fins App 20190088478 - Shu; Jiehui ; et al.	2019-03-21
Gate cut structure with liner spacer and related method Grant 10,236,213 - Pandey , et al.	2019-03-19
Methods of forming upper source/drain regions on a vertical transistor device Grant 10,229,999 - Wu , et al.	2019-03-12
Multiple Patterning With Variable Space Mandrel Cuts App 20190067010 - Shu; Jiehui ; et al.	2019-02-28
Vertical field effect transistor formation with critical dimension control Grant 10,217,846 - Xie , et al. Feb	2019-02-26
Variable space mandrel cut for self aligned double patterning Grant 10,199,265 - Shu , et al. Fe	2019-02-05
Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks Grant 10,192,780 - Wang , et al. Ja	2019-01-29
Semiconductor devices with robust low-k sidewall spacers and method for producing the same Grant 10,192,791 - Gu , et al. Ja	2019-01-29
Shallow Trench Isolation (sti) Gap Fill App 20190027556 - Shu; Jiehui ; et al.	2019-01-24
Semiconductor Structure App 20180350607 - SHU; Jiehui ; et al.	2018-12-06
Narrowed Feature Formation During A Double Patterning Process App 20180323067 - Shu; Jiehui ; et al.	2018-11-08
Method to prevent cobalt recess Grant 10,109,521 - Fang , et al. October 23, 2	2018-10-23
Methods Of Forming Upper Source/drain Regions On A Vertical Transistor Device App 20180248046 - Wu; Xusheng ; et al.	2018-08-30
Variable Space Mandrel Cut For Self Aligned Double Patterning App 20180233404 - SHU; Jiehui ; et al.	2018-08-16
Sub-fin doping method Grant 10,002,793 - Shu , et al. June 19, 2	2018-06-19
Silicon liner for STI CMP stop in FinFET Grant 9,984,933 - Xu , et al. May 29, 2	2018-05-29
Methods for nitride planarization using dielectric Grant 9,966,272 - Sheng , et al. May 8, 2	2018-05-08
Notched Fin Structures And Methods Of Manufacture App 20180108732 - Shu; Jiehui ; et al.	2018-04-19
Silicon nitride CESL removal without gate cap height loss and resulting device Grant 9,905,472 - Shu , et al. February 27, 2	2018-02-27
Devices And Methods Of Forming Sadp On Sram And Saqp On Logic App 20180012760 - SHU; Jiehui ; et al.	2018-01-11
Interconnects With Inner Sacrificial Spacers App 20180012791 - Sun; Zhiguo ; et al.	2018-01-11
Nanowire transistors having multiple threshold voltages Grant 9,865,681 - Wu , et al. January 9, 2	2018-01-09
Devices and methods of forming SADP on SRAM and SAQP on logic Grant 9,761,452 - Shu , et al. September 12, 2	2017-09-12
Sacrificial amorphous silicon hard mask for BEOL Grant 9,741,610 - Fang , et al. August 22, 2	2017-08-22
Self-aligned lithographic patterning with variable spacings Grant 9,711,447 - Shu , et al. July 18, 2	2017-07-18
Advanced self-aligned patterning process with sit spacer as a final dielectric etch hardmask Grant 9,704,746 - Shu , et al. July 11, 2	2017-07-11
Reducing liner corrosion during metallization of semiconductor devices Grant 9,595,493 - Sun , et al. March 14, 2	2017-03-14
Reducing Liner Corrosion During Metallization Of Semiconductor Devices App 20170047282 - SUN; Zhiguo ; et al.	2017-02-16
Sacrificial Amorphous Silicon Hard Mask For Beol App 20160365277 - FANG; Qiang ; et al.	2016-12-15
Method to improve selectivity cobalt cap process Grant 9,275,898 - Shu , et al. March 1, 2	2016-03-01
Reduced Silicon Gouging During Oxide Spacer Formation App 20150325445 - SHU; Jiehui ; et al.	2015-11-12