name:-0.11510491371155
name:-0.10742115974426
name:-0.045108079910278
Liu; Jinping Patent Filings

Liu; Jinping

Patent Applications and Registrations

Patent applications and USPTO patent grants for Liu; Jinping.The latest application filed is for "large-scale axle intelligent cross wedge rolling mill for rail transit".

Company Profile
39.104.102
  • Liu; Jinping - Ballston Lake NY
  • Liu; Jinping - Taiyuan CN
  • Liu; Jinping - Shanghai CN
  • Liu; Jinping - Nanjing CN
  • LIU; Jinping - Beijing CN
  • Liu; Jinping - Shenzhen Guangdong
  • Liu; Jinping - Zhaoqing CN
  • Liu; Jinping - Clifton Park NY
  • Liu; Jinping - Jiangsu CN
  • LIU; JINPING - ZHAOQING CITY CN
  • Liu; Jinping - Ballstone Lake NY
  • Liu; Jinping - Hopewell Junction NY
  • Liu; Jinping - Singapore N/A SG
  • Liu; Jinping - Chengdu CN
  • Liu; Jinping - Beacon NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks
Patent Activity
PatentDate
Transistor comprising an air gap positioned adjacent a gate electrode
Grant 11,456,382 - Economikos , et al. September 27, 2
2022-09-27
Electrical fuse formation during a multiple patterning process
Grant 11,348,870 - Shu , et al. May 31, 2
2022-05-31
Large-scale axle intelligent cross wedge rolling mill for rail transit
App 20220136558 - Chu; Zhibing ;   et al.
2022-05-05
Miniature Step Motor With Shoeless Stator And Prewound Bobbins
App 20220069687 - Lin; Ted T. ;   et al.
2022-03-03
FinFET device comprising a single diffusion break with an upper surface that is substantially coplanar with an upper surface of a fin
Grant 11,121,023 - Shu , et al. September 14, 2
2021-09-14
Systems And Methods For Intelligent Application Instantiation
App 20210103447 - Wei; Daowen ;   et al.
2021-04-08
Multi-step insulator formation in trenches to avoid seams in insulators
Grant 10,964,599 - Sirman , et al. March 30, 2
2021-03-30
Device with large EPI in FinFETs and method of manufacturing
Grant 10,910,471 - Peng , et al. February 2, 2
2021-02-02
Device And Method For Forming Shaft Part By Two-roller Flexible Skew Rolling
App 20200346262 - WANG; Baoyu ;   et al.
2020-11-05
Electrical Fuse Formation During A Multiple Patterning Process
App 20200335435 - Shu; Jiehui ;   et al.
2020-10-22
Electrical fuse formation during a multiple patterning process
Grant 10,784,195 - Shu , et al. Sept
2020-09-22
Method of forming semiconductor material in trenches having different widths, and related structures
Grant 10,714,376 - Chang , et al.
2020-07-14
Method, apparatus and system for improved performance using tall fins in finFET devices
Grant 10,622,463 - Zang , et al.
2020-04-14
Methods Of Forming Stress Liners Using Atomic Layer Deposition To Form Gapfill Seams
App 20200111704 - Kozarksy; Eric S. ;   et al.
2020-04-09
Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process
Grant 10,586,860 - Shu , et al.
2020-03-10
Transistor Comprising An Air Gap Positioned Adjacent A Gate Electrode
App 20200066899 - Economikos; Laertis ;   et al.
2020-02-27
Multiple patterning with variable space mandrel cuts
Grant 10,566,195 - Shu , et al. Feb
2020-02-18
Capping structure
Grant 10,559,470 - Huang , et al. Feb
2020-02-11
Device With Large Epi In Finfets And Method Of Manufacturing
App 20200020769 - PENG; Jianwei ;   et al.
2020-01-16
Method for forming replacement air gap
Grant 10,535,771 - Economikos , et al. Ja
2020-01-14
Isolated Deposition Zones For Atomic Layer Deposition
App 20200002813 - Shu; Jiehui ;   et al.
2020-01-02
Method Of Forming Semiconductor Material In Trenches Having Different Widths, And Related Structures
App 20190393077 - Chang; Chih-Chiang ;   et al.
2019-12-26
Method For Forming Replacement Air Gap
App 20190393335 - Economikos; Laertis ;   et al.
2019-12-26
Finfet Device Comprising A Single Diffusion Break With An Upper Surface That Is Substantially Coplanar With An Upper Surface Of
App 20190378751 - Shu; Jiehui ;   et al.
2019-12-12
Ic Product Comprising An Insulating Gate Separation Structure Positioned Between End Surfaces Of Adjacent Gate Structures
App 20190355832 - Shu; Jiehui ;   et al.
2019-11-21
Multi-step Insulator Formation In Trenches To Avoid Seams In Insulators
App 20190355624 - Sirman; Asli ;   et al.
2019-11-21
Methods, Apparatus, And System For A Semiconductor Device Comprising Gates With Short Heights
App 20190355615 - Shu; Jiehui ;   et al.
2019-11-21
Method for forming single diffusion breaks between finFET devices and the resulting devices
Grant 10,475,693 - Shu , et al. Nov
2019-11-12
A Method Of Manufacturing Finfet Devices Using Narrow And Wide Gate Cut Openings In Conjuction With A Replacement Metal Gate Pro
App 20190341475 - Shu; Jiehui ;   et al.
2019-11-07
Electrical Fuse Formation During A Multiple Patterning Process
App 20190326209 - Shu; Jiehui ;   et al.
2019-10-24
Methods of forming replacement gate structures on transistor devices
Grant 10,453,936 - Shu , et al. Oc
2019-10-22
Self-aligned Multiple Patterning Processes With Layered Mandrels
App 20190318931 - Shu; Jiehui ;   et al.
2019-10-17
Self-aligned multiple patterning processes with layered mandrels
Grant 10,446,395 - Shu , et al. Oc
2019-10-15
Gate Skirt Oxidation For Improved Finfet Performance And Method For Producing The Same
App 20190305105 - GAO; Qun ;   et al.
2019-10-03
Multi-step Insulator Formation In Trenches To Avoid Seams In Insulators
App 20190304843 - Sirman; Asli ;   et al.
2019-10-03
Multi-step insulator formation in trenches to avoid seams in insulators
Grant 10,431,500 - Sirman , et al. O
2019-10-01
Multiple-layer spacers for field-effect transistors
Grant 10,431,665 - Han , et al. O
2019-10-01
Methods, apparatus, and system for a semiconductor device comprising gates with short heights
Grant 10,418,272 - Shu , et al. Sept
2019-09-17
Field-effect Transistors With Fins Formed By A Damascene-like Process
App 20190273148 - Zhao; Wei ;   et al.
2019-09-05
Field-effect transistors with fins formed by a damascene-like process
Grant 10,403,742 - Zhao , et al. Sep
2019-09-03
Capping Structure
App 20190228976 - HUANG; Haigou ;   et al.
2019-07-25
Method, Apparatus, And Server For Rendering A Cell Page, And Readable Storage Medium
App 20190228062 - Wu; Qinglin ;   et al.
2019-07-25
Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same
Grant 10,361,289 - Zhao , et al.
2019-07-23
Active gate contacts and method of fabrication thereof
Grant 10,347,541 - Shu , et al. July 9, 2
2019-07-09
Methods, apparatus and system for self-aligned metal hard masks
Grant 10,340,142 - Gao , et al.
2019-07-02
Protected trench isolation for fin-type field-effect transistors
Grant 10,312,150 - Al-Amoody , et al.
2019-06-04
Precision forming method of high-efficiency and near-net hollow valve blank of engine
Grant 10,279,440 - Liu , et al.
2019-05-07
Methods Of Forming Replacement Gate Structures On Transistor Devices
App 20190131429 - Shu; Jiehui ;   et al.
2019-05-02
Methods for forming fins
Grant 10,276,374 - Shu , et al.
2019-04-30
Common metal contact regions having different Schottky barrier heights and methods of manufacturing same
Grant 10,276,683 - Lee , et al.
2019-04-30
Field-effect Transistors With Fins Formed By A Damascene-like Process
App 20190097019 - Zhao; Wei ;   et al.
2019-03-28
Methods For Forming Fins
App 20190088478 - Shu; Jiehui ;   et al.
2019-03-21
Multiple Patterning With Variable Space Mandrel Cuts
App 20190067010 - Shu; Jiehui ;   et al.
2019-02-28
Method, Apparatus And System For Improved Performance Using Tall Fins In Finfet Devices
App 20190043965 - Zang; Hui ;   et al.
2019-02-07
Variable space mandrel cut for self aligned double patterning
Grant 10,199,265 - Shu , et al. Fe
2019-02-05
Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks
Grant 10,192,780 - Wang , et al. Ja
2019-01-29
Semiconductor devices with robust low-k sidewall spacers and method for producing the same
Grant 10,192,791 - Gu , et al. Ja
2019-01-29
Process for variable fin pitch and critical dimension
Grant 10,192,786 - Zang , et al. Ja
2019-01-29
Shallow Trench Isolation (sti) Gap Fill
App 20190027556 - Shu; Jiehui ;   et al.
2019-01-24
Semiconductor Structure
App 20180350607 - SHU; Jiehui ;   et al.
2018-12-06
Process For Variable Fin Pitch And Critical Dimension
App 20180330994 - ZANG; Hui ;   et al.
2018-11-15
Method, apparatus and system for improved performance using tall fins in finFET devices
Grant 10,115,807 - Zang , et al. October 30, 2
2018-10-30
Field Effect Transistors With Reduced Parasitic Resistances And Method
App 20180247936 - RAY; SHISHIR K. ;   et al.
2018-08-30
Field effect transistors with reduced parasitic resistances and method
Grant 10,062,692 - Ray , et al. August 28, 2
2018-08-28
Siloxane and organic-based MOL contact patterning
Grant 10,056,458 - Maeng , et al. August 21, 2
2018-08-21
Variable Space Mandrel Cut For Self Aligned Double Patterning
App 20180233404 - SHU; Jiehui ;   et al.
2018-08-16
Fabrication of multi threshold-voltage devices
Grant 10,020,202 - Kang , et al. July 10, 2
2018-07-10
Laminated spacers for field-effect transistors
Grant 10,008,456 - Han , et al. June 26, 2
2018-06-26
Sub-fin doping method
Grant 10,002,793 - Shu , et al. June 19, 2
2018-06-19
Contact etch stop layer with sacrificial polysilicon layer
Grant 9,991,363 - Huang , et al. June 5, 2
2018-06-05
Multiple-layer Spacers For Field-effect Transistors
App 20180151690 - Han; Tao ;   et al.
2018-05-31
Silicon liner for STI CMP stop in FinFET
Grant 9,984,933 - Xu , et al. May 29, 2
2018-05-29
Preparation method for revaprazan hydrochloride
Grant 9,981,917 - Liu , et al. May 29, 2
2018-05-29
Formation Of Band-edge Contacts
App 20180138177 - LEE; Tek Po Rinus ;   et al.
2018-05-17
FORMING DEFECT-FREE RELAXED SiGe FINS
App 20180130656 - Holt; Judson Robert ;   et al.
2018-05-10
Methods for nitride planarization using dielectric
Grant 9,966,272 - Sheng , et al. May 8, 2
2018-05-08
Notched Fin Structures And Methods Of Manufacture
App 20180108732 - Shu; Jiehui ;   et al.
2018-04-19
Precision Forming Method Of High-efficiency And Near-net Hollow Valve Blank Of Engine
App 20180104776 - LIU; JINPING ;   et al.
2018-04-19
Multiple-layer spacers for field-effect transistors
Grant 9,947,769 - Han , et al. April 17, 2
2018-04-17
Silicon nitride CESL removal without gate cap height loss and resulting device
Grant 9,905,472 - Shu , et al. February 27, 2
2018-02-27
Forming defect-free relaxed SiGe fins
Grant 9,882,052 - Holt , et al. January 30, 2
2018-01-30
Common Metal Contact Regions Having Different Schottky Barrier Heights And Methods Of Manufacturing Same
App 20180019313 - LEE; Tek Po Rinus ;   et al.
2018-01-18
Devices And Methods Of Forming Sadp On Sram And Saqp On Logic
App 20180012760 - SHU; Jiehui ;   et al.
2018-01-11
Forming Defect-free Relaxed Sige Fins
App 20180006155 - HOLT; Robert Judson ;   et al.
2018-01-04
Controlling Within-die Uniformity Using Doped Polishing Material
App 20170338226 - Huang; Haigou ;   et al.
2017-11-23
Apparatus And Method Of Adjusting Work-function Metal Thickness To Provide Variable Threshold Voltages In Finfets
App 20170338156 - ZANG; Hui ;   et al.
2017-11-23
Common metal contact regions having different Schottky barrier heights and methods of manufacturing same
Grant 9,812,543 - Lee , et al. November 7, 2
2017-11-07
Apparatus and method of adjusting work-function metal thickness to provide variable threshold voltages in finFETs
Grant 9,805,982 - Zang , et al. October 31, 2
2017-10-31
Fabrication Of Multi Threshold-voltage Devices
App 20170301551 - KANG; Donghun ;   et al.
2017-10-19
Advanced method for scaled SRAM with flexible active pitch
Grant 9,773,680 - Zang , et al. September 26, 2
2017-09-26
Preparation Method For Revaprazan Hydrochloride
App 20170267646 - Liu; Wenzheng ;   et al.
2017-09-21
Devices and methods of forming SADP on SRAM and SAQP on logic
Grant 9,761,452 - Shu , et al. September 12, 2
2017-09-12
Common Metal Contact Regions Having Different Schottky Barrier Heights And Methods Of Manufacturing Same
App 20170256624 - LEE; Tek Po Rinus ;   et al.
2017-09-07
Controlling within-die uniformity using doped polishing material
Grant 9,754,837 - Huang , et al. September 5, 2
2017-09-05
Self-aligned lithographic patterning with variable spacings
Grant 9,711,447 - Shu , et al. July 18, 2
2017-07-18
Siloxane And Organic-based Mol Contact Patterning
App 20170200792 - MAENG; Chang Ho ;   et al.
2017-07-13
Advanced self-aligned patterning process with sit spacer as a final dielectric etch hardmask
Grant 9,704,746 - Shu , et al. July 11, 2
2017-07-11
Introducing self-aligned dopants in semiconductor fins
Grant 9,698,018 - Dai , et al. July 4, 2
2017-07-04
Methods of forming spacers on FinFET devices
Grant 9,673,301 - Al-Amoody , et al. June 6, 2
2017-06-06
Method, Apparatus And System For Improved Performance Using Tall Fins In Finfet Devices
App 20170141214 - Zang; Hui ;   et al.
2017-05-18
Integrated circuits and methods for their fabrication
Grant 9,640,423 - Krishnan , et al. May 2, 2
2017-05-02
Methods of forming self-aligned contacts on FinFET devices
Grant 9,627,274 - Sheng , et al. April 18, 2
2017-04-18
Method of adjusting spacer thickness to provide variable threshold voltages in FinFETs
Grant 9,620,425 - Zang , et al. April 11, 2
2017-04-11
Method for eliminating interlayer dielectric dishing and controlling gate height uniformity
Grant 9,589,807 - Huang , et al. March 7, 2
2017-03-07
Methods of forming fins with different fin heights
Grant 9,577,066 - Al-Amoody , et al. February 21, 2
2017-02-21
Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors
Grant 9,570,552 - Lee , et al. February 14, 2
2017-02-14
Integrated Circuits And Methods For Their Fabrication
App 20170033178 - Krishnan; Bharat ;   et al.
2017-02-02
Method For Improved Fin Profile
App 20170033224 - LICAUSI; Nicholas Vincent ;   et al.
2017-02-02
Method for improved fin profile
Grant 9,553,194 - Licausi , et al. January 24, 2
2017-01-24
Wrap-around contact for finFET
Grant 9,478,622 - Yu , et al. October 25, 2
2016-10-25
10 nm alternative N/P doped fin for SSRW scheme
Grant 9,455,204 - Cao , et al. September 27, 2
2016-09-27
Gate structures for transistor devices for CMOS applications and products
Grant 9,362,283 - Hong , et al. June 7, 2
2016-06-07
Semiconductor device with diffusion barrier film and method of manufacturing the same
Grant 9,330,982 - Cao , et al. May 3, 2
2016-05-03
Integrated circuits having finFETs with improved doped channel regions and methods for fabricating same
Grant 9,287,180 - Liu , et al. March 15, 2
2016-03-15
Semiconductor device including graded gate stack, related method and design structure
Grant 9,257,519 - Chudzik , et al. February 9, 2
2016-02-09
Semiconductor Structure With Increased Space And Volume Between Shaped Epitaxial Structures
App 20160005657 - KRISHNAN; Bharat ;   et al.
2016-01-07
Method To Form Wrap-around Contact For Finfet
App 20150380502 - Yu; Hong ;   et al.
2015-12-31
Methods Of Forming Gate Structures For Transistor Devices For Cmos Applications And The Resulting Products
App 20150311206 - Hong; Zhendong ;   et al.
2015-10-29
Self-aligned Contact Openings Over Fins Of A Semiconductor Device
App 20150303295 - Wan; Jing ;   et al.
2015-10-22
Semiconductor structure with increased space and volume between shaped epitaxial structures
Grant 9,165,767 - Krishnan , et al. October 20, 2
2015-10-20
Integrated Circuits Having Finfets With Improved Doped Channel Regions And Methods For Fabricating Same
App 20150294915 - Liu; Jinping ;   et al.
2015-10-15
Method to form wrap-around contact for finFET
Grant 9,159,794 - Yu , et al. October 13, 2
2015-10-13
Forming Source/drain Regions With Single Reticle And Resulting Device
App 20150255353 - WAN; Jing ;   et al.
2015-09-10
Methods of forming gate structures for transistor devices for CMOS applications
Grant 9,105,497 - Hong , et al. August 11, 2
2015-08-11
Method of manufacturing scaled equivalent oxide thickness gate stacks in semiconductor devices and related design structure
Grant 9,099,461 - Chudzik , et al. August 4, 2
2015-08-04
Dopant Diffusion Barrier To Form Isolated Source/drains In A Semiconductor Device
App 20150214345 - Wan; Jing ;   et al.
2015-07-30
Methods Of Forming Epitaxial Semiconductor Material On Source/drain Regions Of A Finfet Semiconductor Device And The Resulting Devices
App 20150214369 - Fronheiser; Jody A. ;   et al.
2015-07-30
Integrated circuits having FinFETs with improved doped channel regions and methods for fabricating same
Grant 9,093,476 - Liu , et al. July 28, 2
2015-07-28
Method To Form Wrap-around Contact For Finfet
App 20150200260 - Yu; Hong ;   et al.
2015-07-16
Reducing gate expansion after source and drain implant in gate last process
Grant 9,059,218 - Krishnan , et al. June 16, 2
2015-06-16
Concurrently forming nFET and pFET gate dielectric layers
Grant 9,059,315 - Ando , et al. June 16, 2
2015-06-16
Method for forming fully relaxed silicon germanium on silicon
Grant 9,048,129 - Liu June 2, 2
2015-06-02
Composite high-k gate dielectric stack for reducing gate leakage
Grant 9,029,959 - Brodsky , et al. May 12, 2
2015-05-12
Increased Space Between Epitaxy On Adjacent Fins Of Finfet
App 20150123146 - KRISHNAN; Bharat ;   et al.
2015-05-07
Reducing Gate Expansion After Source And Drain Implant In Gate Last Process
App 20150076622 - Krishnan; Bharat ;   et al.
2015-03-19
Methods Of Forming Gate Structures For Transistor Devices For Cmos Applications And The Resulting Products
App 20150061027 - Hong; Zhendong ;   et al.
2015-03-05
Integrated Circuits Having Finfets With Improved Doped Channel Regions And Methods For Fabricating Same
App 20150035062 - LIU; Jinping ;   et al.
2015-02-05
Method and apparatus for adjusting threshold voltage in a replacement metal gate integration
Grant 8,912,085 - Lee , et al. December 16, 2
2014-12-16
Method of manufacturing semiconductor devices including replacement metal gate process incorporating a conductive dummy gate layer
Grant 8,835,292 - Chudzik , et al. September 16, 2
2014-09-16
Transistor with reduced parasitic capacitance
Grant 8,809,962 - Liu , et al. August 19, 2
2014-08-19
Concurrently Forming nFET and pFET Gate Dielectric Layers
App 20140187028 - Ando; Takashi ;   et al.
2014-07-03
Method And Structure For Transistor With Reduced Drain-induced Barrier Lowering And On Resistance
App 20140159052 - Liu; Jinping ;   et al.
2014-06-12
Method for fabricating a semiconductor device having an epitaxial channel and transistor having same
Grant 8,716,076 - Liu , et al. May 6, 2
2014-05-06
Method Of Manufacturing Semiconductor Devices Including Replacement Metal Gate Process Incorporating A Conductive Dummy Gate Layer
App 20140120708 - Chudzik; Michael P. ;   et al.
2014-05-01
Semiconductor Device Including Graded Gate Stack, Related Method And Design Structure
App 20140070334 - Chudzik; Michael P. ;   et al.
2014-03-13
Method for forming N-shaped bottom stress liner
Grant 8,669,616 - Yang , et al. March 11, 2
2014-03-11
Methods for fabricating a FINFET integrated circuit on a bulk silicon substrate
Grant 8,637,372 - Liu , et al. January 28, 2
2014-01-28
Method For Forming N-shaped Bottom Stress Liner
App 20140015020 - YANG; Xiaodong ;   et al.
2014-01-16
Composite High-k Gate Dielectric Stack For Reducing Gate Leakage
App 20140001570 - Brodsky; MaryJane ;   et al.
2014-01-02
Method Of Manufacturing Scaled Equivalent Oxide Thickness Gate Stacks In Semiconductor Devices And Related Design Structure
App 20130330843 - Chudzik; Michael P. ;   et al.
2013-12-12
Semiconductor Device Including Graded Gate Stack, Related Method And Design Structure
App 20130277765 - Chudzik; Michael P. ;   et al.
2013-10-24
Method for forming N-shaped bottom stress liner
Grant 8,557,668 - Yang , et al. October 15, 2
2013-10-15
Integrated circuit and method of fabrication thereof
Grant 8,546,873 - Liu , et al. October 1, 2
2013-10-01
Fabrication of silicon oxide and oxynitride having sub-nanometer thickness
Grant 8,492,290 - Chudzik , et al. July 23, 2
2013-07-23
Method For Forming N-shaped Bottom Stress Liner
App 20130181260 - Yang; Xiaodong ;   et al.
2013-07-18
Hybrid Nanostructure, A Method For Forming The Hybrid Nanostructure, And An Electrode Including A Plurality Of The Hybrid Nanostructures
App 20130115453 - Fan; Hongjin ;   et al.
2013-05-09
Methods for reducing loading effects during film formation
Grant 8,415,236 - Chew , et al. April 9, 2
2013-04-09
Method For Forming N-type And P-type Metal-oxide-semiconductor Gates Separately
App 20130082332 - Liu; Jinping ;   et al.
2013-04-04
Transistor With Reduced Parasitic Capacitance
App 20130049142 - Liu; Yanxiang ;   et al.
2013-02-28
Methods For Fabricating A Finfet Integrated Circuit On A Bulk Silicon Substrate
App 20130005103 - Liu; Yanxiang ;   et al.
2013-01-03
Fabrication Of Silicon Oxide And Oxynitride Having Sub-nanometer Thickness
App 20120329230 - Chudzik; Michael P. ;   et al.
2012-12-27
Method For Forming Fully Relaxed Silicon Germanium On Silicon
App 20120299155 - Liu; Jinping
2012-11-29
Integrated Circuit And Method Of Fabrication Thereof
App 20120012940 - LIU; Jinping ;   et al.
2012-01-19
Low-power numerically controlled contactor and control system made of the contactors
Grant 8,093,969 - Liu , et al. January 10, 2
2012-01-10
Method For Fabricating A Semiconductor Device Having An Epitaxial Channel And Transistor Having Same
App 20110281410 - LIU; JINPING ;   et al.
2011-11-17
Integrated circuit and method of fabrication thereof
Grant 8,058,123 - Liu , et al. November 15, 2
2011-11-15
Method for fabricating a semiconductor device having an epitaxial channel and transistor having same
Grant 8,012,839 - Liu , et al. September 6, 2
2011-09-06
Method of fabricating a nitrogenated silicon oxide layer and MOS device having same
Grant 7,928,020 - Liu , et al. April 19, 2
2011-04-19
Methods For Reducing Loading Effects During Film Formation
App 20100167505 - CHEW; Han Guan ;   et al.
2010-07-01
High Stress Film
App 20100096695 - Chew; Han Guan ;   et al.
2010-04-22
Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement
App 20090315115 - Zhang; Beichao ;   et al.
2009-12-24
Method For Fabricating A Semiconductor Device Having An Epitaxial Channel And Transistor Having Same
App 20090218597 - Liu; Jinping ;   et al.
2009-09-03
Integrated Circuit And Method Of Fabrication Thereof
App 20090140292 - LIU; Jinping ;   et al.
2009-06-04
Method Of Fabricating A Nitrogenated Silicon Oxide Layer And Mos Device Having Same
App 20090088002 - Liu; Jinping ;   et al.
2009-04-02
Method For Fabricating A Semiconductor Structure Having Heterogeneous Crystalline Orientations
App 20090053864 - Liu; Jinping ;   et al.
2009-02-26
Pyrazolopyrimidinone Derivatives, Their Preparation And Their Use
App 20080318949 - Tian; Guanghui ;   et al.
2008-12-25
Low-Power Numerically Controlled Contactor and Control System Made of the Contactors
App 20080238594 - Liu; Jinping ;   et al.
2008-10-02
End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping
Grant 7,400,018 - Tan , et al. July 15, 2
2008-07-15
Implantation-less approach to fabricating strained semiconductor on isolation wafers
Grant 7,338,886 - Liu , et al. March 4, 2
2008-03-04
Method of manufacturing a semiconductor device with a strained channel
Grant 7,238,581 - Chui , et al. July 3, 2
2007-07-03
Material Architecture For The Fabrication Of Low Temperature Transistor
App 20070117326 - Tan; Chung Foong ;   et al.
2007-05-24
Method of forming ultra thin silicon oxynitride for gate dielectric applications
Grant 7,202,164 - Liu , et al. April 10, 2
2007-04-10
Material architecture for the fabrication of low temperature transistor
Grant 7,169,675 - Tan , et al. January 30, 2
2007-01-30
End Of Range (eor) Secondary Defect Engineering Using Chemical Vapor Deposition (cvd) Substitutional Carbon Doping
App 20060270168 - Tan; Chung Foong ;   et al.
2006-11-30
Implantation-less approach to fabricating strained semiconductor on isolation wafers
App 20060234479 - Liu; Jinping ;   et al.
2006-10-19
End of range (EOR) secondary defect engineering using substitutional carbon doping
Grant 7,109,099 - Tan , et al. September 19, 2
2006-09-19
Method of forming ultra thin silicon oxynitride for gate dielectric applications
App 20060110865 - Liu; Jinping ;   et al.
2006-05-25
Method of manufacturing a semiconductor device with a strained channel
App 20060030094 - Chui; King Jien ;   et al.
2006-02-09
Material architecture for the fabrication of low temperature transistor
App 20060006427 - Tan; Chung Foong ;   et al.
2006-01-12
End of range (EOR) secondary defect engineering using substitutional carbon doping
App 20050085055 - Tan, Chung Foong ;   et al.
2005-04-21
Company Registrations
SEC0001380316Liu Jinping

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed