Chang; Chang-Yun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chang; Chang-Yun.The latest application filed is for "sram structure and method for forming the same".

Company Profile

25.83.79

Chang; Chang-Yun - Taipei TW
CHANG; Chang-Yun - Taipei City TW
Chang; Chang-Yun - Hsin-Chu TW
Chang; Chang-Yun - Taipai TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for forming semiconductor device Grant 11,437,278 - Chang , et al. September 6, 2	2022-09-06
Sram Structure And Method For Forming The Same App 20220254789 - WEN; MING-CHANG ; et al.	2022-08-11
Methods for manufacturing a transistor gate by non-directional implantation of impurities in a gate spacer Grant 11,398,384 - Peng , et al. July 26, 2	2022-07-26
Structure And Method For Providing Line End Extensions For Fin-type Active Regions App 20220223727 - YU; Shao-Ming ; et al.	2022-07-14
Cut Metal Gate Process For Reducing Transistor Spacing App 20220157595 - Wen; Ming-Chang ; et al.	2022-05-19
SRAM structure and method for forming the same Grant 11,315,933 - Wen , et al. April 26, 2	2022-04-26
Profile Control Of A Gap Fill Structure App 20220077001 - WU; Wan-Yao ; et al.	2022-03-10
Structure and method for providing line end extensions for fin-type active regions Grant 11,239,365 - Yu , et al. February 1, 2	2022-02-01
Cut metal gate process for reducing transistor spacing Grant 11,239,072 - Wen , et al. February 1, 2	2022-02-01
Profile control of a gap fill structure Grant 11,177,180 - Wu , et al. November 16, 2	2021-11-16
Fin structure of fin field effect transistor Grant 11,158,725 - Yuan , et al. October 26, 2	2021-10-26
Isolation Structure Having Different Distances to Adjacent FinFET Devices App 20210296484 - Chang; Chang-Yun ; et al.	2021-09-23
Semiconductor Device and Method App 20210249271 - Peng; Yu-Jiun ; et al.	2021-08-12
Profile Control Of A Gap Fill Structure App 20210249309 - Wu; Wan-Yao ; et al.	2021-08-12
Etch Stop Layer Between Substrate and Isolation Structure App 20210242090 - Wen; Ming-Chang ; et al.	2021-08-05
Local Gate Height Tuning by Cmp And Dummy Gate Design App 20210202320 - Wen; Ming-Chang ; et al.	2021-07-01
Structure For Fringing Capacitance Control App 20210193530 - CHEN; Keng-Yao ; et al.	2021-06-24
Gate Formation Of Semiconductor Devices App 20210183713 - Syu; Chang-Jhih ; et al.	2021-06-17
Metal Gate Structure Cutting Process App 20210175126 - Wu; I-Wen ; et al.	2021-06-10
Isolation structure having different distances to adjacent FinFET devices Grant 11,031,501 - Chang , et al. June 8, 2	2021-06-08
Etch stop layer between substrate and isolation structure Grant 10,991,628 - Wen , et al. April 27, 2	2021-04-27
Etch stop layer between substrate and isolation structure Grant 10,978,351 - Wen , et al. April 13, 2	2021-04-13
Metal gate structure cutting process Grant 10,930,564 - Wu , et al. February 23, 2	2021-02-23
Creating devices with multiple threshold voltages by cut-metal-gate process Grant 10,868,003 - Wen , et al. December 15, 2	2020-12-15
Method For Forming Semiconductor Device App 20200365465 - CHANG; Chang-Yun ; et al.	2020-11-19
Semiconductor device having a metal gate and formation method thereof Grant 10,741,450 - Chang , et al. A	2020-08-11
Cut Metal Gate Process for Reducing Transistor Spacing App 20200251325 - Kind Code	2020-08-06
Structure And Method For Providing Line End Extensions For Fin-type Active Regions App 20200212217 - YU; Shao-Ming ; et al.	2020-07-02
Cut metal gate process for reducing transistor spacing Grant 10,651,030 - Wen , et al.	2020-05-12
Isolation Structure Having Different Distances to Adjacent FinFET Devices App 20200119183 - Chang; Chang-Yun ; et al.	2020-04-16
Etch Stop Layer Between Substrate and Isolation Structure App 20200091008 - Wen; Ming-Chang ; et al.	2020-03-19
Metal Gate Structure Cutting Process App 20200075421 - Wu; I-Wen ; et al.	2020-03-05
Structure and method for providing line end extensions for fin-type active regions Grant 10,573,751 - Yu , et al. Feb	2020-02-25
Creating Devices with Multiple Threshold Voltages by Cut-Metal-Gate Process App 20200058650 - Wen; Ming-Chang ; et al.	2020-02-20
Sram Structure And Method For Forming The Same App 20200006354 - WEN; MING-CHANG ; et al.	2020-01-02
Isolation structure having different distances to adjacent FinFET devices Grant 10,510,894 - Chang , et al. Dec	2019-12-17
Fin Structure Of Fin Field Effect Transistor App 20190341473 - YUAN; Feng ; et al.	2019-11-07
Creating devices with multiple threshold voltage by cut-metal-gate process Grant 10,461,078 - Wen , et al. Oc	2019-10-29
Cut Metal Gate Process for Reducing Transistor Spacing App 20190318922 - Wen; Ming-Chang ; et al.	2019-10-17
Creating Devices with Multiple Threshold Voltage by Cut-Metal-Gate Process App 20190267372 - Wen; Ming-Chang ; et al.	2019-08-29
Method of forming a fin field effect transistor comprising two etching steps to define a fin structure Grant 10,355,108 - Yuan , et al. July 16, 2	2019-07-16
Cut metal gate process for reducing transistor spacing Grant 10,319,581 - Wen , et al.	2019-06-11
Isolation Structure Having Different Distances To Adjacent Finfet Devices App 20190165155 - Chang; Chang-Yun ; et al.	2019-05-30
Cut Metal Gate Process for Reducing Transistor Spacing App 20190164741 - Wen; Ming-Chang ; et al.	2019-05-30
Semiconductor Device And Formation Method Thereof App 20190164838 - CHANG; Chang-Yun ; et al.	2019-05-30
Etch Stop Layer Between Substrate and Isolation Structure App 20190157159 - Wen; Ming-Chang ; et al.	2019-05-23
FinFET device for device characterization Grant 9,960,274 - Chen , et al. May 1, 2	2018-05-01
STI shape near fin bottom of Si fin in bulk FinFET Grant 9,953,885 - Yuan , et al. April 24, 2	2018-04-24
Memory cell layout Grant 9,941,173 - Liaw , et al. April 10, 2	2018-04-10
Structure and method for transistors with line end extension Grant 9,917,192 - Yu , et al. March 13, 2	2018-03-13
Structure And Method For Providing Line End Extensions For Fin-type Active Regions App 20170271503 - YU; Shao-Ming ; et al.	2017-09-21
FinFETs with different fin heights Grant 9,711,412 - Lee , et al. July 18, 2	2017-07-18
Structure and method for providing line end extensions for fin-type active regions Grant 9,673,328 - Yu , et al. June 6, 2	2017-06-06
Fin Structure Of Fin Field Effect Transistor App 20170117388 - YUAN; Feng ; et al.	2017-04-27
FinFET Device For Device Characterization App 20170018641 - Chen; Hao-Yu ; et al.	2017-01-19
FinFETs with Different Fin Heights App 20160358926 - Lee; Tsung-Lin ; et al.	2016-12-08
Fin structure of fin field effect transistor Grant 9,484,462 - Yuan , et al. November 1, 2	2016-11-01
Memory Cell Layout App 20160284600 - Liaw; Jhon-Jhy ; et al.	2016-09-29
FinFET for device characterization Grant 9,455,348 - Chen , et al. September 27, 2	2016-09-27
FinFETs with different fin heights Grant 9,425,102 - Lee , et al. August 23, 2	2016-08-23
Structure And Method For Transistors With Line End Extension App 20160240675 - Yu; Shao-Ming ; et al.	2016-08-18
Structure And Method For Providing Line End Extensions For Fin-type Active Regions App 20160163851 - Yu; Shao-Ming ; et al.	2016-06-09
Memory cell layout Grant 9,362,290 - Liaw , et al. June 7, 2	2016-06-07
Structure and method for transistor with line end extension Grant 9,324,866 - Yu , et al. April 26, 2	2016-04-26
Semiconductor device and method for making the same using semiconductor fin density design rules Grant 9,245,080 - Yu , et al. January 26, 2	2016-01-26
Structure And Method For Providing Line End Extensions For Fin-type Active Regions App 20150115373 - Yu; Shao-Ming ; et al.	2015-04-30
FinFETs with Different Fin Heights App 20150111355 - Lee; Tsung-Lin ; et al.	2015-04-23
FinFETs with different fin heights Grant 8,941,153 - Lee , et al. January 27, 2	2015-01-27
Semiconductor Device And Method For Making The Same Using Semiconductor Fin Density Design Rules App 20140331192 - YU; Shao-Ming ; et al.	2014-11-06
High gate density devices and methods Grant 8,871,597 - Shieh , et al. October 28, 2	2014-10-28
Fully depleted SOI multiple threshold voltage application Grant 8,865,539 - Chen , et al. October 21, 2	2014-10-21
Structure for a multiple-gate FET device and a method for its fabrication Grant RE45,180 - Chen , et al. October 7, 2	2014-10-07
Structure and method for fabricating fin devices Grant 8,847,295 - Shieh , et al. September 30, 2	2014-09-30
Forming inter-device STI regions and intra-device STI regions using different dielectric materials Grant 8,846,466 - Yuan , et al. September 30, 2	2014-09-30
Integrated circuit with multi recessed shallow trench isolation Grant 8,846,465 - Lee , et al. September 30, 2	2014-09-30
Memory cell layout Grant 8,847,361 - Liaw , et al. September 30, 2	2014-09-30
High Gate Density Devices and Methods App 20140256107 - Shieh; Ming-Feng ; et al.	2014-09-11
Semiconductor device and method for making the same using semiconductor fin density design rules Grant 8,813,014 - Yu , et al. August 19, 2	2014-08-19
Cross OD FinFET patterning Grant 8,796,156 - Shieh , et al. August 5, 2	2014-08-05
FinFETs with multiple fin heights Grant 8,748,993 - Lee , et al. June 10, 2	2014-06-10
High gate density devices and methods Grant 8,735,991 - Shieh , et al. May 27, 2	2014-05-27
Voids in STI regions for forming bulk FinFETs Grant 8,723,271 - Yuan , et al. May 13, 2	2014-05-13
Semiconductor fin device and method for forming the same using high tilt angle implant Grant 8,709,928 - Yu , et al. April 29, 2	2014-04-29
FinFETs with multiple fin heights Grant 8,673,709 - Lee , et al. March 18, 2	2014-03-18
FinFETs with Multiple Fin Heights App 20140035043 - Lee; Tsung-Lin ; et al.	2014-02-06
Forming Inter-Device STI Regions and Intra-Device STI Regions Using Different Dielectric Materials App 20140004682 - Yuan; Feng ; et al.	2014-01-02
Integrated circuit with multi recessed shallow trench isolation Grant 8,610,240 - Lee , et al. December 17, 2	2013-12-17
Structure and Method for Fabricating Fin Devices App 20130313646 - Shieh; Ming-Feng ; et al.	2013-11-28
Forming inter-device STI regions and intra-device STI regions using different dielectric materials Grant 8,592,918 - Yuan , et al. November 26, 2	2013-11-26
Voids in STI Regions for Forming Bulk FinFETs App 20130277757 - Yuan; Feng ; et al.	2013-10-24
Memory Cell Layout App 20130280903 - Liaw; Jhon-Jhy ; et al.	2013-10-24
Integrated Circuit with Multi Recessed Shallow Trench Isolation App 20130267075 - Lee; Tsung-Lin ; et al.	2013-10-10
Voids in STI regions for forming bulk FinFETs Grant 8,519,481 - Yuan , et al. August 27, 2	2013-08-27
Structure and method for fabricating fin devices Grant 8,513,078 - Shieh , et al. August 20, 2	2013-08-20
Structure And Method For Transistor With Line End Extension App 20130187237 - Yu; Shao-Ming ; et al.	2013-07-25
Integrated circuit including FINFETs and methods for forming the same Grant 8,482,073 - Chen , et al. July 9, 2	2013-07-09
Structure and Method for Fabricating Fin Devices App 20130164924 - Shieh; Ming-Feng ; et al.	2013-06-27
FinFETs with Multiple Fin Heights App 20130149826 - Lee; Tsung-Lin ; et al.	2013-06-13
High Gate Density Devices And Methods App 20130140639 - Shieh; Ming-Feng ; et al.	2013-06-06
FinFETs with multiple Fin heights Grant 8,373,238 - Lee , et al. February 12, 2	2013-02-12
Method of fabrication of a semiconductor device having reduced pitch Grant 8,241,823 - Shieh , et al. August 14, 2	2012-08-14
Integrated circuit structures with multiple FinFETs Grant 8,174,073 - Lee , et al. May 8, 2	2012-05-08
Cross OD FinFET Patterning App 20120100673 - Shieh; Ming-Feng ; et al.	2012-04-26
Cross OD FinFET patterning Grant 8,110,466 - Shieh , et al. February 7, 2	2012-02-07
Method Of Fabrication Of A Semiconductor Device Having Reduced Pitch App 20120021589 - Shieh; Ming-Feng ; et al.	2012-01-26
In-situ Spectrometry App 20120009690 - Wann; Clement Hsingjen ; et al.	2012-01-12
Inductor energy loss reduction techniques Grant 8,049,300 - Yeh , et al. November 1, 2	2011-11-01
Integrated circuit layout design Grant 8,039,179 - Shieh , et al. October 18, 2	2011-10-18
Integrated Circuit Including Finfets And Methods For Forming The Same App 20110233679 - CHEN; Hung-Ming ; et al.	2011-09-29
Fully Depleted SOI Multiple Threshold Voltage Application App 20110212579 - Chen; Hao-Yu ; et al.	2011-09-01
Memory Cell Layout App 20110195564 - Liaw; Jhon-Jhy ; et al.	2011-08-11
Semiconductor Fin Device And Method For Forming The Same Using High Tilt Angle Implant App 20110175165 - YU; Shao-Ming ; et al.	2011-07-21
Semiconductor Device And Method For Making The Same Using Semiconductor Fin Density Design Rules App 20110156148 - Yu; Shao-Ming ; et al.	2011-06-30
Integrated Circuit Layout Design App 20110151359 - Shieh; Ming-Feng ; et al.	2011-06-23
FinFETs with Multiple Fin Heights App 20110133292 - Lee; Tsung-Lin ; et al.	2011-06-09
FinFETs with Different Fin Heights App 20110121406 - Lee; Tsung-Lin ; et al.	2011-05-26
Forming Inter-Device STI Regions and Intra-Device STI Regions Using Different Dielectric Materials App 20110095372 - Yuan; Feng ; et al.	2011-04-28
Cross OD FinFET Patterning App 20110097863 - Shieh; Ming-Feng ; et al.	2011-04-28
STI Shape Near Fin Bottom of Si Fin in Bulk FinFET App 20110097889 - Yuan; Feng ; et al.	2011-04-28
Integrated Circuit with Multi Recessed Shallow Trench Isolation App 20110089526 - Lee; Tsung-Lin ; et al.	2011-04-21
Voids in STI Regions for Forming Bulk FinFETs App 20110084340 - Yuan; Feng ; et al.	2011-04-14
Fin Field Effect Transistor App 20110068405 - YUAN; Feng ; et al.	2011-03-24
Integrated circuit layout design Grant 7,862,962 - Shieh , et al. January 4, 2	2011-01-04
Integrated Circuit Layout Design App 20100183961 - Shieh; Ming-Feng ; et al.	2010-07-22
Static noise-immune SRAM cells Grant 7,511,988 - Lin , et al. March 31, 2	2009-03-31
Integrated circuit structures with multiple FinFETs App 20080296702 - Lee; Tsung-Lin ; et al.	2008-12-04
Fully Depleted SOI Multiple Threshold Voltage Application App 20080237717 - Chen; Hao-Yu ; et al.	2008-10-02
Method and structure for a 1T-RAM bit cell and macro Grant 7,425,740 - Liu , et al. September 16, 2	2008-09-16
FinFET for device characterization App 20080185650 - Chen; Hao-Yu ; et al.	2008-08-07
Fully depleted SOI multiple threshold voltage application Grant 7,382,023 - Chen , et al. June 3, 2	2008-06-03
Structure for a multiple-gate FET device and a method for its fabrication Grant 7,381,649 - Chen , et al. June 3, 2	2008-06-03
FinFET transistor device on SOI and method of fabrication Grant 7,300,837 - Chen , et al. November 27, 2	2007-11-27
Static noise-immune SRAM cells App 20070268747 - Lin; Wesley ; et al.	2007-11-22
Inductor Energy Loss Reduction Techniques App 20070246798 - Yeh; Andrew ; et al.	2007-10-25
Multiple gate field effect transistor structure Grant 7,271,448 - Hsu , et al. September 18, 2	2007-09-18
Inductor energy loss reduction techniques Grant 7,247,922 - Yeh , et al. July 24, 2	2007-07-24
Method and structure for a 1T-RAM bit cell and macro App 20070080387 - Liu; Sheng-Da ; et al.	2007-04-12
Multiple gate field effect transistor structure App 20060180854 - Hsu; Ju-Wang ; et al.	2006-08-17
Inductor energy loss reduction techniques App 20060065948 - Yeh; Andrew ; et al.	2006-03-30
FinFET transistor device on SOI and method of fabrication App 20050242395 - Chen, Hau-Yu ; et al.	2005-11-03
Fully depleted SOI multiple threshold voltage application App 20050242398 - Chen, Hao-Yu ; et al.	2005-11-03