U.S. patent number T101,804 [Application Number 06/146,909] was granted by the patent office on 1982-05-04 for integrated circuit layout utilizing separated active circuit and wiring regions. Invention is credited to John Balyoz, Algirdas J. Grwodis.

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United States Patent	T101,804
Balyoz ,   et al.	May 4, 1982

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Integrated circuit layout utilizing separated active circuit and wiring regions

Abstract

An LSI masterslice wiring technique, employing an array of elongated logic cells. A first level of metallization includes a first set of elongated, generally parallel conductors, orthogonal to the elongated logic cells and selectively contacting the cells. A second level of metal conductors, overlying and insulated from the first set, extends orthogonal to the first set, and thus parallel to the elongated logic cells. The second set includes both conductors passing over the areas of the logic cells and conductors lying between the logic cells. Conductors of the second set are selectively connected to conductors of the first set. This application has the same disclosure as that of Defensive Publication T100,501, published Apr. 7, 1981, but the abstracts are in conflict.

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Inventors:	Balyoz; John (Hopewell Junction, NY), Grwodis; Algirdas J. (Wappingers Falls, NY)
Family ID:	2171280
Appl. No.:	06/146,909
Filed:	May 5, 1980

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	9712	Feb 5, 1979
	830715	Sep 6, 1977

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Current U.S. Class:	257/211; 257/204
Current CPC Class:	H01L 23/528 (20130101); H01L 27/11801 (20130101); H01L 2924/0002 (20130101); H01L 2924/0002 (20130101); H01L 2924/00 (20130101)
Current International Class:	H01L 23/52 (20060101); H01L 23/528 (20060101); H01L 27/118 (20060101); H01L 027/04 ()

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