Balyoz; John
Patent Applications and Registrations
Patent applications and USPTO patent grants for Balyoz; John.The latest application filed is for "integrated circuit layout utilizing separated active circuit and wiring regions".
- Balyoz; John - Hopewell Junction NY
| Patent | Date |
|---|---|
| Integrated circuit layout utilizing separated active circuit and wiring regions Grant T101,804 - Balyoz , et al. May 4, 1 | 1982-05-04 |
| Master image chip organization technique or method Grant 4,295,149 - Balyoz , et al. October 13, 1 | 1981-10-13 |
| Integrated circuit layout utilizing separated active circuit and wiring regions Grant T100,501 - Balyoz , et al. April 7, 1 | 1981-04-07 |
| LSI Semiconductor device and fabrication thereof Grant 4,249,193 - Balyoz , et al. February 3, 1 | 1981-02-03 |
| High density semiconductor integrated circuit layout Grant 4,032,962 - Balyoz , et al. June 28, 1 | 1977-06-28 |
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