U.S. patent number RE47,709 [Application Number 15/336,265] was granted by the patent office on 2019-11-05 for forming grounded through-silicon vias in a semiconductor substrate.
This patent grant is currently assigned to Taiwan Semiconductor Manufacturing Company, Ltd.. The grantee listed for this patent is Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Shang-Yun Hou, Chi-Chun Hsieh, Hsien-Pin Hu, Shin-Puu Jeng, Wei-Cheng Wu, Hsiao-Tsung Yen.
United States Patent |
RE47,709 |
Hsieh , et al. |
November 5, 2019 |
Forming grounded through-silicon vias in a semiconductor
substrate
Abstract
A method of forming an interposer includes providing a
semiconductor substrate, the semiconductor substrate having a front
surface and a back surface opposite the front surface; forming one
or more through-silicon vias (TSVs) extending from the front
surface into the semiconductor substrate; forming an inter-layer
dielectric (ILD) layer overlying the front surface of the
semiconductor substrate and the one or more TSVs; and forming an
interconnect structure in the ILD layer, the interconnect structure
electrically connecting the one or more TSVs to the semiconductor
substrate.
Inventors: |
Hsieh; Chi-Chun (Taipei,
TW), Wu; Wei-Cheng (Hsin-Chu, TW), Yen;
Hsiao-Tsung (Tainan, TW), Hu; Hsien-Pin (Zhubei,
TW), Hou; Shang-Yun (Jubei, TW), Jeng;
Shin-Puu (Hsin-Chu, TW) |
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Hsin-Chu |
N/A |
TW |
|
|
Assignee: |
Taiwan Semiconductor Manufacturing
Company, Ltd. (Hsinchu, TW)
|
Family
ID: |
47438169 |
Appl.
No.: |
15/336,265 |
Filed: |
October 27, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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Reissue of: |
13178079 |
Jul 7, 2011 |
8872345 |
Oct 28, 2014 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
23/481 (20130101); H01L 23/481 (20130101); H01L
23/535 (20130101); H01L 21/743 (20130101); H01L
2924/0002 (20130101); H01L 21/743 (20130101); H01L
2924/0002 (20130101); H01L 2924/0002 (20130101); H01L
2924/0002 (20130101); H01L 2924/00012 (20130101); H01L
2924/00012 (20130101); H01L 2924/0002 (20130101); H01L
2924/0002 (20130101); H01L 2924/00 (20130101); H01L
2924/00 (20130101) |
Current International
Class: |
H01L
21/283 (20060101); H01L 23/48 (20060101); H01L
21/74 (20060101) |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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2005243689 |
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Sep 2005 |
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JP |
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2005243689 |
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Sep 2005 |
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JP |
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Primary Examiner: Vincent; Sean E
Attorney, Agent or Firm: Slater Matsil, LLP
Claims
What is claimed is:
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, the semiconductor substrate
having a first side and a second side opposite the first side;
forming a through-silicon via (TSV) opening extending from the
first side of the semiconductor substrate into the semiconductor
substrate; forming a liner layer on the first side of the
semiconductor substrate and along the sidewalls and bottom of the
TSV opening; depositing a first conductive material layer over the
liner layer in the opening to form a TSV; forming an inter-layer
dielectric (ILD) layer over the first side of the semiconductor
substrate; forming a via opening extending from the ILD layer into
a portion of the semiconductor substrate; forming a trench opening
in the ILD layer to expose a portion of the TSV; and depositing a
second conductive material layer in the via and the trench openings
to form an interconnect structure, the interconnect structure
electrically connecting the TSV with the semiconductor
substrate.
2. The method of claim 1, wherein the semiconductor device is an
interposer.
3. The method of claim 1, after the forming the TSV, further
comprising planarizing the first side of the semiconductor
substrate.
4. The method of claim 1, further comprising forming a first
barrier layer between the liner layer and the TSV.
5. The method of claim 4, further comprising forming a first seed
layer between the first barrier layer and the TSV.
6. The method of claim 1, before the forming the ILD layer over the
first side of the semiconductor substrate, further comprising
forming an etch stop layer.
7. The method of claim 1, further comprising forming a second
barrier layer over the via and trench openings.
8. The method of claim 7, further comprising forming a second seed
layer over the second barrier layer.
9. The method of claim 1, wherein the interconnect structure is
formed by electro-chemical plating.
10. The method of claim 1, wherein the TSV and interconnect
structure comprise copper or copper alloys.
11. The method of claim 1, after the forming the interconnect
structure, further comprising planarizing the first side of the
semiconductor substrate.
12. A method of forming an interposer, comprising: providing a
semiconductor substrate, the semiconductor substrate having a front
surface and a back surface opposite the front surface; forming one
or more through-silicon vias (TSVs) extending from the front
surface into the semiconductor substrate; forming an inter-layer
dielectric (ILD) layer overlying the front surface of the
semiconductor substrate and the one or more TSVs; and forming an
interconnect structure having a first partition and a second
partition, the first partition formed in the ILD layer and the
second partition formed in a portion of the semiconductor
substrate, .Iadd.wherein the second partition has straight
sidewalls extending from the first partition to a bottom of the
second partition and .Iaddend.wherein the interconnect structure
electrically connecting the one or more TSVs to the semiconductor
substrate.
13. The method of claim 12, further comprising forming a liner
layer between at least the one or more TSVs and the semiconductor
substrate.
14. The method of claim 13, further comprising forming a barrier
layer and/or a seed layer between the one or more TSVs and the
liner layer.
15. The method of claim 12, further comprising forming a barrier
layer and/or seed layer between at least the interconnect structure
and the ILD layer and the front surface of the semiconductor
substrate.
16. An integrated circuit structure, comprising: a semiconductor
substrate having a front surface and a back surface opposite the
front surface; a through-silicon via (TSV) formed extending from
the front surface of the semiconductor substrate into the
semiconductor substrate; and an interconnect structure having a
first partition and a second partition, the first partition formed
in an inter-layer dielectric (ILD) layer, the ILD layer overlying
the front surface of the semiconductor substrate, and the second
partition formed in a portion of the semiconductor substrate
.Iadd.and having straight sidewalls from a top surface of the
semiconductor substrate to a bottom surface of the second
partition.Iaddend., wherein the interconnect structure electrically
connects the TSV to the semiconductor substrate.
17. The integrated circuit structure of claim 16, wherein the
integrated circuit structure is an interposer.
18. The integrated circuit structure of claim 16, further
comprising a liner layer formed at least between the TSV and the
semiconductor substrate.
19. The integrated circuit structure of claim 18, further
comprising: a barrier layer formed between the TSV and the liner
layer; and a seed layer formed between the TSV and the barrier
layer.
20. The integrated circuit structure of claim 16, wherein the
interconnect structure and the TSV are formed of the same
conductive material.
21. The integrated circuit structure of claim 17, wherein the
interposer comprises passive devices.
22. The integrated circuit structure of claim 21, wherein the
interposer comprises active devices.
23. An interposer, comprising: a semiconductor substrate having a
front surface and a back surface opposite the front surface; a
through-silicon via (TSV) formed extending from the front surface
of the semiconductor substrate into the semiconductor substrate; a
liner layer formed at least between the TSV and the semiconductor
substrate; an inter-layer dielectric (ILD) layer formed over the
front surface of the semiconductor substrate; and an interconnect
structure having a first partition and a second partition, the
first partition formed in the ILD layer and the second partition
formed in a portion of the semiconductor substrate, wherein the
interconnect structure electrically connects the TSV to the
semiconductor substrate .Iadd.and wherein the second partition has
straight sidewalls as the second partition extends into the
semiconductor substrate to a bottom surface of the second
partition.Iaddend..
24. The interposer of claim 23, further comprising a barrier layer
formed between the TSV and the liner layer.
25. The interposer of claim 24, further comprising a seed layer
formed between the TSV and the barrier layer.
26. The interposer of claim 23, wherein the interconnect structure
and the TSV are formed of the same conductive material.
27. The interposer of claim 23, further comprising passive
devices.
28. The interposer of claim 27, further comprising active
devices.
29. A semiconductor package structure, comprising: an interposer
having: a semiconductor substrate having a front surface and a back
surface opposite the front surface; a through-silicon via (TSV)
formed extending from the front surface of the semiconductor
substrate into the semiconductor substrate; a liner layer formed at
least between the TSV and the semiconductor substrate; an
inter-layer dielectric (ILD) layer formed over the front surface of
the semiconductor substrate; and an interconnect structure having a
first partition and a second partition, the first partition formed
in the ILD layer and the second partition formed in a portion of
the semiconductor substrate, wherein the interconnect structure
electrically connects the TSV to the semiconductor substrate.Iadd.,
wherein a straight sidewall of the second partition extends from a
bottom of the second partition to a surface of the semiconductor
substrate facing the first partition.Iaddend.; a semiconductor
chip; and a plurality of bonding pads bonding the semiconductor
chip to the interposer.
30. The semiconductor package structure of claim 29, further
comprising an additional semiconductor chip bonded onto the
semiconductor chip.
31. The semiconductor package structure of claim 29, wherein the
interposer comprises passive devices.
32. The semiconductor package structure of claim 31, wherein the
interposer further comprises active devices.
33. A semiconductor package structure, comprising: an interposer
having: a semiconductor substrate having a front surface and a back
surface opposite the front surface; a through-silicon via (TSV)
formed extending from the front surface of the semiconductor
substrate into the semiconductor substrate; a liner layer formed at
least between the TSV and the semiconductor substrate; an
inter-layer dielectric (ILD) layer formed over the front surface of
the semiconductor substrate; and an interconnect structure having a
first partition and a second partition, the first partition formed
in the ILD layer and the second partition formed in a portion of
the semiconductor substrate, wherein the interconnect structure
electrically connects the TSV to the semiconductor substrate.Iadd.,
the second partition having a straight sidewall through the
semiconductor substrate.Iaddend.; a multi-chip semiconductor
structure having at least a first chip and a second chip; and a
plurality of bonding pads bonding the multi-chip semiconductor
structure to the interposer.
34. The semiconductor package structure of claim 33, wherein the
interposer comprises passive devices.
35. The semiconductor package structure of claim 34, wherein the
interposer further comprises active devices.
.Iadd.36. An integrated circuit structure, comprising: a
semiconductor substrate having a front surface and a back surface
opposite the front surface; a through via (TV) formed in the
semiconductor substrate; a liner layer formed at least between the
TV and the semiconductor substrate; and an interconnect structure
having a first partition and a second partition, the first
partition formed in an inter-layer dielectric (ILD) layer, the ILD
layer overlying the front surface of the semiconductor substrate,
and the second partition formed with straight sidewalls in a
portion of the semiconductor substrate, wherein the interconnect
structure electrically connects the TV to the semiconductor
substrate..Iaddend.
.Iadd.37. The integrated circuit structure of claim 36, wherein the
integrated circuit structure is an interposer..Iaddend.
.Iadd.38. The integrated circuit structure of claim 36, further
comprising: a first barrier layer formed between the TV and the
liner layer; and a seed layer formed between the TV and the first
barrier layer..Iaddend.
.Iadd.39. The integrated circuit structure of claim 38, wherein the
interconnect structure comprises a second barrier
layer..Iaddend.
.Iadd.40. The integrated circuit structure of claim 39, wherein the
second barrier layer is in contact with a top surface of
TV..Iaddend.
.Iadd.41. The integrated circuit structure of claim 39, wherein the
second barrier layer is in contact with the first barrier
layer..Iaddend.
.Iadd.42. The integrated circuit structure of claim 36, wherein the
interconnect structure and the TV are formed of the same conductive
material..Iaddend.
.Iadd.43. The integrated circuit structure of claim 37, wherein the
interposer comprises passive devices..Iaddend.
.Iadd.44. The integrated circuit structure of claim 43, wherein the
interposer comprises active devices..Iaddend.
.Iadd.45. The integrated circuit structure of claim 36, wherein the
TV is grounded..Iaddend.
.Iadd.46. The integrated circuit structure of claim 36, further
comprising another TV in the semiconductor substrate and being
insulated from the semiconductor substrate by the liner
layer..Iaddend.
.Iadd.47. The integrated circuit structure of claim 36, wherein the
liner layer located between the ILD layer and the front surface of
the semiconductor substrate is conformal..Iaddend.
.Iadd.48. An interposer, comprising: a semiconductor substrate
having a front surface and a back surface opposite the front
surface; a through via (TV) formed in the semiconductor substrate;
a liner layer formed at least between the TV and the semiconductor
substrate; an inter-layer dielectric (ILD) layer formed over the
front surface of the semiconductor substrate; an interconnect
structure having a first partition and a second partition, the
first partition formed in the ILD layer and the second partition
formed in a portion of the semiconductor substrate, wherein the
interconnect structure electrically connects the TV to the
semiconductor substrate, wherein the second partition has straight
sidewalls within the semiconductor substrate..Iaddend.
.Iadd.49. The interposer of claim 48, further comprising a first
barrier layer formed between the TV and the liner
layer..Iaddend.
.Iadd.50. The interposer of claim 49, further comprising a seed
layer formed between the TV and the first barrier
layer..Iaddend.
.Iadd.51. The integrated circuit structure of claim 49, wherein the
second liner comprises a second barrier layer..Iaddend.
.Iadd.52. The integrated circuit structure of claim 51, wherein the
second barrier layer is in contact with a top surface of
TV..Iaddend.
.Iadd.53. The integrated circuit structure of claim 51, wherein the
second barrier layer is in contact with the first barrier
layer..Iaddend.
.Iadd.54. The interposer of claim 48, wherein the interconnect
structure and the TV are formed of the same conductive
material..Iaddend.
.Iadd.55. The interposer of claim 48, further comprising passive
devices..Iaddend.
.Iadd.56. The interposer of claim 55, further comprising active
devices..Iaddend.
.Iadd.57. The integrated circuit structure of claim 48, wherein the
TV is grounded..Iaddend.
.Iadd.58. The integrated circuit structure of claim 48, further
comprising another TV in the semiconductor substrate and being
insulated from the semiconductor substrate by the liner
layer..Iaddend.
.Iadd.59. The integrated circuit structure of claim 48, wherein the
liner layer comprises a portion between the ILD layer and the front
surface of the semiconductor substrate..Iaddend.
.Iadd.60. A semiconductor package structure, comprising: an
interposer having: a semiconductor substrate having a front surface
and a back surface opposite the front surface; a through via (TV)
formed in the semiconductor substrate; a liner layer formed at
least between the TV and the semiconductor substrate; a dielectric
layer formed over the front surface of the semiconductor substrate;
and an interconnect structure having a first partition and a second
partition, the first partition formed in the dielectric layer and
the second partition formed in a portion of the semiconductor
substrate, wherein the interconnect structure electrically connects
the TV to the semiconductor substrate, the second partition extends
into the semiconductor substrate a first length, the second
partition having a straight sidewall along the first length; and a
semiconductor chip bonded to the interposer..Iaddend.
.Iadd.61. The semiconductor package structure of claim 60, further
comprising an additional semiconductor chip bonded onto the
semiconductor chip..Iaddend.
.Iadd.62. The semiconductor package structure of claim 60, wherein
the interposer comprises passive devices..Iaddend.
.Iadd.63. The semiconductor package structure of claim 62, wherein
the interposer further comprises active devices..Iaddend.
.Iadd.64. The integrated circuit structure of claim 60, wherein the
semiconductor chip is bonded to the interposer through a plurality
of bonding pads..Iaddend.
.Iadd.65. The integrated circuit structure of claim 60, wherein the
TV is grounded..Iaddend.
.Iadd.66. The integrated circuit structure of claim 60, further
comprising another TV in the semiconductor substrate and being
insulated from the semiconductor substrate by the liner
layer..Iaddend.
.Iadd.67. The integrated circuit structure of claim 60, wherein the
liner layer comprises a portion between the dielectric layer and
the front surface of the semiconductor substrate..Iaddend.
.Iadd.68. A semiconductor package structure, comprising: an
interposer having: a semiconductor substrate having a front surface
and a back surface opposite the front surface; a through via (TV)
in the semiconductor substrate; a liner layer formed at least
between the TV and the semiconductor substrate; a dielectric layer
formed over the front surface of the semiconductor substrate; and
an interconnect structure having a first partition and a second
partition, the first partition formed in the dielectric layer and
the second partition formed with straight sidewalls extending into
a portion of the semiconductor substrate, the straight sidewalls
extending from a first side of the second partition to a second
side of the second partition opposite the first side of the
partition, wherein the interconnect structure electrically connects
the TV to the semiconductor substrate; and a multi-chip
semiconductor structure having at least a first chip and a second
chip, wherein at least one of the first chip and the second chip is
bonded to the interposer..Iaddend.
.Iadd.69. The semiconductor package structure of claim 68, wherein
the interposer comprises passive devices..Iaddend.
.Iadd.70. The semiconductor package structure of claim 69, wherein
the interposer further comprises active devices..Iaddend.
.Iadd.71. The integrated circuit structure of claim 68, wherein the
first chip is bonded to the interposer through a plurality of
bonding pads..Iaddend.
.Iadd.72. The integrated circuit structure of claim 68, wherein the
TV is grounded..Iaddend.
.Iadd.73. The integrated circuit structure of claim 68, further
comprising another TV in the semiconductor substrate and being
insulated from the semiconductor substrate by the liner
layer..Iaddend.
.Iadd.74. The integrated circuit structure of claim 68, wherein the
second chip is bonded onto the first chip..Iaddend.
Description
.Iadd.This application is a reissue application of U.S. Pat. No.
8,872,345. .Iaddend.
FIELD
The disclosure relates generally to the fabrication of
semiconductor devices and, more particularly, to a method of
forming grounded through-silicon vias in a semiconductor
substrate.
BACKGROUND
Interposers are used for integrated circuit packaging, typically
for space transformation, which is for routing connections between
semiconductor dies and packaging components. FIG. 1 illustrates a
cross-sectional view of a portion of an interposer 10. Usually,
interposer 10 includes a substrate 30, which is typically formed of
organic materials or ceramics. One or more through-silicon vias
(TSVs) 50 are formed in the substrate 30 for making electrical
connections from one or more semiconductor dies and/or packaging
components (not shown).
With the increasing scaling down of integrated circuits and
increasing circuit functionality there is an increased demand for
progressively smaller linewidths on the interposer. As linewidths
shrink, RC transmission line effects increase due to loading from
die/die package resistance, inductance, and/or capacitance.
Moreover, as substrate 30 is not grounded cross coupling or cross
talk between adjacent TSVs increases as well. Due to this
cross-coupling between TSVs, signals traveling along relatively
long interconnections suffer delays and other forms of distortion.
As a result, these signals may become corrupted, slowing operation
of integrated circuits or even causing failure. These effects are
more pronounced as operating frequencies increase.
BRIEF DESCRIPTION OF DRAWINGS
The features, aspects, and advantages of the disclosure will become
more fully apparent from the following detailed description,
appended claims, and accompanying drawings in which:
FIG. 1 is a cross-sectional view of a portion of an interposer
showing the problem of low signal integrity resulting from TSV to
TSV coupling.
FIGS. 2-6 are cross-sectional views of a portion of an interposer
at various stages of fabrication according to an exemplary
embodiment of the present disclosure.
DETAILED DESCRIPTION
In the following description, numerous specific details are set
forth to provide a thorough understanding of embodiments of the
present disclosure. However, one having an ordinary skill in the
art will recognize that embodiments of the disclosure can be
practiced without these specific details. In some instances,
well-known structures and processes are not described in detail to
avoid unnecessarily obscuring embodiments of the present
disclosure.
Reference throughout this specification to "one embodiment" or "an
embodiment" means that a particular feature, structure, or
characteristic described in connection with the embodiment is
included in at least one embodiment of the present disclosure.
Thus, the appearances of the phrases "in one embodiment" or "in an
embodiment" in various places throughout this specification are not
necessarily all referring to the same embodiment. Furthermore, the
particular features, structures, or characteristics may be combined
in any suitable manner in one or more embodiments. It should be
appreciated that the following figures are not drawn to scale;
rather, these figures are merely intended for illustration.
FIGS. 2-6 are cross-sectional views of a portion of an interposer
20 at various stages of fabrication according to an exemplary
embodiment of the present disclosure. It is understood that FIGS.
2-6 have been simplified for a better understanding of the
inventive concepts of the present disclosure.
Referring to FIG. 2, the interposer 20 includes a substrate 30
having a front surface 32a and a back surface 32b opposite the
front surface 32a. Substrate 30 is formed of silicon, although
other semiconductor materials including group III, group IV, group
V elements and silicon germanium (SiGe) may also be used. In
alternative embodiments, substrate 30 contains commonly used
materials such as inorganic and organic materials, ceramics, and/or
multi-layers thereof.
In an embodiment to form a TSV opening that extends from front
surface 32a into a portion of the substrate 30, a photoresist layer
(not shown) is spin coated over the front surface 32a of substrate
30. The photoresist layer is then patterned by exposure, bake,
development, and/or other photolithography processes using the
patterned photoresist layer as a masking element to form the TSV
opening passing through a portion of the substrate 30. In some
embodiments, the TSV opening may be etched using any suitable
etching method including, for example, plasma etch, a chemical wet
etch, a laser drill, and/or other suitable processes. In an
embodiment, the etching process includes a deep reactive ion
etching (RIF) process to etch the substrate 30. The etching process
may result in an opening having a vertical sidewall profile or a
tapered sidewall profile.
In another embodiment of forming an opening that is a TSV opening,
a photoresist layer (not shown) may be formed on a hard mask layer
(not shown). The photoresist layer is patterned by exposure, bake,
developing, and/or other photolithography processes to provide an
opening exposing the hard mask layer. The exposed hard mask layer
is then etched, by a wet etch or dry etch process, using the
patterned photoresist layer as a masking element to provide an
opening. Using the hard mask layer and the patterned photoresist
layer as mask elements, an etching process is performed to etch the
exposed substrate 30 forming the TSV opening.
A Liner layer 40 is thereafter formed over substrate 30. Liner
layer 40 is conformally deposited on the front surface 32a of the
substrate 30 and along the sidewalls and bottom of the TSV opening
in order to prevent any conducting material from leaching into
substrate 30. In some embodiments, the liner layer 40 may be formed
of silicon oxide, TEOS (tetraethylorthosilicate) oxide, silicon
nitride, polyimide, combinations thereof, or the like. The
deposition can be carried out using any of a variety of techniques,
including thermal oxidation, LPCVD (low-pressure chemical vapor
deposition), APCVD (atmospheric-pressure chemical vapor
deposition), PECVD (plasma-enhanced chemical vapor deposition), and
other suitable deposition procedures. For example, an LPCVD or
PECVD process with TEOS and O.sub.3 may be employed to form a TEOS
oxide film.
Still referring to FIG. 2, a barrier layer 45a is then formed on
the liner layer 40, lining the TSV opening. The barrier layer 45a
functions as a diffusion barrier to prevent metal diffusion and as
an adhesion layer between metal and dielectric. In some
embodiments, refractory metals, refractory metal-nitrides,
refractory metal-silicon-nitrides, or combinations thereof are
typically used for the barrier layer 45a. For example, TaN, Ta, Ti,
TiN, TiSiN, WN, or combinations thereof may be used. In an
embodiment, the barrier layer 45a includes a TaN layer and a Ta
layer, in another embodiment, the barrier layer 45a is a TiN layer.
In yet another embodiment, the barrier layer 45a is a Ti layer. The
barrier layer 45a can be formed using PVD (physical vapor
deposition), sputtering, or the like. Subsequently, a metal seed
layer (not shown) is formed on the barrier layer 45a. In an
embodiment, the metal seed layer is a copper seed layer that may be
formed by PVD (physical vapor deposition) sputtering, electro
plating, or electroless plating. In some embodiments, other methods
for forming the copper seed layer, such as CVD (chemical vapor
deposition), are used.
Next, a conductive material layer is deposited on the interposer 20
to fill the TSV opening thereby forming a conductive plug 55.
Throughout the description, the conductive plug 55 is referred to
as a through-silicon-via (TSV). The conductive material layer may
include a low resistivity conductor material selected from the
group of conductor materials including, but is not limited to,
copper and copper-based alloy. In some embodiments, the conductive
material layer may comprise various materials, such as tungsten,
aluminum, gold, silver, titanium, or the like. The formation
methods may include sputtering, printing, electroplating,
electroless plating, and/or chemical vapor deposition (CVD)
methods.
Subsequently, the excess portions of the conductive material layer
outside the .[.ISV.]. .Iadd.TSV .Iaddend.opening are removed,
either through etching, chemical mechanical polishing (CMP), or the
like, having the upper surface of the conductive plug 55
substantially coplanar with the upper surface of the liner layer
40.
One or more etch stop layers 60 may optionally be formed over
interposer 20. Generally, the etch stop layers provide a mechanism
to stop an etching process when forming vias and/or contacts. In
some embodiments etch stop layer 60 is formed of a dielectric
material having a different etch selectivity from adjacent layers,
e.g., the underlying liner layer 40, the substrate 30, and an
overlying ILD layer 70. In an embodiment, etch stop layer 60 may be
formed of SiN, SiON, ON, combinations thereof, or the like,
deposited by CVD or PECVD techniques.
Still referring to FIG. 2, the inter-layer dielectric (ILD) layer
70 is formed on the front surface 32a of substrate 30 over the
liner layer 40 and the etch stop layer 60. The ILD layer 70
isolates the TSV 55 from a subsequent formation of interconnection
structure. The ILD layer 70 may be a single layer or a
multi-layered structure. In some embodiments, the ILD layer 70 may
be a silicon oxide containing layer formed of doped or undoped
silicon oxide by a thermal CVD process or high-density plasma (HDP)
process, e.g., undoped silicate glass (USG), phosphorous doped
silicate glass (PSG) or borophosphosilicate glass (BPSG). In some
alternative embodiments, the ILD layer 70 may be formed of doped or
P-doped spin-on-glass (SOG), phosphosilicate TEOS (PTEOS), or
borophosphosilicate TEOS (BPTEOS).
An interconnect structure electrically connecting the .[.ISV.].
.Iadd.TSV .Iaddend.with the substrate 30 will now be described with
reference to FIGS. 3-6. With reference to FIG. 3, a via opening 80
is formed extending from the ILD layer 70 into a portion of the
substrate 30. In some embodiments, via opening 80 may be formed by
firstly coating a photoresist layer (not shown) on ILD layer 70.
The photoresist layer is then patterned by exposure, bake,
development, and/or other photolithography processes using the
patterned photoresist layer as a masking element to form the via
opening. In some embodiments, the via opening 80 may be etched
using any suitable etching method including, for example, a plasma
etch, a chemical wet etch, a laser drill, and/or other processes.
The etching process may result in an opening having a vertical
sidewall profile or a tapered sidewall profile.
In another embodiment of forming an opening that is a via opening,
a photoresist layer (not shown) may be formed on a hard mask layer
(not shown). The photoresist layer is patterned by exposure, bake,
developing, and/or other photolithography processes to provide an
opening exposing the hard mask layer. The exposed hard mask layer
is then etched, by a wet etch or dry etch process, using the
patterned photoresist layer as a masking element to provide an
opening. Using the hard mask layer and the patterned photoresist
layer as mask elements, an etching process is performed to etch the
exposed substrate 30 forming the via opening.
A trench opening 90, shown in FIG. 4, is then formed in the ILD
layer 70 in a similar fashion as forming the via opening 80 above
and hence the process will not be repeated herein. The trench
opening 90 exposes a portion of the TSV 55 so that in a subsequent
step a conductive material layer will be deposited on interposer
20, said conductive material layer forming an interconnect
structure that connects TSV 55 with substrate 30. A barrier layer
45b may be formed over interposer 20, in the via opening 80 and the
trench opening 90. A seed layer (not shown) may be subsequently
formed over the barrier layer 45b. Both the materials and processes
used for forming the barrier layer 45b and the seed layer was
previously described above with reference to FIG. 2 and will
therefore not be described again.
Referring to FIG. 5, the interposer 20 is transferred to a plating
tool, such as an electrochemical plating (ECP) tool, and a
conductive material layer is plated on the interposer 20 by the
plating process to fill the via opening 80 and the trench opening
90 to form an interconnect structure 100. While the ECP process is
described therein, the embodiment is not limited to ECP deposited
metal. The conductive material layer may include a low resistivity
conductor material selected from the group of conductor materials
including, but is not limited to, copper and copper-based alloy. In
some embodiments, the conductive material layer 80 may comprise
various materials, such as tungsten, aluminum, gold, silver, or the
like. This electroplating process forms a void-free metallization
structure to provide a reliable solution. Other methods for
depositing a conductive material layer in via opening 80 and trench
opening 90 are also contemplated.
Following the depositing of the conductive material layer, the
upper surface of interposer 20 undergoes a planarization step.
Excess portions of the conductive material layer outside the via
and trench openings are removed, either through etching, chemical
mechanical polishing (CMP), or the like, having the upper surface
of the interconnect structure 100 substantially coplanar with the
upper surface of the ILD layer 70.
Advantageously, interposer 20 may be easily customized to suit
different requirements. In an exemplary embodiment, an active or
passive device (not shown) is embedded into the interposer 20,
wherein the active or passive device may include capacitors,
resistors, and the like.
It is understood that additional processes may be performed to
complete the fabrication of interposer 20 to form various features
for implementation in a semiconductor package structure. Subsequent
fabrication processing may further form features such as metal
lines, connecting vias, dielectric layers, bonding pads, or solder
bumps configured to connect the various features or structures of
interposer 20 to one or more semiconductor chips. In an exemplary
embodiment, a semiconductor chip can be bonded onto interposer 20
with a plurality of bonding pads. One skilled in the art will
realize the corresponding bonding process steps. In another
exemplary embodiment, a multi-chip structure having at least two
semiconductor chips can be bonded onto interposer 20. According to
one embodiment, the at least two chips are bonded together before
they are bonded onto interposer 20. Alternatively, a first chip is
bonded onto interposer 20 first, and then the second chip is bonded
onto the first chip.
.Iadd.FIG. 6 illustrates another embodiment in which the conductive
plug 55 is utilized along with another conductive plug 57, which
may also be another through-silicon via (TSV) or another
through-via (TV) in those circumstances when the substrate 30 is a
non-silicon material. In this embodiment the another conductive
plug 57 may be similar to the conductive plug 55, and may be
insulated from the substrate 30 by the line layer 40. .Iaddend.
According to one embodiment, a method of forming a semiconductor
device comprises providing a semiconductor substrate, the
semiconductor substrate having a first side and a second side
opposite the first side; forming a through-silicon via (TSV)
opening extending from the first side of the semiconductor
substrate into the semiconductor substrate; forming a liner layer
on the first side of the semiconductor substrate and along the
.[.sidewalk.]. .Iadd.sidewall .Iaddend.and bottom of the TSV
opening; depositing a first conductive material layer over the
liner layer in the opening to form a TSV; forming an
.[.interlayer.]. .Iadd.inter-layer .Iaddend.dielectric (ILD) layer
over the first side of the semiconductor substrate; forming a via
opening extending from the ILD layer into a portion of the
semiconductor substrate; forming a trench opening in the .[.IUD.].
.Iadd.ILD .Iaddend.layer to expose a portion of the ISV; and
depositing a second conductive material layer in the via and the
trench openings to form an interconnect structure, the interconnect
structure electrically connecting the TSV with the semiconductor
substrate.
According to another embodiment, a method of forming an interposer
comprises providing a semiconductor substrate, the semiconductor
substrate having a front surface and a back surface opposite the
front surface; forming one or more through-silicon vias (TSVs)
extending from the front surface into the semiconductor substrate;
forming an inter-layer dielectric (ILD) layer overlying the front
surface of the semiconductor substrate and the one or more TSVs;
and forming an interconnect structure having a first partition and
a second partition, the first partition formed in the ILD layer and
the second partition formed in a portion of the semiconductor
substrate, wherein the interconnect structure electrically connects
the one or more TSVs to the semiconductor substrate.
According to yet another embodiment, an integrated circuit
structure comprises a semiconductor substrate having a front
surface and a hack surface opposite the front surface; a TSV formed
extending from the front surface of the semiconductor substrate
into the semiconductor substrate; and an interconnect structure
having a first partition and a second partition, the first
partition formed in an ILD layer, the ILD layer overlying the front
surface of the semiconductor substrate and the second partition
formed in a portion of the semiconductor substrate, wherein the
interconnect structure electrically connects the TSV to the
semiconductor substrate.
According to yet another embodiment, an interposer comprises a
semiconductor substrate having a front surface and a back surface
opposite the front surface; a TSV formed extending from the front
surface of the semiconductor substrate into the semiconductor
substrate; a liner layer formed at least between the TSV and the
semiconductor substrate; an ILD layer formed over the front surface
of the semiconductor substrate; and an interconnect structure
having a first partition and a second partition, the first
partition formed in the ILD layer and the second partition formed
in a portion of the semiconductor substrate. Wherein the
interconnect structure electrically connects the TSV to the
semiconductor substrate.
According to yet still another embodiment, a semiconductor package
structure comprises an interposer having a semiconductor substrate
having a front surface and a back surface opposite the front
surface; a TSV formed extending from the front surface of the
semiconductor substrate into the semiconductor substrate; a liner
layer formed at least between the TSV and the semiconductor
substrate; an ILD layer formed over the front surface of the
semiconductor substrate; and an interconnect structure having a
first partition and a second partition, the first partition formed
in the ILD layer and the second partition formed in a portion of
the semiconductor substrate, wherein the interconnect structure
electrically connects the TSV to the semiconductor substrate. The
package structure further comprises a semiconductor chip; and a
plurality of bonding pads bonding the semiconductor chip to the
interposer.
According to yet another embodiment, a semiconductor package
structure comprises an interposer having: a semiconductor substrate
having a front surface and a back surface opposite the front
surface; a TSV formed extending from the front surface of the
semiconductor substrate into the semiconductor substrate; a liner
layer formed at least between the TSV and the semiconductor
substrate; an ILD layer formed over the front surface of the
semiconductor substrate; and an interconnect structure having a
first partition and a second partition, the first partition formed
in the ILD layer and the second partition formed in a portion of
the semiconductor substrate. Wherein the interconnect structure
electrically connects the TSV to the semiconductor substrate. The
package structure further comprises a multi-chip semiconductor
structure having at least a first chip and a second chip; and a
plurality of bonding pads bonding the semiconductor structure to
the interposer.
One or more of the embodiments of the present disclosure discussed
above have advantages over existing methods. It is understood,
however, that other embodiments may have different advantages, and
that no particular advantage is required for all embodiments.
One of the advantages is that as TSV 55 is grounded (e.g., TSV 55
is electrically connected to substrate 30), cross coupling and
cross talk between adjacent TSVs can be minimized. By having the
TSVs grounded, resistive-capacitive delays that hinder further
increasing of speed in microelectronic integrated circuits are
minimized and signal integrity is thereby improved. Further, as an
added benefit, a grounded TSV provides for better heat dissipation,
especially in micro-electronic ICs having smaller and smaller
feature sizes. As a further advantage by grounding the TSV, charge
build-up on electrostatic discharge (ESD) sensitive integrated
circuits from an ESD event is prevented, thus reducing damage to
the integrated circuit.
In the preceding detailed description, specific exemplary
embodiments have been described. It will, however, be apparent to a
person of ordinary skill in the art that various modifications,
structures, processes, and changes may be made thereto without
departing from the broader spirit and scope of the present
disclosure. The specification and drawings are, accordingly, to be
regarded as illustrative and not restrictive. It is understood that
embodiments of the present disclosure are capable of using various
other combinations and environments and are capable of changes or
modifications within the scope of the claims.
* * * * *