Semiconductor package

Description

FIG. 1 is a front, top and left side perspective view of a semiconductor package showing our new design;

FIG. 2 is a front view thereof;

FIG. 3 is a rear view thereof;

FIG. 4 is a top view thereof;

FIG. 5 is a bottom view thereof;

FIG. 6 is a left side view thereof;

FIG. 7 is a right view thereof;

FIG. 8 is a cross-sectional view taken along line 8-8 in FIG. 2, with the internal structure shown in broken lines; and,

FIG. 9 is a perspective view of FIG. 1, shown in a state of use.

The parts shown in even dashed broken lines do not form part of the claimed design. The dot and dashed lines mean a boundary between the claimed portion and the non-claimed portion and form no part of the claimed design.

Claims

CLAIM The ornamental design for a semiconductor package, as shown and described.

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Inventors:	Itakura; Hiroshi (Tokyo, JP), Yamagishi; Keitaro (Tokyo, JP), Akeboshi; Yoshihiro (Tokyo, JP)
Applicant:	Name City State Country Type Mitsubishi Electric Corporation Tokyo N/A JP
Assignee:	Mitsubishi Electric Corporation (Tokyo, JP)
Appl. No.:	D/709,607
Filed:	October 16, 2019

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	29614124	Aug 16, 2017	D877707

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Foreign Application Priority Data

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Mar 30, 2017 [JP]			2017-006616
Mar 30, 2017 [JP]			2017-006617
Mar 30, 2017 [JP]			2017-006618
Mar 30, 2017 [JP]			2017-006619
Mar 30, 2017 [JP]			2017-006620

Current U.S. Class:	D13/182
Current International Class:	1303
Field of Search:	;D13/182 ;257/678,684,690,691 ;361/679.01,713,728,736,760,761,772,775,783,820 ;174/250,253 ;438/15,25,26,51,55,63,64,106

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References Cited [Referenced By]

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U.S. Patent Documents

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Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Studebaker & Brackett PC

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