U.S. patent number D476,296 [Application Number D/156,639] was granted by the patent office on 2003-06-24 for semiconductor device.
This patent grant is currently assigned to Sharp Kabushiki Kaisha. Invention is credited to Hideshi Koizumi.
United States Patent |
D476,296 |
Koizumi |
June 24, 2003 |
Semiconductor device
Claims
The ornamental design for a "semiconductor device", as shown and
described.
Inventors: |
Koizumi; Hideshi (Nara-ken,
JP) |
Assignee: |
Sharp Kabushiki Kaisha (Osaka,
JP)
|
Appl.
No.: |
D/156,639 |
Filed: |
March 6, 2002 |
Foreign Application Priority Data
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|
|
|
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Sep 6, 2001 [JP] |
|
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2001-026198 |
Sep 6, 2001 [JP] |
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2001-026199 |
Sep 6, 2001 [JP] |
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2001-026205 |
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Current U.S.
Class: |
D13/182 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/182
;257/670,672,676,686,688,690-696,703,787
;361/736,742,748,752,760,761,774,783,784,785,798,813,820
;372/43 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Shooman; Ted
Assistant Examiner: Sikder; Selina
Attorney, Agent or Firm: Nixon & Vanderhye
Description
FIG. 1 is a top, front and right side perspective view of a
semiconductor device according to my design;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a rear elevational view thereof;
FIG. 4 is a top plan view thereof;
FIG. 5 is a bottom plan view thereof;
FIG. 6 is a right side elevational view thereof, the left side
elevational view being a mirror image thereof;
FIG. 7 is a view of a further embodiment of a semiconductor device
similar to FIG. 1, the broken lines illustrating environmental
structure of this embodiment which does not form part of the design
of this embodiment;
FIG. 8 is a front elevational view thereof;
FIG. 9 is a rear elevational view thereof;
FIG. 10 is a top plan view thereof;
FIG. 11 is a bottom plan view thereof; and,
FIG. 12 is a right side elevational view thereof, the left side
elevational view being a mirror image thereof.
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