U.S. patent number D673,922 [Application Number D/393,921] was granted by the patent office on 2013-01-08 for portion of a substrate for an electronic circuit.
This patent grant is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Toyokazu Eguchi, Takakatsu Moriai, Isao Ozawa.
United States Patent |
D673,922 |
Moriai , et al. |
January 8, 2013 |
Portion of a substrate for an electronic circuit
Claims
CLAIM The ornamental design for a portion of a substrate for an
electronic circuit, as shown and described.
Inventors: |
Moriai; Takakatsu (Honjo,
JP), Ozawa; Isao (Chigasaki, JP), Eguchi;
Toyokazu (Inagi, JP) |
Assignee: |
Kabushiki Kaisha Toshiba
(JP)
|
Appl.
No.: |
D/393,921 |
Filed: |
June 10, 2011 |
Foreign Application Priority Data
|
|
|
|
|
Apr 21, 2011 [JP] |
|
|
2011-009238 |
|
Current U.S.
Class: |
D13/182 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/182 ;257/678,690
;361/679.31,719,720,752,777,820 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
Primary Examiner: Sikder; Selina
Attorney, Agent or Firm: Banner & Witcoff, Ltd.
Description
FIG. 1 is a front, bottom and left side perspective view of a
portion of a substrate for an electronic circuit, showing our new
design;
FIG. 2 is a top plan view thereof;
FIG. 3 is a left side elevational view thereof;
FIG. 4 is a front elevational view thereof;
FIG. 5 is a right side elevational view thereof;
FIG. 6 is a bottom plan view thereof; and,
FIG. 7 is a rear elevational view thereof.
The uneven spaced broken lines define the bounds of the claimed
design and form no part thereof. The even spaced broken line
showing of the substrate for an electronic circuit is for
illustrative purpose only and forms no part of the claimed
design.
* * * * *