U.S. patent number D621,803 [Application Number D/321,418] was granted by the patent office on 2010-08-17 for semiconductor wafer processing tape.
This patent grant is currently assigned to The Furukawa Electric Co., Ltd.. Invention is credited to Shinichi Ishiwata, Hiromitsu Maruyama, Yasumasa Morishima, Shuzo Taguchi.
United States Patent |
D621,803 |
Maruyama , et al. |
August 17, 2010 |
Semiconductor wafer processing tape
Claims
CLAIM The ornamental design for a "semiconductor wafer processing
tape," as shown and described.
Inventors: |
Maruyama; Hiromitsu (Tokyo,
JP), Taguchi; Shuzo (Tokyo, JP), Morishima;
Yasumasa (Tokyo, JP), Ishiwata; Shinichi (Tokyo,
JP) |
Assignee: |
The Furukawa Electric Co., Ltd.
(Tokyo, JP)
|
Appl.
No.: |
D/321,418 |
Filed: |
July 16, 2008 |
Current U.S.
Class: |
D13/182 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/182 ;156/235,248
;428/343,345,353,355R ;438/114,455,460,463 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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D1267623 |
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Apr 2006 |
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JP |
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2007-2173 |
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Jan 2007 |
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JP |
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D1315406 |
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Nov 2007 |
|
JP |
|
D1315621 |
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Nov 2007 |
|
JP |
|
Primary Examiner: Sikder; Selina
Attorney, Agent or Firm: Knoble Yoshida & Dunleavy,
LLC
Description
FIG. 1 is a perspective view showing our new design;
FIG. 2 is a top plan view;
FIG. 3 is a bottom plan view;
FIG. 4 is a left side view;
FIG. 5 is a front side view;
FIG. 6 is a right side view;
FIG. 7 is a cross sectional view at 7--7 of FIG. 1; and,
FIG. 8 is a cross sectional view at 8--8 of FIG. 1.
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