Portion of a printed circuit board

Kobayashi , et al. August 4, 2

Patent Grant D597504

U.S. patent number D597,504 [Application Number D/279,827] was granted by the patent office on 2009-08-04 for portion of a printed circuit board. This patent grant is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Atsushi Kobayashi, Hiroshi Takei.


United States Patent D597,504
Kobayashi ,   et al. August 4, 2009

Portion of a printed circuit board

Claims

CLAIM The ornamental design for a portion of a printed circuit board, as shown and described.
Inventors: Kobayashi; Atsushi (Tokyo, JP), Takei; Hiroshi (Tokyo, JP)
Assignee: Kabushiki Kaisha Toshiba (Tokyo, JP)
Appl. No.: D/279,827
Filed: May 8, 2007

Foreign Application Priority Data

Nov 30, 2006 [JP] 2006-033055
Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;29/829 ;361/720,749,760,776,820 ;174/250,253,255

References Cited [Referenced By]

U.S. Patent Documents
4724514 February 1988 Kaufman
5339219 August 1994 Urich
D363920 November 1995 Roberts et al.
5614698 March 1997 Estes
5661343 August 1997 Takahashi et al.
5838546 November 1998 Miyoshi
5905639 May 1999 Warren
D428860 August 2000 Siperek
D466093 November 2002 Ebihara et al.
D471167 March 2003 Ebihara et al.
D471524 March 2003 Ebihara et al.
6585525 July 2003 Jung et al.
6721821 April 2004 Rent
6985341 January 2006 Vinciarelli et al.
D570307 June 2008 Kobayashi et al.
D576577 September 2008 Kobayashi et al.
2002/0189083 December 2002 Matsumoto et al.
2006/0126314 June 2006 Jeong
2006/0239037 October 2006 Repetto et al.
2007/0294889 December 2007 Schmitt et al.
2008/0007926 January 2008 Lee et al.
Primary Examiner: Sikder; Selina
Attorney, Agent or Firm: Banner & Witcoff, Ltd.

Description



FIG. 1 is a front, bottom and right side perspective view of a portion of a printed circuit board, showing our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a right side elevational view thereof;

FIG. 7 is a left side elevational view thereof;

FIG. 8 is an enlarged view thereof showing the portion marked with F--F, G--G in FIG. 2;

FIG. 9 is an enlarged view thereof showing the portion marked with 9--9 in FIG. 6; and,

FIG. 10 is an enlarged view thereof showing the portion marked with 10--10 in FIG. 5.

The uneven spaced broken lines define the bounds of the claimed design and form no part thereof. The even spaced broken line showing of the printed circuit board is for illustrative purpose only and forms no part of the claimed design.

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