U.S. patent number D576,577 [Application Number D/279,843] was granted by the patent office on 2008-09-09 for portion of a printed circuit board.
This patent grant is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Atsushi Kobayashi, Hiroshi Takei.
United States Patent |
D576,577 |
Kobayashi , et al. |
September 9, 2008 |
Portion of a printed circuit board
Claims
CLAIM The ornamental design for a portion of a printed circuit
board, as shown and described.
Inventors: |
Kobayashi; Atsushi (Tokyo,
JP), Takei; Hiroshi (Tokyo, JP) |
Assignee: |
Kabushiki Kaisha Toshiba
(JP)
|
Appl.
No.: |
D/279,843 |
Filed: |
May 8, 2007 |
Foreign Application Priority Data
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|
|
|
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Nov 30, 2006 [JP] |
|
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2006-033057 |
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Current U.S.
Class: |
D13/182 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/182 ;29/829
;361/720,749,760,776,820 ;174/250,253,255 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Sikder; Selina
Attorney, Agent or Firm: Banner & Witcoff, Ltd.
Description
FIG. 1 is a front, bottom and right side perspective view of a
portion of a printed circuit board, showing our new design;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a rear elevational view thereof;
FIG. 4 is a top plan view thereof;
FIG. 5 is a bottom plan view thereof;
FIG. 6 is a right side elevational view thereof;
FIG. 7 is a left side elevational view thereof;
FIG. 8 is an enlarged view thereof showing the portion marked with
8--8 in FIG. 6; and,
FIG. 9 is an enlarged view thereof showing the portion marked with
9--9 in FIG. 5.
The uneven spaced broken lines define the bounds of the claimed
design and form no part thereof. The even spaced broken line
showing of the printed circuit board is for illustrative purpose
only and forms no part of the claimed design.
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