U.S. patent number D571,810 [Application Number D/268,869] was granted by the patent office on 2008-06-24 for module with built-in integrated circuits for use with ic cards.
This patent grant is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Hidetaka Ikeda.
United States Patent |
D571,810 |
Ikeda |
June 24, 2008 |
Module with built-in integrated circuits for use with IC cards
Claims
CLAIM We claim the ornamental design for a module with built-in
integrated circuits for use with IC cards, as shown and described.
Inventors: |
Ikeda; Hidetaka (Yokohama,
JP) |
Assignee: |
Kabushiki Kaisha Toshiba
(JP)
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Appl.
No.: |
D/268,869 |
Filed: |
November 15, 2006 |
Foreign Application Priority Data
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Jun 20, 2006 [JP] |
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2006-016006 |
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Current U.S.
Class: |
D14/437 |
Current International
Class: |
1402 |
Field of
Search: |
;D14/435-437,478-480,485-495,474 ;D13/182
;369/275.1-275.5,44.26,284,286,100,52.1,272,273,280-288 ;283/81
;720/718 ;435/6,287.2 ;604/891.1 ;216/2 ;D11/80 ;235/492,488
;361/737 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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981863 |
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May 1997 |
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JP |
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1196836 |
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Feb 2004 |
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JP |
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Primary Examiner: Tung; Melanie
Assistant Examiner: Lee; Susan Moon
Attorney, Agent or Firm: Banner & Witcoff, Ltd.
Description
FIG. 1 is a perspective view of a module with built-in integrated
circuits for use with IC cards showing my new design,
FIG. 2 is a front elevational view thereof,
FIG. 3 is a rear elevational view thereof,
FIG. 4 is a left side elevational view thereof,
FIG. 5 is a right side elevational view thereof,
FIG. 6 is a top plan view thereof,
FIG. 7 is a bottom plan view thereof; and,
FIG. 8 is a reduced reference view showing the article in use
thereof.
The portions shown in broken lines are for illustrative purposes
only and form no part of the claimed design.
* * * * *