Grooves formed around a semiconductor device on a circuit board

Terada , et al. May 13, 2

Patent Grant D568838

U.S. patent number D568,838 [Application Number D/268,260] was granted by the patent office on 2008-05-13 for grooves formed around a semiconductor device on a circuit board. This patent grant is currently assigned to Nitto Denko Corporation. Invention is credited to Kouji Kataoka, Toshiki Naito, Tetsuya Ohsawa, Naohiro Terada.


United States Patent D568,838
Terada ,   et al. May 13, 2008

Grooves formed around a semiconductor device on a circuit board

Claims

CLAIM The ornamental design for grooves formed around a semiconductor device on a circuit board, as shown and described.
Inventors: Terada; Naohiro (Osaka, JP), Kataoka; Kouji (Osaka, JP), Ohsawa; Tetsuya (Osaka, JP), Naito; Toshiki (Osaka, JP)
Assignee: Nitto Denko Corporation (Osaka, JP)
Appl. No.: D/268,260
Filed: November 1, 2006

Foreign Application Priority Data

May 1, 2006 [JP] 2006-011426
May 1, 2006 [JP] 2006-011429
May 1, 2006 [JP] 2006-011430
May 1, 2006 [JP] 2006-011431
May 1, 2006 [JP] 2006-011432
May 1, 2006 [JP] 2006-011435
May 1, 2006 [JP] 2006-011439
May 1, 2006 [JP] 2006-011440
May 1, 2006 [JP] 2006-011441
May 1, 2006 [JP] 2006-011442
Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;174/250,251,253,254,255,256,265,260,261 ;361/760,748,720 ;336/200

References Cited [Referenced By]

U.S. Patent Documents
D319629 September 1991 Hasegawa et al.
5420558 May 1995 Ito et al.
5467252 November 1995 Nomi et al.
5777277 July 1998 Inagawa
5969590 October 1999 Gutierrez
6114937 September 2000 Burghartz et al.
6121552 September 2000 Brosnihan et al.
6486412 November 2002 Kato
6798326 September 2004 Iida
6922128 July 2005 Vilander et al.
7068138 June 2006 Edelstein et al.
7126452 October 2006 Teshima et al.
2006/0266545 November 2006 Takeuchi et al.
2007/0188287 August 2007 Lien et al.
2007/0205856 September 2007 Matsunaga et al.
Primary Examiner: Sikder; Selina
Attorney, Agent or Firm: Osha Liang LLP

Description



FIG. 1 is a plan view of a first embodiment of the grooves formed around a semiconductor device on a circuit board showing our new design;

FIG. 2 is an enlarged view of the area boxed by the dash-dot-dash line in FIG. 1;

FIG. 3 is a sectional view taken along line 3--3 in FIG. 2;

FIG. 4 is a sectional view taken along line 4--4 in FIG. 2;

FIG. 5 is a plan view of a second embodiment;

FIG. 6 is an enlarged view of the area boxed by the dash-dot-dash line in FIG. 5;

FIG. 7 is a sectional view taken along line 7--7 in FIG. 6;

FIG. 8 is a sectional view taken along line 8--8 in FIG. 6;

FIG. 9 is a plan view of a third embodiment;

FIG. 10 is an enlarged view of the area boxed by the dash-dot-dash line in FIG. 9;

FIG. 11 is a sectional view taken along line 11--11 in FIG. 10; and,

FIG. 12 is a sectional view taken along line 12--12 in FIG. 10.

The broken lines represent unclaimed subject matter.

* * * * *


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