Semiconductor device

Description

FIG. 1 is a front perspective view of a semiconductor device, showing our new design;

FIG. 2 is a rear perspective view thereof;

FIG. 3 is a top plan view thereof; a bottom plan view being a mirror image thereof;

FIG. 4 is a right side elevational view thereof; a left side elevational view being a mirror image thereof;

FIG. 5 is a front elevational view thereof; and,

FIG. 6 is a rear elevational view thereof.

Claims

The ornamental design for a semiconductor device, as shown and described.

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Inventors:	Hori; Tetsuji (Yokohama, JP), Yoshihira; Takayuki (Yokohama, JP), Hiyama; Yuuji (Yokohama, JP), Ookura; Gentaro (Tokyo, JP)
Assignee:	Kabushiki Kaisha Toshiba (Tokyo, JP)
Appl. No.:	D/167,131
Filed:	September 10, 2002

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Foreign Application Priority Data

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Mar 11, 2002 [JP]			2002-006217

Current U.S. Class:	D13/182
Current International Class:	1303
Field of Search:	;D13/110,123,125,179,182 ;174/16.3,52.1,52.2,52.4 ;211/261,4.17,162 ;361/718,728,747,748,760,774,784,785,813,820

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References Cited [Referenced By]

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U.S. Patent Documents

5401910	March 1995	Mandai et al.
5450286	September 1995	Jacques et al.
5459641	October 1995	Kuriyama
5726859	March 1998	Khadem et al.
D396846	August 1998	Nakayama et al.
6232655	May 2001	Sugimura
D444132	June 2001	Iwanishi et al.
6330165	December 2001	Kohjiro et al.
6459048	October 2002	Sakai et al.

Other References

Catalog of a Chip Size Package (VMN4). . Extract of Nihon Kogyo Shimbun (Newspaper) showing a Chip-Type Transistor Package (E-CSP)..

Primary Examiner: Shooman; Ted
Assistant Examiner: Sikder; Selina
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.