U.S. patent number 9,412,841 [Application Number 14/810,722] was granted by the patent office on 2016-08-09 for method of fabricating a transistor using contact etch stop layers.
This patent grant is currently assigned to Taiwan Semiconductor Manufacturing Company, Ltd.. The grantee listed for this patent is TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.. Invention is credited to Harry-Hak-Lay Chuang, Lee-Wee Teo, Bao-Ru Young, Ming Zhu.
United States Patent |
9,412,841 |
Teo , et al. |
August 9, 2016 |
Method of fabricating a transistor using contact etch stop
layers
Abstract
A method for fabricating a field-effect transistor includes
forming a spacer adjacent to sidewalls of a gate structure. The
method further includes forming silicide regions in a substrate
adjacent to the spacer. The method further includes depositing a
first interlayer dielectric layer over the substrate. The method
further includes exposing a top surface of the gate structure. The
method further includes depositing a contact etch stop layer over
the first interlayer dielectric layer and the top surface of the
gate structure. The method further includes patterning the contact
etch stop layer to remove a portion of the contact etch stop layer
over the silicide regions, wherein the contact etch stop layer over
the gate structure is maintained.
Inventors: |
Teo; Lee-Wee (Singapore,
SG), Zhu; Ming (Singapore, SG), Young;
Bao-Ru (Zhubei, TW), Chuang; Harry-Hak-Lay
(Singapore, SG) |
Applicant: |
Name |
City |
State |
Country |
Type |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
Hsinchu |
N/A |
TW |
|
|
Assignee: |
Taiwan Semiconductor Manufacturing
Company, Ltd. (Hsin-Chu, TW)
|
Family
ID: |
45545841 |
Appl.
No.: |
14/810,722 |
Filed: |
July 28, 2015 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20150333150 A1 |
Nov 19, 2015 |
|
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
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13858687 |
Apr 8, 2013 |
9117894 |
|
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12849601 |
May 28, 2013 |
8450216 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
21/31144 (20130101); H01L 21/76802 (20130101); H01L
21/76829 (20130101); H01L 21/28518 (20130101); H01L
29/78 (20130101); H01L 29/7833 (20130101); H01L
29/6656 (20130101); H01L 21/76834 (20130101); H01L
21/76897 (20130101); H01L 29/66545 (20130101); H01L
21/31116 (20130101); H01L 21/76816 (20130101); H01L
21/0217 (20130101); H01L 29/66575 (20130101) |
Current International
Class: |
H01L
21/44 (20060101); H01L 29/66 (20060101); H01L
21/311 (20060101); H01L 21/285 (20060101); H01L
21/768 (20060101); H01L 29/78 (20060101); H01L
21/02 (20060101) |
Field of
Search: |
;438/655,233,620,621,622,623,624,740
;257/E21.5,E21.501,E21.585,E21.593,E21.625,E29.255,288 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
Other References
Office Action dated Dec. 27, 2012 from corresponding application
No. CN 201110038163.5. cited by applicant.
|
Primary Examiner: Luu; Chuong A
Assistant Examiner: Eskridge; Cory
Attorney, Agent or Firm: Slater Matsil, LLP
Parent Case Text
PRIORITY CLAIM
This application is a continuation of U.S. application Ser. No.
13/858,687, filed Apr. 8, 2013, which is a continuation application
of U.S. application Ser. No. 12/849,601, filed Aug. 3, 2010, now
U.S. Pat. No. 8,450,216, issued May 28, 2013, which are hereby
incorporated by reference in their entireties.
Claims
What is claimed is:
1. A method for fabricating a field-effect transistor, the method
comprising: forming a spacer adjacent to sidewalls of a gate
structure; forming silicide regions in a substrate adjacent to the
spacer; depositing a first interlayer dielectric layer over the
substrate; exposing a top surface of the gate structure; depositing
a contact etch stop layer over the first interlayer dielectric
layer and the top surface of the gate structure; and patterning the
contact etch stop layer to remove a first portion of the contact
etch stop layer over the silicide regions, wherein a second portion
of the contact etch stop layer over the gate structure is
maintained; forming a second interlayer dielectric layer over the
first interlayer dielectric layer; and patterning the second
interlayer dielectric layer and the first interlayer dielectric
layer, wherein at least a portion of the second interlayer
dielectric layer contacts a sidewall of the second portion of the
contact etch stop layer.
2. The method of claim 1, wherein forming the second interlayer
dielectric layer comprises forming a first portion of the second
interlayer dielectric layer over the silicide regions in contact
with the first interlayer dielectric layer.
3. The method of claim 2, wherein forming the second interlayer
dielectric layer further comprises forming a second portion of the
second interlayer dielectric layer over the gate structure in
contact with the contact etch stop layer.
4. The method of claim 1, further comprising etching the contact
etch stop layer, after patterning the contact etch stop layer, to
expose a portion of the gate structure.
5. The method of claim 1, further comprising depositing an
additional contact etch stop layer over the silicide regions and
over the spacer.
6. The method of claim 5, wherein depositing the contact etch stop
layer comprises depositing the contact etch stop layer in contact
with the additional contact etch stop layer.
7. The method of claim 5, wherein patterning the second interlayer
dielectric layer and the first interlayer dielectric layer
comprises forming patterning holes in the first interlayer
dielectric layer and the second interlayer dielectric layer,
wherein the patterning holes expose the contact etch stop layer
over the gate structure and the additional contact etch stop layer
over the silicide regions.
8. The method of claim 7, further comprising simultaneously etching
the contact etch stop layer and the additional contact etch stop
layer to expose a portion of the gate structure and a portion of
the silicide regions.
9. A method for fabricating a transistor, the method comprising:
depositing a first contact etch stop layer over a top surface of a
gate structure, a spacer adjacent to a sidewall of the gate
structure, and a silicide region adjacent to the spacer, the first
contact etch stop layer having a first thickness; depositing a
first interlayer dielectric layer over the first contact etch stop
layer; exposing a portion of the gate structure; depositing a
second contact etch stop layer over the first interlayer dielectric
layer, the second contact etch stop layer having a second
thickness, the second thickness being greater than the first
thickness; and patterning the second contact etch stop layer to
remove a portion of the second contact etch stop layer, the portion
of the second contact etch stop layer being directly over the
silicide region.
10. The method of claim 9, further comprising etching a contact
hole in the first interlayer dielectric layer, wherein the contact
holes are over the silicide region.
11. The method of claim 10, further comprising: etching the first
contact etch stop layer through the contact hole to expose a
portion of the silicide region; and etching the second contact etch
stop layer to expose a portion of the top surface of the gate
structure.
12. The method of claim 11, wherein etching the first contact etch
stop layer comprises etching the first contact etch stop layer
simultaneously with etching the second contact etch stop layer.
13. The method of claim 11, wherein etching the first contact etch
stop layer comprises etching the first contact etch stop layer
using an etchant comprising CH.sub.2F.sub.2.
14. The method of claim 9, further comprising depositing a second
interlayer dielectric layer over the first interlayer dielectric
layer, wherein the second interlayer dielectric layer contacts a
sidewall of the second contact etch stop layer.
15. The method of claim 9, wherein patterning the second contact
etch stop layer comprises patterning the second contact etch stop
layer to have a patterned width greater than a width of the gate
structure.
16. A method for fabricating a transistor, the method comprising:
depositing a first contact etch stop layer over a gate structure of
the transistor and a silicide region of the transistor, the first
contact etch stop layer having a first thickness, the gate
structure comprising a dummy gate electrode; depositing a first
interlayer dielectric layer over the first contact etch stop layer;
exposing the dummy gate electrode; replacing the dummy gate
electrode with a gate electrode; depositing a second contact etch
stop layer over the first interlayer dielectric layer, the second
contact etch stop layer having a second thickness, a ratio of the
second thickness to the first thickness being between about 1.05
and about 1.15; and patterning the second contact etch stop layer
to remove a portion of the second contact etch stop layer, the
patterned second contact etch stop layer covering the gate
electrode and exposing the silicide region.
17. The method of claim 16, wherein depositing the second contact
etch stop layer comprises depositing the second contact etch stop
layer over a portion of the first interlayer dielectric layer over
the silicide region.
18. The method of claim 16, further comprising depositing a second
interlayer dielectric layer over the first interlayer dielectric
layer, wherein a first portion of the second interlayer dielectric
layer contacts the first interlayer dielectric layer.
19. The method of claim 18, wherein depositing the second
interlayer dielectric layer comprises depositing a second portion
of the second interlayer dielectric layer over the second contact
etch stop layer, and the second contact etch stop layer is between
the second portion of the second interlayer dielectric layer and
the first interlayer dielectric layer.
20. The method of claim 16, further comprising etching the
patterned second contact etch stop layer to expose a portion of a
top surface of the gate electrode, wherein the portion of the top
surface of the gate electrode is less than an entirety of the top
surface of the gate electrode.
Description
TECHNICAL FIELD
The disclosure relates to integrated circuit fabrication, and more
particularly to a field effect transistor with contact etch stop
layers.
BACKGROUND
As the technology nodes shrink, in some integrated circuit (IC)
designs, there has been a desire to replace the typically
polysilicon gate electrode with a metal gate electrode to improve
device performance with the decreased feature sizes. One process of
forming a metal gate structure is termed a "gate last" process in
which the final gate structure is fabricated "last" which allows
for reduced number of subsequent processes, including high
temperature processing, that must be performed after formation of
the gate. Additionally, as the dimensions of transistors decrease,
the thickness of the gate oxide must be reduced to maintain
performance with the decreased gate length. In order to reduce gate
leakage, high-dielectric-constant (high-k) gate dielectric layers
are also used which allow greater physical thicknesses while
maintaining the same effective thickness as would be provided by a
thinner layer of the gate oxide used in larger technology
nodes.
However, there are challenges to implementing such features and
processes in complementary metal-oxide-semiconductor (CMOS)
fabrication. As the gate length and spacing between devices
decrease, these problems are exacerbated. For example, recess in a
metal gate structure may be generated during contact etching due to
low etch selectivity between the metal gate structure and a contact
etch stop layer. Accordingly, what is needed is an improved device
and method of metal gate structure protection.
BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure is best understood from the following
detailed description when read with the accompanying figures. It is
emphasized that, in accordance with the standard practice in the
industry, various features are not drawn to scale and are used for
illustration purposes only. In fact, the dimensions of the various
features in the drawings may be arbitrarily increased or reduced
for clarity of discussion.
FIG. 1 is a flowchart illustrating a method for fabricating a field
effect transistor comprising contact etch stop layers according to
various aspects of the present disclosure; and
FIGS. 2A-H show schematic cross-sectional views of contact etch
stop layers of a field effect transistor at various stages of
fabrication according to various aspects of the present
disclosure.
DESCRIPTION
It is understood that the following disclosure provides many
different embodiments, or examples, for implementing different
features of the invention. Specific examples of components and
arrangements are described below to simplify the present
disclosure. These are, of course, merely examples and are not
intended to be limiting. For example, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed between the first and second
features, such that the first and second features may not be in
direct contact. Various features may be arbitrarily drawn in
different scales for simplicity and clarity. In addition, the
present disclosure provides examples based on a "gate last" metal
gate structure, however, one skilled in the art may recognize
applicability to other structures and/or use of other
materials.
FIG. 1 is a flowchart illustrating a method 100 for fabricating a
field effect transistor 200 comprising contact etch stop layers
224, 234 (shown in FIGS. 2C through 2H) according to various
aspects of the present disclosure. FIGS. 2A-H show schematic
cross-sectional views of contact etch stop layers 224, 234 of a
field effect transistor 200 at various stages of fabrication
according to various aspects of the present disclosure. The field
effect transistor of FIG. 1 may be further processed using CMOS
technology processing. Accordingly, it is understood that
additional processes may be provided before, during, and after the
method 100 of FIG. 1, and that some other processes may only be
briefly described herein. Also, FIGS. 1 through 2H are simplified
for a better understanding of the inventive concepts of the present
disclosure. For example, although the figures illustrate the
contact etch stop layers 224, 234 of a field effect transistor 200,
it is understood the field effect transistor may be part of an IC
that further comprises a number of other devices such as resistors,
capacitors, inductors, fuses, etc.
Referring to FIGS. 1 and 2A, the method 100 begins at step 102
wherein a gate structure 220 comprising sidewalls 220s and a top
surface 220t over a substrate 202 is provided. In at least one
embodiment, the substrate 202 may comprise a silicon substrate. In
some alternative embodiments, the substrate 202 may comprise
silicon germanium, gallium arsenic, or other suitable semiconductor
materials. The substrate 202 may further comprise other features
such as various doped regions, a buried layer, and/or an epitaxy
layer. Furthermore, the substrate 202 may be a semiconductor on
insulator such as silicon on insulator (SOI) or silicon on
sapphire. In some other embodiments, the substrate 202 may comprise
a doped epi layer, a gradient semiconductor layer, and/or may
further include a semiconductor layer overlying another
semiconductor layer of a different type such as a silicon layer on
a silicon germanium layer. In other examples, a compound
semiconductor substrate 202 may comprise a multilayer silicon
structure or a silicon substrate may include a multilayer compound
semiconductor structure. The substrate 202 comprises a surface
202s.
In some embodiments, the substrate 202 may further comprise active
regions 204 and isolation regions 206. The active regions 204 may
include various doping configurations depending on design
requirements as known in the art. In some embodiments, the active
region 204 may be doped with p-type or n-type dopants. For example,
the active regions 204 may be doped with p-type dopants, such as
boron or BF.sub.2; n-type dopants, such as phosphorus or arsenic;
and/or combinations thereof. The active regions 204 may be
configured for an N-type metal-oxide-semiconductor transistor
device (referred to as an NMOS), or alternatively configured for a
P-type metal-oxide-semiconductor transistor device (referred to as
a PMOS).
In some embodiments, the isolation regions 206 may be formed on the
substrate 202 to isolate the various active regions 204. The
isolation regions 206 may utilize isolation technology, such as
local oxidation of silicon (LOCOS) or shallow trench isolation
(STI), to define and electrically isolate the various active
regions 204. In at least one embodiment, the isolation region 206
includes a STI. The isolation regions 206 may comprise silicon
oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate
glass (FSG), a low-K dielectric material, other suitable materials,
and/or combinations thereof. The isolation regions 206, and in the
present embodiment, the STI, may be formed by any suitable process.
As one example, the formation of the STI may include patterning the
semiconductor substrate 202 by a conventional photolithography
process, etching a trench in the substrate 202 (for example, by
using a dry etching, wet etching, and/or plasma etching process),
and filling the trench (for example, by using a chemical vapor
deposition process) with a dielectric material. In some
embodiments, the filled trench may have a multi-layer structure
such as a thermal oxide liner layer filled with silicon nitride or
silicon oxide.
Then, a gate dielectric layer 212 is formed over the substrate 202.
In some embodiments, the gate dielectric layer 212 may comprise
silicon oxide, high-k dielectric material or combination thereof. A
high-k dielectric material is defined as a dielectric material with
a dielectric constant greater than that of SiO.sub.2. The high-k
dielectric layer comprises metal oxide. In some embodiments, the
metal oxide is selected from the group consisting of oxides of Li,
Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb,
Dy, Ho, Er, Tm, Yb, Lu, or mixtures thereof. The gate dielectric
layer 212 may be grown by a thermal oxidation process, a chemical
vapor deposition (CVD) process, an atomic layer deposition (ALD)
process, and may have a thickness less than 2 nm.
In some embodiments, the gate dielectric layer 212 may further
comprise an interfacial layer (not shown) to minimize stress
between the gate dielectric layer 212 and the substrate 202. The
interfacial layer may be formed of silicon oxide or silicon
oxynitride grown by a thermal oxidation process. For example, the
interfacial layer can be grown by a rapid thermal oxidation (RTO)
process or in an annealing process comprising oxygen.
Then, a dummy gate electrode layer 214 may be formed over the gate
dielectric layer 212. In some embodiments, the dummy gate electrode
layer 214 may comprise a single layer or multilayer structure. In
the present embodiment, the dummy gate electrode layer 214 may
comprise poly-silicon. Further, the dummy gate electrode layer 214
may be doped poly-silicon with the uniform or gradient doping. The
dummy gate electrode layer 214 may have any suitable thickness. In
the present embodiment, the dummy gate electrode layer 214 has a
thickness in the range of about 30 nm to about 60 nm. In some
embodiments, the dummy gate electrode layer 214 may be formed using
a low-pressure chemical vapor deposition (LPCVD) process. In at
least one embodiment, the LPCVD process can be carried out in a
LPCVD furnace at a temperature of about 580.degree. C. to
650.degree. C. and at a pressure of about 200 mTorr to 1 Torr,
using silane (SiH.sub.4), disilane (Si.sub.2H.sub.6), trisilane
(Si.sub.3H.sub.8) or dichlorosilane (SiH.sub.2Cl.sub.2) as the
silicon source gas.
And then, in some embodiments, a hard mask layer (not shown) may be
formed over the dummy gate electrode layer 214 to protect the dummy
gate electrode layer 214. The hard mask layer may include silicon
nitride. The hard mask layer can be deposited by, for example, a
CVD process, or a LPCVD process. The hard mask layer may have a
thickness of about 100 to 400 .ANG.. After the hard mask layer is
deposited, the hard mask layer is patterned using a photo-sensitive
layer (not shown). Then the gate structure 220 is patterned through
the hard mask layer using a reactive ion etching (RIE) or a high
density plasma (HDP) process, exposing a portion of the substrate
202, thereby the gate structure 220 comprises sidewalls 220s and a
top surface 220t.
Also shown in FIG. 2A, in some embodiments, after formation of the
gate structure 220, lightly doped source and drain (LDD) regions
208 may be created in the active region 204. This is accomplished
via ion implantation of boron or phosphorous, at an energy between
about 5 to 100 KeV, at a dose between about 1E11 to 1E 14
atoms/cm.sup.2.
Referring to FIGS. 1 and 2B, the method 100 continues with step 104
in which a spacer 222 adjacent to the sidewalls 220s of the gate
structure 220 is formed. The spacer 222 may be formed of silicon
oxide, silicon nitride, silicon oxynitride, silicon carbide,
fluoride-doped silicate glass (FSG), a low k dielectric material,
and/or combinations thereof. The spacers 222 may have a
multiple-layers structure, for example, including one or more liner
layers. The liner layer may include a dielectric material such as
silicon oxide, silicon nitride, and/or other suitable materials.
The spacer 222 may be formed by methods including deposition of
suitable dielectric material and anisotropically etching the
material to form the spacer 222. A width of the spacer 222 may be
in the range of about 6 to 35 nm.
Also shown in FIG. 2B is the creation of a plurality of heavily
doped source and drain (S/D) regions 210 in the active region 204
needed for low resistance contact. This is achieved via ion
implantation of boron or phosphorous, at an energy level between
about 5 to 150 KeV, at a dose between about 1E15 to 1E 16
atoms/cm.sup.2.
Still referring to FIGS. 1 and 2B, the method 100 continues with
step 106 in which silicide regions 230 in the substrate 202 on
sides of the gate structure 220 are formed. In some embodiments,
the silicide regions 230 may be formed on the S/D regions 210 by a
self-aligned silicide (salicide) process. For example, the salicide
process may comprise 2 steps. First, a metal material may be
deposited via sputtering to the substrate surface 202s at a
temperature between 500.degree. C. to 900.degree. C., causing a
reaction between the underlying silicon and metal material to form
the silicide regions 230. And then, the un-reacted metal material
may be etched away. The silicide regions 230 may comprise a
material selected from titanium silicide, cobalt silicide, nickel
silicide, platinum silicide, erbium silicide, or palladium
silicide. A thickness of the silicide regions 230 is in the range
of about 30 to 50 nm.
The method 100 in FIG. 1 continues with step 108 in which the
structure in FIG. 2C is produced by depositing a first contact etch
stop layer 224 over the spacer 222 and the top surface 220t of the
gate structure 220 and extending along the surface 202s of the
substrate 202. The first contact etch stop layer 224 may comprise,
but is not limited to, silicon nitride or carbon-doped silicon
nitride. The first contact etch stop layer 224 may have any
suitable thickness. In some embodiments, the first contact etch
stop layer 224 has a thickness t.sub.1 in the range of about 180 to
about 220 angstroms.
In some embodiments, the first contact etch stop layer 224 may be
deposited using CVD, high density plasma (HDP) CVD, sub-atmospheric
CVD (SACVD), molecular layer deposition (MLD), sputtering, or other
suitable methods. For example, in some embodiments, the MLD process
is generally carried out under a pressure less than 10 mTorr and in
the temperature range from about 350.degree. C. to 500.degree. C.
In at least one embodiment, the silicon nitride is deposited on the
spacer 222 and the top surface 220t of the gate structure 220 by
reacting a silicon source compound and a nitrogen source. The
silicon source compound provides silicon to the deposited silicon
nitride and may be silane (SiH.sub.4) or tetrathoxysilane (TEOS).
The nitrogen source provides nitrogen to the deposited silicon
nitride and may be ammonia (NH.sub.3) or nitrogen gas (N.sub.2). In
another embodiment, the carbon-doped silicon nitride is deposited
on the spacer 222 and the top surface 220t of the gate structure
220 by reacting a carbon source compound, a silicon source
compound, and a nitrogen source. The carbon source compound may be
an organic compound, such as a hydrocarbon compound, e.g., ethylene
(C.sub.2H.sub.6).
The method 100 in FIG. 1 continues with step 110 in which the
structure in FIG. 2C is produced by further depositing a first
interlayer dielectric (ILD) layer 226 over the first contact etch
stop layer 224. The first ILD layer 226 may comprise a dielectric
material. The dielectric material may comprise silicon oxide,
silicon nitride, silicon oxynitride, phosphosilicate glass (PSG),
borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated
silica glass (FSG), carbon doped silicon oxide (e.g., SiCOH), BLACK
DIAMOND.RTM. (Applied Materials of Santa Clara, Calif.), Xerogel,
Aerogel, amorphous fluorinated carbon, Parylene, BCB
(bis-benzocyclobutenes), Flare, SILK.RTM. (Dow Chemical, Midland,
Mich.), polyimide, and/or combinations thereof. It is understood
that the first ILD layer 226 may comprise one or more dielectric
materials and/or one or more dielectric layers. In some
embodiments, the first ILD layer 226 may be deposited over the
first contact etch stop layer 224 to a suitable thickness by CVD,
high density plasma (HDP) CVD, sub-atmospheric CVD (SACVD),
spin-on, sputtering, or other suitable methods. In the present
embodiment, the first ILD layer 226 comprises a thickness of about
3000 to 4500 .ANG..
The method 100 in FIG. 1 continues with step 112 in which the
structure in FIG. 2D is produced by performing a chemical
mechanical polishing (CMP) on the first interlayer dielectric (ILD)
layer 226 and first contact etch stop layer 224 to expose the top
surface 220t of the gate structure 220. In a gate last process, the
dummy gate electrode layer 214 may be removed so that a resulting
metal gate electrode layer 216 may be formed in place of the dummy
gate electrode layer 214. Accordingly, the ILD layer 226 is
planarized using a CMP process until the top surface 220t of the
dummy gate electrode layer 214 is exposed or reached. The CMP
process may have a high selectivity to provide a substantially
planar surface for the dummy gate electrode layer 214, spacer 222,
first contact etch stop layer 224, and ILD layer 226. Thus, a top
surface 226t of the ILD layer 226 is coplanar with the top surface
220t of the gate structure 220. The CMP process may also have low
dishing and/or erosion effect. In some alternative embodiments, the
CMP process may be performed to expose the hard mask layer and then
an etching process such as a wet etch dip may be applied to remove
the hard mask layer thereby exposing the top surface 220t of the
dummy gate electrode layer 214.
After the CMP process, a gate replacement process is performed. The
dummy gate electrode layer 214 may be removed from the gate
structure 220 surrounded with dielectric comprising the spacer 222,
first contact etch stop layer 224, and ILD layer 226. The dummy
gate electrode layer 214 may be removed to form a trench in the
gate structure 220 by any suitable process, including the processes
described herein. In some embodiments, the dummy gate electrode
layer 214 may be removed using a wet etch and/or a dry etch
process. In at least one embodiment, the wet etch process for the
dummy poly-silicon gate electrode layer 214 comprises exposure to a
hydroxide containing solution (e.g., ammonium hydroxide), deionized
water, and/or other suitable etchant solutions.
Next the dummy gate electrode layer 214 is removed, which results
in the formation of a trench (not shown). A metal layer may be
formed to fill in the trench. The metal layer may include any metal
material suitable for forming a metal gate electrode layer 216 or
portion thereof, including barriers, work function layers, liner
layers, interface layers, seed layers, adhesion layers, barrier
layers, etc. In some embodiments, the metal layer may include
suitable metals, such as TiN, WN, TaN, or Ru that properly perform
in the PMOS device. In some alternative embodiments, the metal
layer may include suitable metals, such as Ti, Ag, Al, TiAl, TiAlN,
TaC, TaCN, TaSiN, Mn, or Zr that properly perform in the NMOS
device. Another CMP is performed on the metal layer to form the
metal gate electrode layer 216 of the semiconductor devices 200.
For simplicity and clarity, the metal gate electrode layer 216 and
gate dielectric layer 212 are hereinafter also referred to as a
gate structure 220.
In some embodiments, it is desirable to protect the metal gate
structure 220 from being damaged during contact etching. The method
100 in FIG. 1 continues with step 114 in which the structure in
FIG. 2E is produced by depositing a second contact etch stop layer
234 over the first ILD layer 226 and the top surface 220t of the
gate structure 220. The second contact etch stop layer 234 will
protect the gate structure 220 during contact etching. The second
contact etch stop layer 234 may comprise, but is not limited to,
silicon nitride or carbon-doped silicon nitride. The second contact
etch stop layer 234 may have any suitable thickness. In the present
embodiment, the second contact etch stop layer 234 has a thickness
t.sub.2 in the range of about 190 to about 250 angstroms. In at
least one embodiment, the thickness t.sub.1 of the first contact
etch stop layer 224 is less than the thickness t.sub.2 of the
second contact etch stop layer 234. In some embodiments, A ratio of
the thickness t.sub.2 of the second contact etch stop layer 234 to
the thickness t.sub.1 of the first contact etch stop layer 224 is
from 1.05 to 1.15. In some other embodiment, a thickness t.sub.1 of
the first contact etch stop layer 224 may be greater than a
thickness t.sub.2 of the second contact etch stop layer 234 for
capacitance reduction if some metal gate electrode layer 216 loss
is acceptable.
In some embodiments, the second contact etch stop layer 234 may be
deposited using CVD, high density plasma (HDP) CVD, sub-atmospheric
CVD (SACVD), molecular layer deposition (MLD), sputtering, or other
suitable methods. For example, in at least one embodiment, the MLD
process is generally carried out under a pressure less than 10
mTorr and in the temperature range from about 350.degree. C. to
500.degree. C. In some embodiments, the silicon nitride is
deposited on the ILD layer 226 and the top surface 220t of the gate
structure 220 by reacting a silicon source compound and a nitrogen
source. The silicon source compound provides silicon to the
deposited silicon nitride and may be silane (SiH.sub.4) or
tetrathoxysilane (TEOS). The nitrogen source provides nitrogen to
the deposited silicon nitride and may be ammonia (NH.sub.3) or
nitrogen gas (N.sub.2). In some other embodiments, the carbon-doped
silicon nitride is deposited on the ILD layer 226 and the top
surface 220t of the gate structure 220 by reacting a carbon source
compound, a silicon source compound, and a nitrogen source. The
carbon source compound may be an organic compound, such as a
hydrocarbon compound, e.g., ethylene (C.sub.2H.sub.6).
In the present embodiment, the first and second contact etch stop
layers 224, 234 comprise the same material. In some alternative
embodiments, the first and second contact etch stop layers 224, 234
comprise different materials. For example, in certain embodiments,
the first contact etch stop layer 224 is silicon nitride, the
second contact etch stop layer 234 is carbon-doped silicon nitride,
and vice versa.
Then, a patterned photo-sensitive layer 250 is formed on the second
contact etch stop layer 234. For example, the patterned
photo-sensitive layer 250 may be formed using processes such as,
spin-coating, photolithography processes including exposure, bake,
and development processes, etching (including ashing or stripping
processes), and/or other processes. The patterned photo-sensitive
layer 250 is sensitive to particular exposure beam such KrF, ArF,
EUV or e-beam light. In at least one example, the patterned
photo-sensitive layer includes polymers, quencher, chromophore,
solvent and/or chemical amplifier (CA). In the present embodiment,
the patterned photo-sensitive layer 250 exposes a portion of the
silicide regions 230 for contact formation in the S/D regions 210.
The width W.sub.1 of photo-sensitive layer 250 is greater than a
width W.sub.2 of the gate structure 220.
The method 100 in FIG. 1 continues with step 116 in which the
structure in FIG. 2F is produced by patterning the second contact
etch stop layer 234 to remove a portion of the second contact etch
stop layer 234 over the silicide regions 230, whereby the second
contact etch stop layer 234 remains over the gate structure 220 but
does not extend as far as up to the silicide regions 230. In some
embodiments, the second contact etch stop layer 234 is patterned
through the photo-sensitive layer 250 using a dry etching process,
exposing a portion of the ILD layer 226, thereby a width W.sub.3 of
second contact etch stop layer 234 is greater than the width
W.sub.2 of the gate structure 220. The dry etching process may have
a high selectivity such that the dry etching process may stop at
the ILD layer 226. For example, the dry etching process may be
performed under a source power of about 150 to 220 W, and a
pressure of about 10 to 45 mTorr, using CH.sub.2F.sub.2 and Ar as
etching gases.
In the present embodiment, the second contact etch stop layer 234
comprises a portion extending on the top surface 220t of the gate
structure 220. The second contact etch stop layer 234 in this
embodiment further comprises a portion extending on a top surface
224t of the first contact etch stop layer 224. The second contact
etch stop layer 234 in this embodiment further comprises a portion
extending on the top surface 226t of the ILD layer 226.
Subsequent CMOS processing steps applied to the semiconductor
device 200 of FIG. 2F may comprise forming contact holes through
the first and second contact etch stop layers 224, 234 to provide
electrical contacts to the gate structure 220 and/or S/D regions
210. Referring to FIG. 2G, contact holes 238 may be formed by any
suitable process. As one example, the formation of the contact
holes 238 may include depositing a second interlayer dielectric
(ILD) layer 236 over the first ILD layer 226 and second contact
etch stop layer 234, patterning the second ILD layer 236 by a
photolithography process, etching the exposed second ILD layer 236
(for example, by using a dry etching, wet etching, and/or plasma
etching process) to remove portions of the second interlayer
dielectric layer 236 over a portion of the silicide region 230 and
a portion of the gate structure 220 to expose portions of the first
and second contact etch stop layers 224, 234.
In the present embodiment, the second ILD layer 236 may comprise a
dielectric material. The dielectric material may comprise silicon
oxide, silicon nitride, silicon oxynitride, phosphosilicate glass
(PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG),
fluorinated silica glass (FSG), carbon doped silicon oxide (e.g.,
SiCOH), BLACK DIAMOND.RTM. (Applied Materials of Santa Clara,
Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene,
BCB (bis-benzocyclobutenes), Flare, SILK.RTM. (Dow Chemical,
Midland, Mich.), polyimide, and/or combinations thereof. It is
understood that the second ILD layer 236 may comprise one or more
dielectric materials and/or one or more dielectric layers. In some
embodiments, the second ILD layer 236 may be deposited over the
first ILD layer 226 and second contact etch stop layers 234 to a
suitable thickness by CVD, HDP CVD, SACVD, spin-on, sputtering, or
other suitable methods. In the present embodiment, the second ILD
layer 236 comprises a thickness of about 3000 to 4500 .ANG..
Referring to FIG. 2H, the exposed portions of the first and second
contact etch stop layers 224, 234 are removed to expose the gate
structure 220 and silicide region 230. In the present embodiment,
the first and second contact etch stop layers 224, 234 are
simultaneously removed using a dry etching process. The dry etching
process may have a high selectivity such that the dry etching
process may stop at the gate structure 220 and silicide region 230.
For example, the dry etching process may be performed under a
source power of about 150 to 220 W, and a pressure of about 10 to
45 mTorr, using CH.sub.2F.sub.2 and Ar as etching gases. Therefore,
unwanted etching of the metal gate structure 220 may be reduced
during contact etching due to the introduction of the second
contact etch stop layer 234 over the metal gate structure 220.
Accordingly, the disclosed methods of fabricating contact etch stop
layers of the semiconductor device 200 may fabricate a metal gate
structure 220 without a recess caused by the contact etch, thereby
enhancing the device performance.
Then, in some embodiments, subsequent processes, including
interconnect processing, are performed after forming the
semiconductor device 200 to complete the IC fabrication.
One aspect of this description relates to a method for fabricating
a field-effect transistor. The method includes forming a spacer
adjacent to sidewalls of a gate structure. The method further
includes forming silicide regions in a substrate adjacent to the
spacer. The method further includes depositing a first interlayer
dielectric layer over the substrate. The method further includes
exposing a top surface of the gate structure. The method further
includes depositing a contact etch stop layer over the first
interlayer dielectric layer and the top surface of the gate
structure. The method further includes patterning the contact etch
stop layer to remove a portion of the contact etch stop layer over
the silicide regions, wherein the contact etch stop layer over the
gate structure is maintained.
Another aspect of this description relates to a method for
fabricating a transistor. The method includes depositing a first
contact etch stop layer over a top surface of a gate structure, a
spacer adjacent to a sidewall of the gate structure, and a silicide
region adjacent to the spacer. The method further includes
depositing a first interlayer dielectric layer over the first
contact etch stop layer. The method further includes exposing a
portion of the gate structure; and depositing a second contact etch
stop layer over the first interlayer dielectric layer. The method
further includes patterning the second contact etch stop layer to
remove a portion of the second contact etch stop layer, the portion
of the second contact etch stop layer being directly over the
silicide region.
Still another aspect of this description relates to a method for
fabricating a transistor. The method includes depositing a first
contact etch stop layer over a gate structure of the transistor and
a silicide region of the transistor, the gate structure comprising
a dummy gate electrode. The method further includes depositing a
first interlayer dielectric layer over the first contact etch stop
layer. The method further includes exposing the dummy gate
electrode; and replacing the dummy gate electrode with a gate
electrode. The method further includes depositing a second contact
etch stop layer over the first interlayer dielectric layer. The
method further includes patterning the second contact etch stop
layer to remove a portion of the second contact etch stop layer,
the patterned second contact etch stop layer covering the gate
electrode and exposing the silicide region.
While the invention has been described by way of example and in
terms of the various embodiments, it is to be understood that the
invention is not limited to the disclosed embodiments. To the
contrary, it is intended to cover various modifications and similar
arrangements (as would be apparent to those skilled in the art).
Therefore, the scope of the appended claims should be accorded the
broadest interpretation so as to encompass all such modifications
and similar arrangements. The invention can be used to form or
fabricate metal gate structures for a semiconductor device. In this
way, metal gate structures with less recess for a semiconductor
device may be formed.
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