U.S. patent number 9,853,133 [Application Number 14/835,155] was granted by the patent office on 2017-12-26 for method of manufacturing high resistivity silicon-on-insulator substrate.
This patent grant is currently assigned to SunEdison Semiconductor Limited (UEN201334164H). The grantee listed for this patent is SunEdison Semiconductor Limited (UEN201334164H). Invention is credited to Qingmin Liu, Shawn George Thomas.
United States Patent |
9,853,133 |
Thomas , et al. |
December 26, 2017 |
Method of manufacturing high resistivity silicon-on-insulator
substrate
Abstract
A multilayer composite structure and a method of preparing a
multilayer composite structure are provided. The multilayer
composite structure comprises a semiconductor handle substrate
having a minimum bulk region resistivity of at least about 500
ohm-cm; a silicon dioxide layer on the surface of the semiconductor
handle substrate; a carbon-doped amorphous silicon layer in contact
with the silicon dioxide layer; a dielectric layer in contact with
the carbon-doped amorphous silicon layer; and a semiconductor
device layer in contact with the dielectric layer.
Inventors: |
Thomas; Shawn George
(Chesterfield, MO), Liu; Qingmin (Glen Carbon, IL) |
Applicant: |
Name |
City |
State |
Country |
Type |
SunEdison Semiconductor Limited (UEN201334164H) |
Singapore |
N/A |
SG |
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Assignee: |
SunEdison Semiconductor Limited
(UEN201334164H) (Singapore, SG)
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Family
ID: |
54147279 |
Appl.
No.: |
14/835,155 |
Filed: |
August 25, 2015 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20160071959 A1 |
Mar 10, 2016 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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62045605 |
Sep 4, 2014 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
21/324 (20130101); H01L 21/76254 (20130101); H01L
29/4916 (20130101); H01L 29/518 (20130101); H01L
21/31 (20130101); H01L 21/283 (20130101); H01L
29/66833 (20130101); H01L 21/02002 (20130101); H01L
29/0649 (20130101); H01L 29/792 (20130101); H01L
29/517 (20130101); H01L 21/304 (20130101) |
Current International
Class: |
H01L
29/66 (20060101); H01L 21/31 (20060101); H01L
29/792 (20060101); H01L 29/06 (20060101); H01L
21/283 (20060101); H01L 21/324 (20060101); H01L
21/304 (20060101); H01L 29/49 (20060101); H01L
21/762 (20060101); H01L 29/51 (20060101); H01L
21/02 (20060101) |
Field of
Search: |
;438/455,458,471,473-476,480,514,515,522,526-528,530,558,795,799,974
;257/E21.561,E21.567,E21.568,E21.57 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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0939430 |
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Jan 1999 |
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EP |
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2009120407 |
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Oct 2009 |
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WO |
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Other References
International Search Report and Written Opinion of the
International Searching Authority regarding PCT/US2015/048041 dated
Dec. 3, 2015; 12 pgs. cited by applicant .
Gamble, H. S. et al., Low-loss CPW Lines on Surface Stabilized
High-Resistivity Silicon, IEEE Microwave and Guided Wave Letters,
Oct. 1999, pp. 395-397, vol. 9, No. 10. cited by applicant .
Lederer, D. et al., Enhanced High resistivity SOI wafers for RF
applications, 2004 IEEE International SOI Conference, Oct. 2004,
pp. 46-47. cited by applicant .
Lederer, D. et al., New Substrate Passivation Method Dedicated to
HR SOI Wafer Fabrication With Increased Substrate Resistivity, IEEE
Electron Device Letters, Nov. 2005, pp. 805-807, vol. 26, No. 11.
cited by applicant .
Lederer, D. et. al, Performance of SOI devices transferred onto
passivated HR SOI substrates using a layer transfer technique, 2006
IEEE International SOI Conference Proceedings, 2006, pp. 29-30.
cited by applicant .
Kerr, Daniel C., Identification of RF harmonic distortion of Si
substrates and its reduction using a trap-rich layer, IEEE (IEEE
Topical Meeting), 2008, pp. 151-154. cited by applicant .
Huran, J. et al., Amorphous silicon carbide thin films deposited by
plasma enhanced chemical vapor deposition at different temperature
for hard environment applications, 21st International Symposium on
Plasma Chemistry, Aug. 4-9, 2013, pp. 1-5. cited by applicant .
Janz, Stefan, Amorphous Silicon Carbide for Photovoltaic
Applications, Dissertation, 2006, pp. 1-227, Fraunhofer Institut
fur Solare Energiesysteme, Freiburg. cited by applicant .
Liao, F. et al., High-rate chemical vapor deposition of
nanocrystalline silicon carbide films by radio frequency thermal
plasma, Materials Letters, 2003, vol. 57, pp. 1982-1986, Elsevier.
cited by applicant .
Fan, J. et al., General Properties of Bulk SiC, Chapter 2,
Engineering Materials and Processes, 2014, pp. 7-114, Springer
international Publishing, Switzerland. cited by applicant.
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Primary Examiner: Malek; Maliheh
Attorney, Agent or Firm: Armstrong Teasdale LLP
Parent Case Text
CROSS REFERENCE TO RELATED APPLICATION(S)
This application claims the benefit of provisional application Ser.
No. 62/045,605, filed Sep. 4, 2014, which is hereby incorporated by
reference as if set forth in its entirety.
Claims
What is claimed is:
1. A multilayer structure comprising: a semiconductor handle
substrate comprising two major, generally parallel surfaces, one of
which is a front surface of the semiconductor handle substrate and
the other of which is a back surface of the semiconductor handle
substrate, a circumferential edge joining the front and back
surfaces of the semiconductor handle substrate, and a bulk region
between the front and back surfaces of the semiconductor handle
substrate, wherein the semiconductor handle substrate has a bulk
region resistivity between 2000 Ohm-cm and about 100,000 Ohm-cm; an
interfacial layer in contact with the front surface of the
semiconductor handle substrate wherein the interfacial layer
comprises a material selected from the group consisting of silicon
dioxide, silicon nitride, and silicon oxynitride; a carbon-doped
amorphous silicon layer in contact with the interfacial layer,
wherein the carbon-doped amorphous silicon layer has an average
thickness of between about 25 nanometers and about 7500 nanometers
and further wherein the carbon-doped amorphous silicon layer
comprises a carbon concentration between about 1% and 10% on an
atomic basis; a dielectric layer in contact with the carbon-doped
amorphous silicon layer; and a semiconductor device layer in
contact with the dielectric layer.
2. The multilayer structure of claim 1 wherein the semiconductor
handle substrate comprises silicon.
3. The multilayer structure of claim 1 wherein the semiconductor
handle substrate comprises a silicon wafer sliced from a single
crystal silicon ingot grown by the Czochralski method or the float
zone method.
4. The multilayer structure of claim 1 wherein the semiconductor
handle substrate has a bulk resistivity between about 2000 Ohm cm
and about 10,000 Ohm-cm.
5. The multilayer structure of claim 1 wherein the crystalline
semiconductor handle substrate has a bulk resistivity between about
3000 Ohm-cm and about 10,000 Ohm-cm.
6. The multilayer structure of claim 1 wherein the semiconductor
handle substrate has a bulk resistivity between about 3000 Ohm cm
and about 5,000 Ohm-cm.
7. The multilayer structure of claim 1 wherein the interfacial
layer comprises silicon nitride or silicon oxynitride.
8. The multilayer structure of claim 1 wherein the interfacial
layer comprises silicon dioxide.
9. The multilayer structure of claim 1 wherein the interfacial
layer has an average thickness between about 1 nanometer and about
5 nanometers.
10. The multilayer structure of claim 1 wherein the interfacial
layer has an average thickness between about 2 nanometers and about
4 nanometers.
11. The multilayer structure of claim 1 wherein the carbon-doped
amorphous silicon layer has an average thickness of between about
50 nanometers and about 5000 nanometers.
12. The multilayer structure of claim 1 wherein the carbon-doped
amorphous silicon layer has an average thickness of between about
100 nanometers and about 3000 nanometers.
13. The multilayer structure of claim 1 wherein the carbon-doped
amorphous silicon layer has an average thickness of between about
500 nanometers and about 2500 nanometers.
14. The multilayer structure of claim 1 wherein the dielectric
layer in contact with the carbon-doped amorphous silicon layer is
selected from the group consisting of silicon dioxide, silicon
nitride, hafnium oxide, titanium oxide, zirconium oxide, Lanthanum
oxide, barium oxide, and a combination thereof.
15. A method of forming a multilayer structure, the method
comprising: forming an interfacial layer on a front surface of a
semiconductor handle substrate, wherein the semiconductor handle
substrate comprises two major, generally parallel surfaces, one of
which is the front surface of the semiconductor handle substrate
and the other of which is a back surface of the semiconductor
handle substrate, a circumferential edge joining the front and back
surfaces of the semiconductor handle substrate, and a bulk region
between the front and back surfaces of the semiconductor handle
substrate, wherein the semiconductor handle substrate has a bulk
region resistivity between 2000 Ohm-cm and about 100,000 Ohm-cm and
the interfacial layer has a thickness between about 1 nanometer and
about 5 nanometers and further wherein the interfacial layer
comprises a material selected from the group consisting of silicon
dioxide, silicon nitride, and silicon oxynitride; forming a
carbon-doped amorphous silicon layer on the interfacial layer on
the front surface of the semiconductor handle substrate, wherein
the carbon-doped amorphous silicon layer has an average thickness
of between about 25 nanometers and about 7500 nanometers and
further wherein the carbon-doped amorphous silicon layer comprises
a carbon concentration between about 1% and 10% on an atomic basis;
and bonding a dielectric layer on a front surface of a
semiconductor donor substrate to the carbon-doped amorphous silicon
layer to thereby form a bonded structure, wherein the semiconductor
donor substrate comprises two major, generally parallel surfaces,
one of which is the front surface of the semiconductor donor
substrate and the other of which is a back surface of the
semiconductor donor substrate, a circumferential edge joining the
front and back surfaces of the semiconductor donor substrate, and a
central plane between the front and back surfaces of the
semiconductor donor substrate.
16. The method of claim 15 wherein the semiconductor handle
substrate comprises a silicon wafer.
17. The method of claim 15 wherein the semiconductor handle
substrate comprises a silicon wafer sliced from a single crystal
silicon ingot grown by the Czochralski method or the float zone
method.
18. The method of claim 15 wherein the semiconductor handle
substrate has a bulk resistivity between about 2000 Ohm cm and
about 10,000 Ohm-cm.
19. The method of claim 15 wherein the crystalline semiconductor
handle substrate has a bulk resistivity between about 3000 Ohm-cm
and about 10,000 Ohm-cm.
20. The method of claim 15 wherein the semiconductor handle
substrate has a bulk resistivity between about 3000 Ohm cm and
about 5,000 Ohm-cm.
21. The method of claim 15 wherein the interfacial layer silicon
nitride or silicon oxynitride.
22. The method of claim 15 wherein the interfacial layer comprises
silicon dioxide.
23. The method of claim 15 wherein the interfacial layer has an
average thickness between about 2 nanometers and about 4
nanometers.
24. The method of claim 15 wherein the carbon-doped amorphous
silicon layer is formed by chemical vapor deposition.
25. The method of claim 15 further comprising forming a silicon
dioxide layer on the carbon-doped amorphous silicon layer before
bonding to the dielectric layer on the front surface of the
semiconductor donor substrate.
26. The method of claim 15 wherein the semiconductor donor
substrate comprises a silicon wafer sliced from a single crystal
silicon ingot grown by the Czochralski method or the float zone
method.
27. The method of claim 15 wherein the semiconductor donor
substrate comprises a silicon wafer sliced from a single crystal
silicon ingot grown by the Czochralski method.
28. The method of claim 15 wherein the dielectric layer is selected
from the group consisting of silicon dioxide, silicon nitride,
hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide,
barium oxide, and any combination thereof.
29. The method of claim 15 further comprising heating the bonded
structure at a temperature and for a duration sufficient to
strengthen the bond between the dielectric layer of the
semiconductor donor structure and the front surface of a
semiconductor handle substrate.
30. The method of claim 15 wherein the semiconductor donor
substrate comprises an ion implanted damage layer.
31. The method of claim 30 further comprising mechanically cleaving
the bonded structure at the ion implanted damage layer of the
semiconductor donor substrate to thereby prepare a cleaved
structure comprising the semiconductor handle substrate, the
interfacial layer, the carbon-doped amorphous silicon layer in
contact with the interfacial layer, the dielectric layer in contact
with the carbon-doped amorphous silicon layer, and a semiconductor
device layer in interfacial contact with the dielectric layer.
32. The method of claim 31 further comprising heating the cleaved
structure at a temperature and for a duration sufficient to
strengthen the bond between the semiconductor device layer and the
single crystal semiconductor handle structure.
Description
FIELD OF THE INVENTION
The present invention generally relates to the field of
semiconductor wafer manufacture. More specifically, the present
invention relates to a method for producing a
semiconductor-on-insulator (e.g., silicon-on-insulator) structure,
and more particularly to a method for producing a charge trapping
layer in the handle wafer of the semiconductor-on-insulator
structure.
BACKGROUND OF THE INVENTION
Semiconductor wafers are generally prepared from a single crystal
ingot (e.g., a silicon ingot) which is trimmed and ground to have
one or more flats or notches for proper orientation of the wafer in
subsequent procedures. The ingot is then sliced into individual
wafers. While reference will be made herein to semiconductor wafers
constructed from silicon, other materials may be used to prepare
semiconductor wafers, such as germanium, silicon carbide, silicon
germanium, or gallium arsenide.
Semiconductor wafers (e.g., silicon wafers) may be utilized in the
preparation of composite layer structures. A composite layer
structure (e.g., a semiconductor-on-insulator, and more
specifically, a silicon-on-insulator (SOI) structure) generally
comprises a handle wafer or layer, a device layer, and an
insulating (i.e., dielectric) film (typically an oxide layer)
between the handle layer and the device layer. Generally, the
device layer is between 0.01 and 20 micrometers thick. In general,
composite layer structures, such as silicon-on-insulator (SOI),
silicon-on-sapphire (SOS), and silicon-on-quartz, are produced by
placing two wafers in intimate contact, followed by a thermal
treatment to strengthen the bond.
After thermal anneal, the bonded structure undergoes further
processing to remove a substantial portion of the donor wafer to
achieve layer transfer. For example, wafer thinning techniques,
e.g., etching or grinding, may be used, often referred to as back
etch SOI (i.e., BESOI), wherein a silicon wafer is bound to the
handle wafer and then slowly etched away until only a thin layer of
silicon on the handle wafer remains. See, e.g., U.S. Pat. No.
5,189,500, the disclosure of which is incorporated herein by
reference as if set forth in its entirety. This method is
time-consuming and costly, wastes one of the substrates and
generally does not have suitable thickness uniformity for layers
thinner than a few microns.
Another common method of achieving layer transfer utilizes a
hydrogen implant followed by thermally induced layer splitting.
Particles (e.g., hydrogen atoms or a combination of hydrogen and
helium atoms) are implanted at a specified depth beneath the front
surface of the donor wafer. The implanted particles form a cleave
plane in the donor wafer at the specified depth at which they were
implanted. The surface of the donor wafer is cleaned to remove
organic compounds deposited on the wafer during the implantation
process.
The front surface of the donor wafer is then bonded to a handle
wafer to form a bonded wafer through a hydrophilic bonding process.
Prior to bonding, the donor wafer and/or handle wafer are activated
by exposing the surfaces of the wafers to plasma containing, for
example, oxygen or nitrogen. Exposure to the plasma modifies the
structure of the surfaces in a process often referred to as surface
activation, which activation process renders the surfaces of one or
both of the donor water and handle wafer hydrophilic. The wafers
are then pressed together, and a bond is formed there between. This
bond is relatively weak, and must be strengthened before further
processing can occur.
In some processes, the hydrophilic bond between the donor wafer and
handle wafer (i.e., a bonded wafer) is strengthened by heating or
annealing the bonded wafer pair. In some processes, wafer bonding
may occur at low temperatures, such as between approximately
300.degree. C. and 500.degree. C. In some processes, wafer bonding
may occur at high temperatures, such as between approximately
800.degree. C. and 1100.degree. C. The elevated temperatures cause
the formation of covalent bonds between the adjoining surfaces of
the donor wafer and the handle wafer, thus solidifying the bond
between the donor wafer and the handle wafer. Concurrently with the
heating or annealing of the bonded wafer, the particles earlier
implanted in the donor wafer weaken the cleave plane.
A portion of the donor wafer is then separated (i.e., cleaved)
along the cleave plane from the bonded wafer to form the SOI wafer.
Cleaving may be carried out by placing the bonded wafer in a
fixture in which mechanical force is applied perpendicular to the
opposing sides of the bonded wafer in order to pull a portion of
the donor wafer apart from the bonded wafer. According to some
methods, suction cups are utilized to apply the mechanical force.
The separation of the portion of the donor wafer is initiated by
applying a mechanical wedge at the edge of the bonded wafer at the
cleave plane in order to initiate propagation of a crack along the
cleave plane. The mechanical force applied by the suction cups then
pulls the portion of the donor wafer from the bonded wafer, thus
forming an SOI wafer.
According to other methods, the bonded pair may instead be
subjected to an elevated temperature over a period of time to
separate the portion of the donor wafer from the bonded wafer.
Exposure to the elevated temperature causes initiation and
propagation of a crack along the cleave plane, thus separating a
portion of the donor wafer. This method allows for better
uniformity of the transferred layer and allows recycle of the donor
wafer, but typically requires heating the implanted and bonded pair
to temperatures approaching 500.degree. C.
The use of high resistivity semiconductor-on-insulator (e.g.,
silicon-on-insulator) wafers for RF related devices such as antenna
switches offers benefits over traditional substrates in terms of
cost and integration. To reduce parasitic power loss and minimize
harmonic distortion inherent when using conductive substrates for
high frequency applications it is necessary, but not sufficient, to
use substrate wafers with a high resistivity. Accordingly, the
resistivity of the handle wafer for an RF device is generally
greater than about 500 Ohm-cm. With reference now to FIG. 1, a
silicon on insulator structure 2 comprising a very high resistivity
silicon wafer 4, a buried oxide (BOX) layer 6, and a silicon device
layer 10. Such a substrate is prone to formation of high
conductivity charge inversion or accumulation layers 12 at the
BOX/handle interface causing generation of free carriers (electrons
or holes), which reduce the effective resistivity of the substrate
and give rise to parasitic power losses and device nonlinearity
when the devices are operated at RF frequencies. These
inversion/accumulation layers can be due to BOX fixed charge, oxide
trapped charge, interface trapped charge, and even DC bias applied
to the devices themselves.
A method is required therefore to trap the charge in any induced
inversion or accumulation layers so that the high resistivity of
the substrate is maintained even in the very near surface region.
It is known that charge trapping layers (CTL) between the high
resistivity handle substrates and the buried oxide (BOX) may
improve the performance of RF devices fabricated using SOI wafers.
A number of methods have been suggested to form these high
interface trap layers. For example, with reference now to FIG. 2,
one of the method of creating a semiconductor-on-insulator 20
(e.g., a silicon-on-insulator, or SOI) with a CTL for RF device
applications is based on depositing an undoped polysilicon film 28
on a silicon substrate having high resistivity 22 and then forming
a stack of oxide 24 and top silicon layer 26 on it. A
polycrystalline silicon layer 28 acts as a high defectivity layer
between the silicon substrate 22 and the buried oxide layer 24. See
FIG. 2, which depicts a polycrystalline silicon film for use as a
charge trapping layer 28 between a high resistivity substrate 22
and the buried oxide layer 24 in a silicon-on-insulator structure
20. An alternative method is the implantation of heavy ions to
create a near surface damage layer. Devices, such as radiofrequency
devices, are built in the top silicon layer 26.
It has been shown in academic studies that the polysilicon layer in
between of the oxide and substrate improves the device isolation,
decreases transmission line losses and reduces harmonic
distortions. See, for example: H. S. Gamble, et al. "Low-loss CPW
lines on surface stabilized high resistivity silicon," Microwave
Guided Wave Lett., 9(10), pp. 395-397, 1999; D. Lederer, R. Lobet
and J. -P. Raskin, "Enhanced high resistivity SOI wafers for RF
applications," IEEE Intl. SOI Conf, pp. 46-47, 2004; D. Lederer and
J. -P. Raskin, "New substrate passivation method dedicated to high
resistivity SOI wafer fabrication with increased substrate
resistivity," IEEE Electron Device Letters, vol. 26, no. 11, pp.
805-807, 2005; D. Lederer, B. Aspar, C. Laghae and J. -P. Raskin,
"Performance of RF passive structures and SOI MOSFETs transferred
on a passivated HR SOI substrate," IEEE International SOI
Conference, pp. 29-30, 2006; and Daniel C. Kerr et al.
"Identification of RF harmonic distortion on Si substrates and its
reduction using a trap-rich layer", Silicon Monolithic Integrated
Circuits in RF Systems, 2008. SiRF 2008 (IEEE Topical Meeting), pp.
151-154, 2008.
SUMMARY OF THE INVENTION
Among the provisions of the present invention may be noted a
multilayer structure comprising: a semiconductor handle substrate
comprising two major, generally parallel surfaces, one of which is
a front surface of the semiconductor handle substrate and the other
of which is a back surface of the semiconductor handle substrate, a
circumferential edge joining the front and back surfaces of the
semiconductor handle substrate, and a bulk region between the front
and back surfaces of the semiconductor handle substrate, wherein
the semiconductor handle substrate has a minimum bulk region
resistivity of at least about 500 ohm-cm; an interfacial layer in
contact with the front surface of the semiconductor handle
substrate; a carbon-doped amorphous silicon layer in contact with
the interfacial layer; a dielectric layer in contact with the
carbon-doped amorphous silicon layer; and a semiconductor device
layer in contact with the dielectric layer.
The present invention is further directed to a method of forming a
multilayer structure, the method comprising: forming an interfacial
layer on a front surface of a semiconductor handle substrate,
wherein the semiconductor handle substrate comprises two major,
generally parallel surfaces, one of which is the front surface of
the semiconductor handle substrate and the other of which is a back
surface of the semiconductor handle substrate, a circumferential
edge joining the front and back surfaces of the semiconductor
handle substrate, and a bulk region between the front and back
surfaces of the semiconductor handle substrate, wherein the
semiconductor handle substrate has a minimum bulk region
resistivity of at least about 500 ohm-cm and the interfacial layer
has a thickness between about 1 nanometer and about 5 nanometers;
forming a carbon-doped amorphous silicon layer on the interfacial
layer on the front surface of the semiconductor handle substrate;
and bonding a front surface of a semiconductor donor substrate to
the carbon-doped amorphous silicon layer to thereby form a bonded
structure, wherein the semiconductor donor substrate comprises two
major, generally parallel surfaces, one of which is the front
surface of the semiconductor donor substrate and the other of which
is a back surface of the semiconductor donor substrate, a
circumferential edge joining the front and back surfaces of the
semiconductor donor substrate, and a central plane between the
front and back surfaces of the semiconductor donor substrate, and
further wherein the front surface of the semiconductor donor
substrate comprises a dielectric layer.
Other objects and features will be in part apparent and in part
pointed out hereinafter.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a depiction of a silicon-on-insulator wafer comprising a
high resistivity substrate and a buried oxide layer.
FIG. 2 is a depiction of a silicon-on-insulator wafer according to
the prior art, the SOI wafer comprising a polysilicon charge
trapping layer between a high resistivity substrate and a buried
oxide layer.
FIG. 3 is a depiction of a high resistivity silicon-on-insulator
composite structure with an embedded carbon-doped amorphous silicon
layer.
FIG. 4A is a graph showing the boron concentration in the as
deposited carbon-doped amorphous silicon layer prior to any high
temperature process steps. The carbon-doped amorphous silicon layer
is approximately 2 micrometers thick. FIG. 4B is a graph showing
the boron concentration in the carbon-doped amorphous silicon layer
and high resisitivity substrate after a high temperature annealing
process.
FIGS. 5A and 5B are graphs showing the 2.sup.nd harmonic power and
3.sup.rd harmonic output power, respectively, measured on a
coplanar waveguide structure on an SOI substrate with a CTL of the
invention and on similar coplanar waveguide structure on an SOI
substrate without a CTL. The input power was +20 dBm at 900
MHz.
DETAILED DESCRIPTION OF THE EMBODIMENT(S) OF THE INVENTION
According to the present invention, a method is provided for
preparing a semiconductor-on-insulator composite structure
comprising a carbon-doped amorphous silicon layer on a
semiconductor handle substrate, e.g., a single crystal
semiconductor handle wafer, such as a single crystal silicon wafer.
The present invention is further directed to a semiconductor handle
wafer comprising a carbon-doped amorphous silicon layer on a
surface thereof. The single crystal semiconductor handle wafer
comprising the carbon-doped amorphous silicon layer is useful in
the production of a semiconductor-on-insulator (e.g.,
silicon-on-insulator) structure. The present invention is thus
further directed to a semiconductor-on-insulator composite
structure comprising a semiconductor handle wafer comprising a
carbon-doped amorphous silicon layer. The carbon-doped amorphous
silicon layer is located at the interface of the semiconductor
handle wafer and the dielectric layer, e.g., a buried oxide, or BOX
layer, which itself interfaces with a semiconductor device
layer.
According to the present invention, the carbon-doped amorphous
silicon layer is formed on a surface of a semiconductor handle
substrate, e.g., a single crystal silicon wafer, at the region near
the oxide interface. The incorporation of a carbon-doped amorphous
silicon layer at the region near the high resistivity semiconductor
wafer-buried oxide interface is advantageous since defects in the
carbon-doped amorphous silicon layer tend to have deep energy
levels. The carriers that are trapped deep in the bandgap require
more energy to be released, which enhances the effectiveness of a
carbon-doped amorphous silicon layer as a charge trapping layer.
Additionally, a carbon-doped amorphous silicon layer may be
prepared to be smoother than polycrystalline silicon charge
trapping layers, and the trap density in a carbon-doped amorphous
silicon layer is higher than in a polycrystalline silicon CTL.
Moreover, the carbon in the carbon-doped amorphous silicon layer
can form carbon clusters during subsequent high temperature process
steps. Carbon clusters may be capable of, e.g., inhibiting boron
activation, which helps reduce boron contamination induced RF
performance degradation.
The substrates for use in the present invention include a
semiconductor handle substrate, e.g., a single crystal
semiconductor handle wafer, and a semiconductor donor substrate,
e.g., a single crystal semiconductor donor wafer. FIG. 3 is a
depiction of an exemplary, non-limiting high resistivity
silicon-on-insulator composite structure with an embedded
carbon-doped amorphous silicon layer 110. The semiconductor device
layer 106 in a semiconductor-on-insulator composite structure 100
is derived from the single crystal semiconductor donor wafer. The
semiconductor device layer 106 may be transferred onto the
semiconductor handle substrate 102 by wafer thinning techniques
such as etching a semiconductor donor substrate or by cleaving a
semiconductor donor substrate comprising a damage plane. In
general, the single crystal semiconductor handle wafer and single
crystal semiconductor donor wafer comprise two major, generally
parallel surfaces. One of the parallel surfaces is a front surface
of the substrate, and the other parallel surface is a back surface
of the substrate. The substrates comprise a circumferential edge
joining the front and back surfaces, and a central plane between
the front and back surfaces. The substrates additionally comprise
an imaginary central axis perpendicular to the central plane and a
radial length that extends from the central axis to the
circumferential edge. In addition, because semiconductor
substrates, e.g., silicon wafers, typically have some total
thickness variation (TTV), warp, and bow, the midpoint between
every point on the front surface and every point on the back
surface may not precisely fall within a plane. As a practical
matter, however, the TTV, warp, and bow are typically so slight
that to a close approximation the midpoints can be said to fall
within an imaginary central plane which is approximately
equidistant between the front and back surfaces.
Prior to any operation as described herein, the front surface and
the back surface of the substrate may be substantially identical. A
surface is referred to as a "front surface" or a "back surface"
merely for convenience and generally to distinguish the surface
upon which the operations of method of the present invention are
performed. In the context of the present invention, a "front
surface" of a single crystal semiconductor handle substrate 102,
e.g., a single crystal silicon handle wafer, refers to the major
surface of the substrate that becomes an interior surface of the
bonded structure. It is upon this front surface that the
carbon-doped amorphous silicon layer 110 is formed. Accordingly, a
"back surface" of a single crystal semiconductor handle substrate,
e.g., a handle wafer, refers to the major surface that becomes an
exterior surface of the bonded structure. Similarly, a "front
surface" of a single crystal semiconductor donor substrate, e.g., a
single crystal silicon donor wafer, refers to the major surface of
the single crystal semiconductor donor substrate that becomes an
interior surface of the bonded structure, and a "back surface" of a
single crystal semiconductor donor substrate, e.g., a single
crystal silicon donor wafer, refers to the major surface that
becomes an exterior surface of the bonded structure. Upon
completion of conventional bonding and wafer thinning steps, the
single crystal semiconductor donor substrate forms the
semiconductor device layer 106 of the semiconductor-on-insulator
(e.g., silicon-on-insulator) composite structure.
The single crystal semiconductor handle substrate and the single
crystal semiconductor donor substrate may be single crystal
semiconductor wafers. In preferred embodiments, the semiconductor
wafers comprise a material selected from the group consisting of
silicon, silicon carbide, silicon germanium, gallium arsenide,
gallium nitride, indium phosphide, indium gallium arsenide,
germanium, and combinations thereof. The single crystal
semiconductor wafers, e.g., the single crystal silicon handle wafer
and single crystal silicon donor wafer, of the present invention
typically have a nominal diameter of at least about 150 mm, at
least about 200 mm, at least about 300 mm, at least about 450 mm,
or more. Wafer thicknesses may vary from about 250 micrometers to
about 1500 micrometers, suitably within the range of about 500
micrometers to about 1000 micrometers.
In particularly preferred embodiments, the single crystal
semiconductor wafers comprise single crystal silicon wafers which
have been sliced from a single crystal ingot grown in accordance
with conventional Czochralski crystal growing methods or float zone
growing methods. Such methods, as well as standard silicon slicing,
lapping, etching, and polishing techniques are disclosed, for
example, in F. Shimura, Semiconductor Silicon Crystal Technology,
Academic Press, 1989, and Silicon Chemical Etching, (J. Grabmaier
ed.) Springer-Verlag, N.Y., 1982 (incorporated herein by
reference). Preferably, the wafers are polished and cleaned by
standard methods known to those skilled in the art. See, for
example, W. C. O'Mara et al., Handbook of Semiconductor Silicon
Technology, Noyes Publications. If desired, the wafers can be
cleaned, for example, in a standard SC1/SC2 solution. In some
embodiments, the single crystal silicon wafers of the present
invention are single crystal silicon wafers which have been sliced
from a single crystal ingot grown in accordance with conventional
Czochralski ("Cz") crystal growing methods, typically having a
nominal diameter of at least about 150 mm, at least about 200 mm,
at least about 300 mm, at least about 450 mm, or more. Preferably,
both the single crystal silicon handle wafer and the single crystal
silicon donor wafer have mirror-polished front surface finishes
that are free from surface defects, such as scratches, large
particles, etc. Wafer thickness may vary from about 250 micrometers
to about 1500 micrometers, suitably within the range of about 500
micrometers to about 1000 micrometers. In some specific
embodiments, the wafer thickness may be about 725 micrometers.
In some embodiments, the single crystal semiconductor wafers, i.e.,
handle wafer and donor wafer, comprise interstitial oxygen in
concentrations that are generally achieved by the
Czochralski-growth method. In some embodiments, the semiconductor
wafers comprise oxygen in a concentration between about 4 PPMA and
about 18 PPMA. In some embodiments, the semiconductor wafers
comprise oxygen in a concentration between about 10 PPMA and about
35 PPMA. Interstitial oxygen may be measured according to SEMI MF
1188-1105.
In some embodiments, the semiconductor handle substrate 102, e.g.,
a single crystal semiconductor handle substrate, such as a single
crystal silicon handle wafer, has a relatively high minimum bulk
resistivity. High resistivity wafers are generally sliced from
single crystal ingots grown by the Czochralski method or float zone
method. Cz-grown silicon wafers may be subjected to a thermal
anneal at a temperature ranging from about 600.degree. C. to about
1000.degree. C. in order to annihilate thermal donors caused by
oxygen that are incorporated during crystal growth. In some
embodiments, the single crystal semiconductor handle wafer has a
minimum bulk resistivity of at least 100 Ohm-cm, such as between
about 100 Ohm-cm and about 100,000 Ohm-cm, or between about 500
Ohm-cm and about 100,000 Ohm-cm, or between about 1000 Ohm-cm and
about 100,000 Ohm-cm, or between about 500 Ohm-cm and about 10,000
Ohm-cm, or between about 750 Ohm-cm and about 10,000 Ohm-cm,
between about 1000 Ohm-cm and about 10,000 Ohm-cm, between about
2000 Ohm-cm and about 10,000 Ohm-cm, between about 3000 Ohm-cm and
about 10,000 Ohm-cm, or between about 3000 Ohm cm and about 5,000
Ohm-cm. Methods for preparing high resistivity wafers are known in
the art, and such high resistivity wafers may be obtained from
commercial suppliers, such as SunEdison Semiconductor Ltd. (St.
Peters, Mo.; formerly MEMC Electronic Materials, Inc.).
In some embodiments, the front surface of the semiconductor handle
wafer 102 is treated to form an interfacial layer prior 108 to
formation of the carbon-doped amorphous silicon layer 110. The
interfacial layer 108 may comprise a material selected from silicon
dioxide, silicon nitride, and silicon oxynitride. In some preferred
embodiments, the interfacial layer 108 may comprise silicon
dioxide. In order to form a silicon dioxide interfacial layer 108,
the front surface of the semiconductor handle wafer 102 is oxidized
prior to formation of the carbon-doped amorphous silicon layer 110
such that the front surface of the wafer comprises an oxide film.
In some embodiments, the oxide layer comprises silicon dioxide,
which may be formed by oxidizing the front surface of the
semiconductor handle substrate 102. This may be accomplished by
means known in the art, such as thermal oxidation (in which some
portion of the deposited semiconductor material film will be
consumed) or CVD oxide deposition. In some embodiments, the single
crystal semiconductor handle substrate 102, e.g., a single crystal
silicon handle wafer, may be thermally oxidized in a furnace such
as an ASM A400. The temperature may range from 750.degree. C. to
1200.degree. C. in an oxidizing ambient. The oxidizing ambient
atmosphere can be a mixture of inert gas, such as Ar or N.sub.2,
and O.sub.2. The oxygen content may vary from 1 to 10 percent, or
higher. In some embodiments, the oxidizing ambient atmosphere may
be up to 100% (a "dry oxidation"). In an exemplary embodiment,
semiconductor handle wafers may be loaded into a vertical furnace,
such as an A400. The temperature is ramped to the oxidizing
temperature with a mixture of N.sub.2 and O.sub.2. After the
desired oxide thickness has been obtained, the O.sub.2 is turned
off and the furnace temperature is reduced and wafers are unloaded
from the furnace. In order to incorporate nitrogen in the
interfacial layer to deposit silicon nitride or silicon oxynitride,
the atmosphere may comprise nitrogen alone or a combination of
oxygen and nitrogen, and the temperature may be increased to a
temperature between 1100.degree. C. and 1400.degree. C. An
alternative nitrogen source is ammonia. In some embodiments, the
interfacial layer 108 is formed on the front surface of the handle
substrate to provide a interfacial layer having an average
thickness between about 1 nanometer and about 5 nanometers, such as
between about 1 nanometers and about 4 nanometers, or between about
2 nanometers and about 4 nanometers.
In some embodiments, a carbon-doped amorphous silicon layer 110 is
deposited on the front surface of the semiconductor handle wafer
102. In some embodiments, a carbon-doped amorphous silicon layer
110 is deposited on an interfacial layer 108 comprising silicon
dioxide, silicon nitride, or silicon oxynitride on the front
surface of the semiconductor handle wafer. The carbon-doped
amorphous silicon layer 110 of the present invention may be
deposited by metalorganic chemical vapor deposition (MOCVD),
physical vapor deposition (PVD), chemical vapor deposition (CVD),
low pressure chemical vapor deposition (LPCVD), plasma enhanced
chemical vapor deposition (PECVD), or molecular beam epitaxy
(MBE).
In some preferred embodiments, carbon-doped amorphous silicon layer
110 of the present invention may be deposited by low pressure
chemical vapor deposition (LPCVD). LPCVD may be carried out in
commercially available instrumentation, such as the ASM Epsilon
reduced pressure CVD system. In LPCVD, gaseous precursors are
injected into a reactor, and chemical reaction between the
precursors deposit a layer of atoms onto a semiconductor wafer at
sub-atmospheric pressure. The pressure inside the LPCVD reactor
chamber may be between about 1 Torr and about 760 Torr, preferably
between about 1 Torr and about 40 Torr. Surface reaction of silicon
and carbon precursors creates conditions for growth. The growth
temperature may be between about 100.degree. C. and about
800.degree. C., such as between about 200.degree. C. and about
600.degree. C., preferably between about 300.degree. C. and about
500.degree. C.
In some preferred embodiments, carbon-doped amorphous silicon layer
110 of the present invention may be deposited by plasma enhanced
chemical vapor deposition (PECVD). PECVD may be carried out in
commercially available instrumentation, such as Applied Materials
Producer PECVD system. In PECVD, gaseous precursors are injected
into a reactor, and chemical reaction between the precursors in a
plasma deposit a layer of atoms onto a semiconductor wafer. Surface
reaction of silicon and carbon precursors creates conditions for
growth. Pressure in a PECVD reactor chamber may be between about
10.sup.-6 Torr (about 0.00013 kPa) and about 10 Torr (about 1.33
kPa), such as about 1 Torr (about 0.133 kPa). The growth
temperature may be between about 50.degree. C. and about
800.degree. C., such as between about 100.degree. C. and about
700.degree. C., preferably between about 100.degree. C. and about
500.degree. C.
Silicon precursors for LPCVD or PECVD include methyl silane,
silicon tetrahydride (silane), trisilane, disilane, pentasilane,
neopentasilane, tetrasilane, dichlorosilane (SiH.sub.2Cl.sub.2),
silicon tetrachloride (SiCl.sub.4), among others. Suitable carbon
precursors for CVD or PECVD include methylsilane, methane, ethane,
ethylene, among others. For LPCVD deposition, methylsilane is a
particularly preferred precursor since it provides both carbon and
silicon. For PECVD deposition, the preferred precursors include
silane and methane. In some embodiments, the carbon-doped amorphous
silicon layer comprises a carbon concentration of at least about 1%
on an atomic basis, such as between about 1% and about 10%.
A CVD reactor suitable for LPCVD or PECVD comprises a chamber
comprising reactor walls, liner, a susceptor, gas injection units,
and temperature control units. The parts of the reactor are made of
materials resistant to and non-reactive with the precursor
materials. To prevent overheating, cooling water may be flowing
through the channels within the reactor walls. A substrate sits on
a susceptor which is at a controlled temperature. The susceptor is
made from a material resistant to the metalorganic compounds used,
such as graphite. Reactive gas is introduced by an inlet that
controls the ratio of precursor reactants. Carrier gases, including
hydrogen, nitrogen, argon, and helium, preferably hydrogen or
argon, may be used. In PECVD, chemical reactions are involved in
the process, which occur after creation of a plasma of the reacting
gases. The plasma is generally created by RF (AC) frequency or DC
discharge between two electrodes, the space between which is filled
with the reacting gases. In some embodiments, the carbon-doped
amorphous silicon layer is deposited to an average thickness of
between about 25 nanometers and about 7500 nanometers, such as
between about 50 nanometers and about 5000 nanometers, such as
between about 100 nanometers and about 3000 nanometers, or between
about 500 nanometers and about 2500 nanometers.
After deposition of the carbon-doped amorphous silicon layer 110,
optionally a dielectric layer may be formed on top of the
carbon-doped amorphous silicon layer 110. In some embodiments, the
dielectric layer comprises an oxide film or a nitride film.
Suitable dielectric layers may comprise a material selected from
among silicon dioxide, silicon nitride, hafnium oxide, titanium
oxide, zirconium oxide, lanthanum oxide, barium oxide, and a
combination thereof. In some embodiments, the dielectric layer
comprises an oxide film. Such an oxide film may serve as a bonding
surface with an optionally oxidized semiconductor device substrate
and thus may be incorporated into the dielectric layer 104 in the
final semiconductor-on-insulator composite structure 100. In some
embodiments, the dielectric layer comprises silicon dioxide, which
may be formed by oxidizing the front surface of the semiconductor
handle substrate 102 comprises the carbon doped amorphous silicon
layer 110. This may be accomplished by means known in the art, such
as thermal oxidation (in which some portion of the deposited
semiconductor material film will be consumed) and/or CVD oxide
deposition. In some embodiments, the single crystal silicon handle
wafer 102 with carbon doped amorphous silicon layer 110 may be
thermally oxidized in a furnace such as an ASM A400. The
temperature may range from 750.degree. C. to 1100.degree. C. in an
oxidizing ambient. The oxidizing ambient atmosphere can be a
mixture of inert gas, such as Ar or N.sub.2, and O.sub.2. The
oxygen content may vary from 1 to 10 percent, or higher. In some
embodiments, the oxidizing ambient atmosphere may be up to 100% (a
"dry oxidation"). In some embodiments, the ambient atmosphere may
comprise a mixture of inert gas, such as Ar or N.sub.2, and
oxidizing gases, such as O.sub.2 and water vapor (a "wet
oxidation"). In an exemplary embodiment, semiconductor handle
wafers may be loaded into a vertical furnace, such as an A400. The
temperature is ramped to the oxidizing temperature with a mixture
of N.sub.2 and O.sub.2. At the desired temperature water vapor is
introduced into the gas flow. After the desired oxide thickness has
been obtained, the water vapor and O.sub.2 are turned off and the
furnace temperature is reduced and wafers are unloaded from the
furnace. In some embodiments, the handle substrates are oxidized to
provide an oxide layer between about 100 nanometers to about 5
micrometers, such as between about 500 nanometers and about 2
micrometers, or between about 700 nanometers and about 1
micrometer.
After oxide deposition, wafer cleaning is optional. If desired, the
wafers can be cleaned, for example, in a standard SC1/SC2 solution.
Additionally, the wafers may be subjected to chemical mechanical
polishing (CMP) to reduce the surface roughness, preferably to the
level of RMS.sub.2.times.2 um2 is less than about 50 angstroms,
even more preferably less than about 5 angstroms, wherein root mean
squared
.times..times..times. ##EQU00001## the roughness profile contains
ordered, equally spaced points along the trace, and y.sub.i is the
vertical distance from the mean line to the data point.
The semiconductor handle substrate 102, e.g. a single crystal
semiconductor handle wafer such as a single crystal silicon handle
wafer, prepared according to the method described herein to
comprise a carbon-doped amorphous silicon layer 110 and,
optionally, an oxide film, is next bonded a semiconductor donor
substrate, e.g., a single crystal semiconductor donor wafer, which
is prepared according to conventional layer transfer methods. That
is, the single crystal semiconductor donor wafer may be subjected
to standard process steps including oxidation, implant, and post
implant cleaning. Accordingly, a semiconductor donor substrate,
such as a single crystal semiconductor wafer of a material that is
conventionally used in preparation of multilayer semiconductor
structures, e.g., a single crystal silicon donor wafer, that has
been etched and polished and optionally oxidized, is subjected to
ion implantation to form a damage layer in the donor substrate. In
some embodiments, the semiconductor donor substrate comprises a
dielectric layer. Suitable dielectric layers may comprise a
material selected from among silicon dioxide, silicon nitride,
hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide,
barium oxide, and a combination thereof. In some embodiments, the
dielectric layer comprises an oxide layer having a thickness from
about 10 nanometers to about 500 nanometers, such as between about
100 nanometers and about 400 nanometers.
Ion implantation may be carried out in a commercially available
instrument, such as an Applied Materials Quantum II. Implanted ions
include He, H, H.sub.2, or combinations thereof. Ion implantation
is carried out as a density and duration sufficient to form a
damage layer in the semiconductor donor substrate. Implant density
may range from about 10.sup.12 ions/cm.sup.2 to about 10.sup.16
ions/cm.sup.2. Implant energies may range from about 1 keV to about
3,000 keV. In some embodiments it may be desirable to subject the
single crystal semiconductor donor wafers, e.g., single crystal
silicon donor wafers, to a clean after the implant. In some
preferred embodiments, the clean could include a Piranha clean
followed by a DI water rinse and SC1/SC2 cleans.
In some embodiments, the ion-implanted and optionally cleaned
single crystal semiconductor donor substrate is subjected to oxygen
plasma and/or nitrogen plasma surface activation. In some
embodiments, the oxygen plasma surface activation tool is a
commercially available tool, such as those available from EV Group,
such as EVG.RTM.810LT Low Temp Plasma Activation System. The
ion-implanted and optionally cleaned single crystal semiconductor
donor wafer is loaded into the chamber. The chamber is evacuated
and backfilled with O.sub.2 to a pressure less than atmospheric to
thereby create the plasma. The single crystal semiconductor donor
wafer is exposed to this plasma for the desired time, which may
range from about 1 second to about 120 seconds. Oxygen plasma
surface oxidation is performed in order to render the front surface
of the single crystal semiconductor donor substrate hydrophilic and
amenable to bonding to a single crystal semiconductor handle
substrate prepared according to the method described above.
The hydrophilic front surface layer of the single crystal
semiconductor donor substrate and the front surface of the single
crystal semiconductor handle substrate, which is optionally
oxidized, are next brought into intimate contact to thereby form a
bonded structure. Since the mechanical bond is relatively weak, the
bonded structure is further annealed to solidify the bond between
the donor wafer and the handle wafer. In some embodiments of the
present invention, the bonded structure is annealed at a
temperature sufficient to form a thermally activated cleave plane
in the single crystal semiconductor donor substrate. An example of
a suitable tool might be a simple Box furnace, such as a Blue M
model. In some preferred embodiments, the bonded structure is
annealed at a temperature of from about 200.degree. C. to about
350.degree. C., from about 225.degree. C. to about 325.degree. C.,
preferably about 300.degree. C. Thermal annealing may occur for a
duration of from about 0.5 hours to about 10 hour, preferably a
duration of about 2 hours. Thermal annealing within these
temperatures ranges is sufficient to form a thermally activated
cleave plane. After the thermal anneal to activate the cleave
plane, the bonded structure may be cleaved.
After the thermal anneal, the bond between the single crystal
semiconductor donor substrate and the single crystal semiconductor
handle substrate is strong enough to initiate layer transfer via
cleaving the bonded structure at the cleave plane. Cleaving may
occur according to techniques known in the art. In some
embodiments, the bonded structure may be placed in a conventional
cleave station affixed to stationary suction cups on one side and
affixed by additional suction cups on a hinged arm on the other
side. A crack is initiated near the suction cup attachment and the
movable arm pivots about the hinge cleaving the wafer apart.
Cleaving removes a portion of the semiconductor donor wafer,
thereby leaving a semiconductor device layer, preferably a silicon
device layer, on the semiconductor-on-insulator composite
structure.
After cleaving, the cleaved structure is subjected to a high
temperature anneal in order to further strengthen the bond between
the transferred device layer and the single crystal semiconductor
handle substrate. An example of a suitable tool might be a vertical
furnace, such as an ASM A400. In some preferred embodiments, the
bonded structure is annealed at a temperature of from about
1000.degree. C. to about 1200.degree. C., preferably at about
1000.degree. C. Thermal annealing may occur for a duration of from
about 0.5 hours to about 8 hours, preferably a duration of about 4
hours. Thermal annealing within these temperatures ranges is
sufficient to strengthen the bond between the transferred device
layer and the single crystal semiconductor handle substrate.
After the cleave and high temperature anneal, the bonded structure
may be subjected to a cleaning process designed to remove thin
thermal oxide and clean particulates from the surface. In some
embodiments, the single crystal semiconductor donor wafer may be
brought to the desired thickness and smoothness by subjecting to a
vapor phase HCl etch process in a horizontal flow single wafer
epitaxial reactor using H.sub.2 as a carrier gas. In some
embodiments, an epitaxial layer may be deposited on the transferred
device layer. The finished SOI wafer comprises the semiconductor
handle substrate, the carbon-doped amorphous silicon layer, the
dielectric layer (e.g., buried oxide layer), and the semiconductor
device layer, may then be subjected to end of line metrology
inspections and cleaned a final time using typical SC1-SC2
process.
According to the present invention, and with reference to FIG. 3, a
semiconductor-on-insulator composite structure 100 is obtained with
the carbon-doped amorphous silicon layer 110 forming an interface
with an interfacial layer 108 and with a dielectric layer 104. The
interfacial layer 108 is in interface with a semiconductor handle
substrate 102, e.g. a single crystal semiconductor handle wafer
such as a single crystal silicon handle wafer. The dielectric layer
104 is in interface with a semiconductor device layer 106. The
dielectric layer 104 may comprise a buried oxide, or BOX. The
carbon-doped amorphous silicon layer 110 is in interface with the
dielectric layer 104 in a semiconductor-on-insulator composite
structure 100 can be effective for preserving charge trapping
efficiency of the films during high temperature treatments.
Having described the invention in detail, it will be apparent that
modifications and variations are possible without departing from
the scope of the invention defined in the appended claims.
EXAMPLES
The following non-limiting examples are provided to further
illustrate the present invention.
Example 1. Silicon-On-Insulator Structure Comprising Carbon-Doped
Amorphous Silicon Charge Trapping Layer
A semiconductor on insulator composite structure 100 of the
invention is illustrated in FIG. 3. The SOI structure 100 comprises
a high resistivity silicon substrate 102, a buried oxide layer 104,
and a silicon device layer 106. At the interface of the high
resistivity silicon substrate 102 and the buried oxide layer 104 is
a silicon dioxide layer 108 and a carbon-doped amorphous silicon
layer 110. The silicon dioxide layer 108 and carbon-doped amorphous
silicon layer 110 are deposited in a chemical vapor deposition
(CVD) system.
First, a thin silicon dioxide layer 108 is deposited on a high
resistivity silicon substrate 102 to a thickness of less than about
4 nanometers. The thin silicon dioxide layer 108 may be deposited
by oxygen plasma, chemical oxidation, or thermal oxidation. The
silicon dioxide layer 108 is useful for preventing the carbon-doped
amorphous silicon layer 110 from re-crystallizing during subsequent
high temperature processing.
After the formation of the silicon dioxide layer 108, a
carbon-doped amorphous silicon layer 110 is deposited in a reduced
pressure chemical vapor deposition (CVD) system. After that, the
carbon-doped amorphous silicon layer 110 is capped by a thick
buried oxide layer 104. The buried oxide layer 104 can be SiO.sub.2
deposited by PECVD, LPCVD, or grown in a thermal oxidation furnace.
The total thickness of the buried oxide layer 104 is about 7600 A.
A conventional donor wafer with about 2400 A SiO.sub.2 can then be
implanted and bonded to the high resistivity silicon substrate 102
with conventional method. The semiconductor on insulator composite
structure 100 is then heat treated, cleaved, and gone through
multiple thermal processes to reach the end of line with standard
process flow.
Example 2. RF Performance of Boron-Contaminated
Silicon-On-Insulator Structure Comprising Carbon-Doped Amorphous
Silicon Charge Trapping Layer
The boron concentration in a carbon-doped amorphous silicon layer
prepared on a high resistivity substrate was measured by secondary
ion mass spectrometry. See FIGS. 4A and 4B. FIG. 4A is a graph
showing the boron concentration in the as deposited carbon-doped
amorphous silicon layer prior to any high temperature process
steps. The carbon-doped amorphous silicon layer is approximately 2
micrometers thick. FIG. 4B is a graph showing the boron
concentration in the carbon-doped amorphous silicon layer and high
resisitivity substrate after a high temperature annealing process.
Since boron diffused into the high resistivity substrate during the
anneal, the resistivity of the substrate decreased. The decrease in
resistivity would be expected to result in a decline in RF
performance. However, the measured RF performance did not decline
in SOI structures comprising a high resistivity substrate
comprising a carbon-doped amorphous silicon layer compared to a SOI
structure lacking a carbon-doped amorphous silicon layer. See FIGS.
5A and 5B, which show the 2.sup.nd harmonic power and 3.sup.rd
harmonic output power, respectively, measured on SOI structures
with an input power of +20 dBm at 900 MHz.
When introducing elements of the present invention or the preferred
embodiments(s) thereof, the articles "a", "an", "the" and "said"
are intended to mean that there are one or more of the elements.
The terms "comprising", "including" and "having" are intended to be
inclusive and mean that there may be additional elements other than
the listed elements.
In view of the above, it will be seen that the several objects of
the invention are achieved and other advantageous results
attained.
As various changes could be made in the above products and methods
without departing from the scope of the invention, it is intended
that all matter contained in the above description and shown in the
accompanying drawings shall be interpreted as illustrative and not
in a limiting sense.
* * * * *