U.S. patent number 9,425,098 [Application Number 14/621,703] was granted by the patent office on 2016-08-23 for radio-frequency device package and method for fabricating the same.
This patent grant is currently assigned to MEDIATEK INC.. The grantee listed for this patent is MediaTek Inc.. Invention is credited to Wei-Che Huang, Yu-Hua Huang, Cheng-Chou Hung, Tung-Hsing Lee, Ming-Tzong Yang.
United States Patent |
9,425,098 |
Yang , et al. |
August 23, 2016 |
Radio-frequency device package and method for fabricating the
same
Abstract
A method for fabricating a electronic device package provides a
electronic device chip, wherein the electronic device chip includes
a semiconductor substrate having a front side and a back side,
wherein the semiconductor substrate has a first thickness, an
electronic component disposed on the front side of the
semiconductor substrate, and an interconnect structure disposed on
the electronic component. The method further performs a thinning
process to remove a portion of the semiconductor substrate from the
back side thereof. The method then removes a portion of the thinned
semiconductor substrate and a portion of a dielectric layer of the
interconnect structure from a back side of the thinned
semiconductor substrate until a first metal layer pattern of the
interconnect structure is exposed, thereby forming a through hole.
Finally, the method forms a TSV structure in the through hole, and
mounts the electronic device chip on a base.
Inventors: |
Yang; Ming-Tzong (Baoshan
Township, Hsinchu County, TW), Hung; Cheng-Chou
(Hukou Township, Hsinchu County, TW), Lee; Tung-Hsing
(New Taipei, TW), Huang; Wei-Che (Zhudong Township,
Hsinchu County, TW), Huang; Yu-Hua (Hsinchu,
TW) |
Applicant: |
Name |
City |
State |
Country |
Type |
MediaTek Inc. |
Hsin-Chu |
N/A |
TW |
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Assignee: |
MEDIATEK INC. (Hsin-Chu,
TW)
|
Family
ID: |
50232412 |
Appl.
No.: |
14/621,703 |
Filed: |
February 13, 2015 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20150162242 A1 |
Jun 11, 2015 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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13790060 |
Mar 8, 2013 |
|
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61698450 |
Sep 7, 2012 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
21/76898 (20130101); H01L 23/481 (20130101); H01L
23/66 (20130101); H01L 21/268 (20130101); H01L
21/30625 (20130101); H01L 31/18 (20130101); H01L
21/02107 (20130101); H01L 24/13 (20130101); H01L
23/5227 (20130101); H01L 24/11 (20130101); H01L
2224/131 (20130101); H01L 2224/16225 (20130101); H01L
24/16 (20130101); H01L 2223/6616 (20130101); H01L
2224/16227 (20130101); H01L 2924/11 (20130101); H01L
2924/12042 (20130101); H01L 2224/13025 (20130101); H01L
2224/131 (20130101); H01L 2924/014 (20130101); H01L
2224/131 (20130101); H01L 2924/00014 (20130101); H01L
2924/12042 (20130101); H01L 2924/00 (20130101) |
Current International
Class: |
H01L
23/00 (20060101); H01L 31/18 (20060101); H01L
21/768 (20060101); H01L 21/268 (20060101); H01L
23/66 (20060101); H01L 21/02 (20060101); H01L
23/48 (20060101); H01L 23/522 (20060101); H01L
21/306 (20060101) |
Field of
Search: |
;438/125 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Hossain; Moazzam
Attorney, Agent or Firm: McClure, Qualey & Rodack,
LLP
Parent Case Text
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a divisional of U.S. patent application Ser.
No. 13/790,060, filed on Mar. 8, 2013, now U.S. Pat. No. 8,987,851,
which claims the benefit of U.S. Provisional Application No.
61/698,450, filed on Sep. 7, 2012, the entireties of which are
incorporated by reference herein.
Claims
What is claimed is:
1. A method for fabricating an electronic device package,
comprising: providing a electronic device chip, wherein the
electronic device chip comprises: a semiconductor substrate having
a front side and a back side, wherein the semiconductor substrate
has a first thickness; an electronic component disposed on the
front side of the semiconductor substrate; and an interconnect
structure disposed on the electronic component, wherein the
interconnect structure is electrically connected to the electronic
component; performing a thinning process to remove a portion of the
semiconductor substrate from the back side thereof, thereby forming
a thinned semiconductor substrate having a second thickness less
than the first thickness; removing a portion of the thinned
semiconductor substrate and a portion of a dielectric layer of the
interconnect structure from a back side of the thinned
semiconductor substrate until a first metal layer pattern of the
interconnect structure is exposed, thereby forming a through hole;
and forming a TSV structure in the through hole; and mounting the
electronic device chip on a base, wherein the back side of the
thinned semiconductor substrate is closer to the base than a front
side of the thinned semiconductor substrate.
2. The method for fabricating the electronic device package as
claimed in claim 1, wherein forming the TSV structure comprises:
forming an insulating liner on a bottom and a sidewall of the
through hole; performing an etching process to remove the
insulating liner on the bottom of the through hole; and filling a
conductive material in the through hole to form a conductive via
plug.
3. The method for fabricating the electronic device package as
claimed in claim 1, further comprising: forming a conductive bump
on an end of the TSV structure in close proximity to the back side
of the thinned semiconductor substrate before mounting the
semiconductor device on the base.
4. The method for fabricating the electronic device package as
claimed in claim 3, wherein the conductive bump is connected to the
base after mounting the semiconductor device on the base.
5. The method for fabricating the electronic device package as
claimed in claim 2, wherein the etching process comprises a dry
etching process or a wet etching process.
6. The method for fabricating the electronic device package as
claimed in claim 1, wherein the second thickness is between 20
.mu.m to 50 .mu.m.
7. The method for fabricating the electronic device package as
claimed in claim 1, wherein the interconnect structure has the
first metal layer pattern at a below-to-top level and a second
metal layer pattern at a top level, and the TSV structure is
directly connected to the first metal layer pattern at the
below-to-top level.
8. The method for fabricating the electronic device package as
claimed in claim 7, wherein the electronic device chip further
comprises a passive component disposed in the interconnect
structure comprising the second metal layer pattern at the top
level.
9. The method for fabricating the electronic device package as
claimed in claim 1, wherein the thinning process comprises a
chemical mechanical polishing process.
10. The method for fabricating the electronic device package as
claimed in claim 1, wherein the through hole is formed by a laser
drilling process.
11. The method for fabricating the electronic device package as
claimed in claim 1, wherein the interconnect structure has a third
thickness, and the second thickness is less than the third
thickness.
12. The method for fabricating the electronic device package as
claimed in claim 1, wherein the electronic device package is a
radio-frequency (RF) device package, the electronic device chip is
an RF device chip, and the electronic component is an RF component.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a radio-frequency (RF) device
package and a method for fabricating the same, and in particular,
to a radio-frequency (RF) device package with improved RF loss and
linearity performances and a method for fabricating the same.
2. Description of the Related Art
In high speed applications (e.g. radio-frequency (RF)
applications), the conventional RF device package comprises several
discrete RF chips and other active or passive devices (such as
power amplifiers (PAs), filters, decoupling and matching circuits)
mounted on an RF main die by a wire bonding method. However, the
conventional RF device package suffers from loss and low linearity
problems because ground (GND) planes of the wire-bonding RF chips
are designed to contact to the RF main die.
Thus, a novel RF device package with improved RF loss and linearity
performances is desirable.
BRIEF SUMMARY OF THE INVENTION
A radio-frequency (RF) device package and a method for fabricating
the same are provided. An exemplary embodiment of a radio-frequency
(RF) device package includes a base, wherein a radio-frequency (RF)
device chip is mounted on the base. The RF device chip includes a
semiconductor substrate having a front side and a back side. A
radio-frequency (RF) component is disposed on the front side of the
semiconductor substrate. An interconnect structure is disposed on
the RF component, wherein the interconnect structure is
electrically connected to the RF component, and a thickness of the
semiconductor substrate is less than that of the interconnect
structure. A through hole is formed through the semiconductor
substrate from the back side of the semiconductor substrate, and is
connected to the interconnect structure. A TSV structure is
disposed in the through hole.
An exemplary embodiment of a method for fabricating a
radio-frequency (RF) device package includes providing a
radio-frequency (RF) device chip. The RF device chip includes a
semiconductor substrate having a front side and a back side,
wherein the semiconductor substrate has a first thickness. A
radio-frequency (RF) component is disposed on the front side of the
semiconductor substrate. An interconnect structure is disposed on
the RF component, wherein the interconnect structure is
electrically connected to the RF component. A thinning process is
performed to remove a portion of the semiconductor substrate from
the back side thereof, thereby forming a thinned semiconductor
substrate having a second thickness less than the first thickness.
A portion of the thinned semiconductor substrate and a portion of a
dielectric layer of the interconnect structure are removed from a
back side of the thinned semiconductor substrate until a first
metal layer pattern of the interconnect structure is exposed,
thereby forming a through hole. A TSV structure is formed in the
through hole. The RF device chip is mounted on a base, wherein the
back side of the thinned semiconductor substrate is closer to the
base than a front side of the thinned semiconductor substrate.
A detailed description is given in the following embodiments with
reference to the accompanying drawings.
BRIEF DESCRIPTION OF DRAWINGS
The invention can be more fully understood by reading the
subsequent detailed description and examples with references made
to the accompanying drawings, wherein:
FIGS. 1-7 are cross sections of one exemplary embodiment of a
method for fabricating a radio-frequency (RF) device package of the
invention.
DETAILED DESCRIPTION OF INVENTION
The following description is a mode for carrying out the invention.
This description is made for the purpose of illustrating the
general principles of the invention and should not be taken in a
limiting sense. The scope of the invention is best determined by
reference to the appended claims. Wherever possible, the same
reference numbers are used in the drawings and the descriptions to
refer the same or like parts.
The present invention will be described with respect to particular
embodiments and with reference to certain drawings, but the
invention is not limited thereto and is only limited by the claims.
The drawings described are only schematic and are non-limiting. In
the drawings, the size of some of the elements may be exaggerated
and not drawn to scale for illustrative purposes. The dimensions
and the relative dimensions do not correspond to actual dimensions
to practice the invention.
FIGS. 1-7 are cross sections of one exemplary embodiment of a
method for fabricating a radio-frequency (RF) device package 500 of
the invention. In this embodiment, the RF device package 500 is
fabricated with through silicon via (TSV) technology. As shown in
FIG. 1, a radio-frequency (RF) device chip 300 is provided. In one
embodiment, the RF device chip 300 may comprise a semiconductor
substrate 200 having a front side 222 and a back side 224. In one
embodiment, the semiconductor substrate 200 may comprise silicon.
In alternative embodiments, a SiGe, bulk semiconductor, strained
semiconductor, compound semiconductor, silicon on insulator (SOI),
or other commonly used semiconductor substrates are used as the
semiconductor substrate 200. The semiconductor substrate 200 may
have a desired conductive type by implanting p-type or n-type
impurities therein. A radio-frequency (RF) component 202 is
disposed on the front side 222 of the semiconductor substrate 200.
As shown in FIG. 1, the RF component 202 is isolated from the other
devices (not shown) by shallow trench isolation (STI) features 201
formed in the semiconductor substrate 200. An interconnect
structure 220 is formed on the front side 201 of the semiconductor
substrate 200. In one embodiment, the interconnect structure 220
may be constructed by dielectric layers 204, 208, and 212 and metal
layer patterns 206, and 210. The interconnect structure 220 may be
used for input/output (I/O) connections of signals or a ground
(GND) for the RF component 202. Therefore, signals or ground (GND)
terminals may be formed in the interconnect structure 220. In one
embodiment, the metal layer patterns 206, and 210 of the
interconnect structure 220 are electrically connected to the RF
component 202. In one embodiment as shown in FIG. 1, the metal
layer patterns 210 are disposed at a top level and the metal layer
patterns 206 are disposed at a lower-to-top level of the
interconnect structure 220. The number of the dielectric layers and
metal layer patterns is defined by design for the RF component 202
and the scope of the invention is not limited thereto. In one
embodiment as shown in FIG. 1, a thickness T1 of the semiconductor
substrate 200 is larger than a thickness T2 of the interconnect
structure 220.
Next, as shown in FIG. 2, the RF device chip 300 may be flipped so
that the back side 224 of the semiconductor substrate 200 is facing
upward. Next, a thinning process is performed to remove a portion
of the semiconductor substrate 200 (as shown in FIG. 1) from the
back side 224 (as shown in FIG. 1) of the semiconductor substrate
200 to reduce a thickness of the semiconductor substrate 200. In
one embodiment, the thinning process may comprise a chemical
mechanical polishing (CMP) process. After performing the thinning
process, a thinned semiconductor substrate 200a is formed. In one
embodiment, the thinned semiconductor substrate 200a has a
thickness T3 less than the thickness T1 of the semiconductor
substrate 200 as shown in FIG. 1. In this embodiment, the thickness
T3 of the thinned semiconductor substrate 200a may be designed to
be between 20 nm to 50 nm to prevent the semiconductor substrate
200a from cracking. Also, the thickness T3 of the thinned
semiconductor substrate 200a may be designed to be less than the
thickness T2 of the interconnect structure 220.
Next, a TSV process is performed for the RF device chip 300 as
shown in FIGS. 3-5. As shown in FIG. 3, a trench opening process,
such as a laser drilling process, is performed to remove a portion
of the thinned semiconductor substrate 200a and a portion of the
dielectric layer 204 of the interconnect structure from a back side
224a of the thinned semiconductor substrate 200a until the metal
layer patterns 206 of the interconnect structure 220 is exposed,
thereby forming through holes 230. In one embodiment, the through
holes 230 define formation positions of subsequently formed TSV
structures.
Next, as shown in FIG. 4, an insulating liner 236 is conformably
formed on a bottom 234 and a sidewall 232 of each of the through
holes 230 by a disposition, photolithography and patterning
process. Also, the insulating liner 236 covers a portion of the
metal layer patterns 206 of the interconnect structure 220.
Next, as shown in FIG. 5, an etching process is performed to remove
the insulating liner 236 on the bottom 234 of the through hole 230,
thereby forming an insulating liner 236a. In one embodiment, the
etching process may comprise a dry etching process or a wet etching
process. Next, a conductive material is filled in the through hole
230 to form a conductive via plug 238. As shown in FIG. 5, the
conductive via plug 238 covers a sidewall of the insulating liner
236. After forming the conductive via plug 238, a TSV structure 240
comprises the insulating liner 236a and the conductive via plug 238
surrounded by the insulating liner 236a is formed in the through
hole 230. In this embodiment, the TSV structure 240 is electrically
connected to the metal layer patterns 206 at the lower-to-top level
of the interconnect structure 220.
Next, as shown in FIG. 6, a bumping process is performed to form a
conductive bump 242 on an end 241 of the TSV structure 240 close to
the back side 224a of the thinned semiconductor substrate 200a. In
one embodiment, the conductive bump 242 may comprise a solder bump,
metal pillar or combinations thereof.
Next, as shown in FIG. 7, the RF device chip 300 may be flipped
again so that the back side 224 of the semiconductor substrate 200
faces downward. Next, a mounting process is performed to mount the
RF device chip 300 on a base 250. As shown in FIG. 7, the
conductive bump 242 connects to the base 250 after mounting the RF
device chip 300 on the base 250. In one embodiment, the base 250
may comprise a main die or a printed circuit board (PCB). In one
embodiment, the back side 224a of the thinned semiconductor
substrate 200a is closer to the base 250 than the front side 222 of
the thinned semiconductor substrate 200a. A distance d between the
RF component 202 and the base 250 is the same as a total thickness
T3 of the thinned semiconductor substrate 200a and the height H of
the conductive bump 242. After the aforementioned processes, one
exemplary embodiment of a radio-frequency (RF) device package 500
is fabricated completely.
Alternatively, the RF device chip 300 the radio-frequency (RF)
device package 500 may further comprise a passive component 246
disposed in the interconnect structure 220. In one embodiment, the
passive component 246 comprises the metal layer patterns 210 at the
top level of the interconnect structure 220.
Embodiments provide a radio-frequency (RF) device package 500. In
one embodiment, the RF device package uses a thinning process and a
TSV process for the RF device chip. A TSV structure adopted by the
RF device chip can achieve a higher density and a shorter
connection than the conventional bonding wire. Compared with the
conventional wire bonding device package, one exemplary embodiment
of the RF device package may have a lower interconnection
resistance due to the TSV structure for the RF device chip. Also,
signal or ground (GND) terminals may be formed in the interconnect
structure 220 of the RF device package. Therefore, one exemplary
embodiment of the RF device package is fabricated without requiring
a GND plane, which is used in the conventional wire bonding device
package, designed to be disposed on a backside of the RF device
package and contacting to the base. Accordingly, the RF device
package can avoid disadvantages of the RF performance degradation
of the conventional wire bonding device package due to the GND
plane contacting to the base. Additionally, a back side of the RF
device package is designed to be disposed closer to the base than
the front side thereof. Therefore, one exemplary embodiment of the
RF device package may provide a higher position for passive
components than the conventional flip chip package. Interference
from the base to the passive components can be reduced, so that the
RF device package can achieve superior RF performances of, for
example, low loss and high linearity.
While the invention has been described by way of example and in
terms of the preferred embodiments, it is to be understood that the
invention is not limited to the disclosed embodiments. On the
contrary, it is intended to cover various modifications and similar
arrangements (as would be apparent to those skilled in the art).
Therefore, the scope of the appended claims should be accorded the
broadest interpretation so as to encompass all such modifications
and similar arrangements.
* * * * *